1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21
22class BoolToList<bit Value> {
23  list<int> ret = !if(Value, [1]<int>, []<int>);
24}
25
26//===------------------------------------------------------------===//
27// Subtarget Features (device properties)
28//===------------------------------------------------------------===//
29
30def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
31  "FastFMAF32",
32  "true",
33  "Assuming f32 fma is at least as fast as mul + add"
34>;
35
36def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
37  "FastDenormalF32",
38  "true",
39  "Enabling denormals does not cause f32 instructions to run at f64 rates"
40>;
41
42def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
43  "MIMG_R128",
44  "true",
45  "Support 128-bit texture resources"
46>;
47
48def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
49  "HalfRate64Ops",
50  "true",
51  "Most fp64 instructions are half rate instead of quarter"
52>;
53
54def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
55  "FlatAddressSpace",
56  "true",
57  "Support flat address space"
58>;
59
60def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
61  "FlatInstOffsets",
62  "true",
63  "Flat instructions have immediate offset addressing mode"
64>;
65
66def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
67  "FlatGlobalInsts",
68  "true",
69  "Have global_* flat memory instructions"
70>;
71
72def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
73  "FlatScratchInsts",
74  "true",
75  "Have scratch_* flat memory instructions"
76>;
77
78def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
79  "ScalarFlatScratchInsts",
80  "true",
81  "Have s_scratch_* flat memory instructions"
82>;
83
84def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
85  "AddNoCarryInsts",
86  "true",
87  "Have VALU add/sub instructions without carry out"
88>;
89
90def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
91  "UnalignedBufferAccess",
92  "true",
93  "Support unaligned global loads and stores"
94>;
95
96def FeatureTrapHandler: SubtargetFeature<"trap-handler",
97  "TrapHandler",
98  "true",
99  "Trap handler support"
100>;
101
102def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
103  "UnalignedScratchAccess",
104  "true",
105  "Support unaligned scratch loads and stores"
106>;
107
108// LDS alignment enforcement is controlled by a configuration register:
109// SH_MEM_CONFIG.alignment_mode
110def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode",
111  "UnalignedAccessMode",
112  "true",
113  "Support unaligned local and region loads and stores"
114>;
115
116def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access",
117  "UnalignedDSAccess",
118  "true",
119  "Does not requires 16 byte alignment for certain local and region loads and stores"
120>;
121
122def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
123  "HasApertureRegs",
124  "true",
125  "Has Memory Aperture Base and Size Registers"
126>;
127
128def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
129  "HasMadMixInsts",
130  "true",
131  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
132>;
133
134def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
135  "HasFmaMixInsts",
136  "true",
137  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
138>;
139
140def FeatureDoesNotSupportXNACK : SubtargetFeature<"no-xnack-support",
141  "DoesNotSupportXNACK",
142  "true",
143  "Hardware does not support XNACK"
144>;
145
146// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
147// XNACK. The current default kernel driver setting is:
148// - graphics ring: XNACK disabled
149// - compute ring: XNACK enabled
150//
151// If XNACK is enabled, the VMEM latency can be worse.
152// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
153def FeatureXNACK : SubtargetFeature<"xnack",
154  "EnableXNACK",
155  "true",
156  "Enable XNACK support"
157>;
158
159def FeatureCuMode : SubtargetFeature<"cumode",
160  "EnableCuMode",
161  "true",
162  "Enable CU wavefront execution mode"
163>;
164
165def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
166  "SGPRInitBug",
167  "true",
168  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
169>;
170
171def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
172  "LDSMisalignedBug",
173  "true",
174  "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode"
175>;
176
177def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
178  "HasMFMAInlineLiteralBug",
179  "true",
180  "MFMA cannot use inline literal as SrcC"
181>;
182
183def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
184  "HasVcmpxPermlaneHazard",
185  "true",
186  "TODO: describe me"
187>;
188
189def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
190  "HasVMEMtoScalarWriteHazard",
191  "true",
192  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
193>;
194
195def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
196  "HasSMEMtoVectorWriteHazard",
197  "true",
198  "s_load_dword followed by v_cmp page faults"
199>;
200
201def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
202  "HasInstFwdPrefetchBug",
203  "true",
204  "S_INST_PREFETCH instruction causes shader to hang"
205>;
206
207def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
208  "HasVcmpxExecWARHazard",
209  "true",
210  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
211>;
212
213def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
214  "HasLdsBranchVmemWARHazard",
215  "true",
216  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
217>;
218
219def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
220  "HasNSAtoVMEMBug",
221  "true",
222  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
223>;
224
225def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
226  "HasFlatSegmentOffsetBug",
227  "true",
228  "GFX10 bug, inst_offset ignored in flat segment"
229>;
230
231def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
232  "HasOffset3fBug",
233  "true",
234  "Branch offset of 3f hardware bug"
235>;
236
237class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
238  "ldsbankcount"#Value,
239  "LDSBankCount",
240  !cast<string>(Value),
241  "The number of LDS banks per compute unit."
242>;
243
244def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
245def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
246
247def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
248  "GCN3Encoding",
249  "true",
250  "Encoding format for VI"
251>;
252
253def FeatureCIInsts : SubtargetFeature<"ci-insts",
254  "CIInsts",
255  "true",
256  "Additional instructions for CI+"
257>;
258
259def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
260  "GFX8Insts",
261  "true",
262  "Additional instructions for GFX8+"
263>;
264
265def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
266  "GFX9Insts",
267  "true",
268  "Additional instructions for GFX9+"
269>;
270
271def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
272  "GFX10Insts",
273  "true",
274  "Additional instructions for GFX10+"
275>;
276
277def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts",
278  "GFX10_3Insts",
279  "true",
280  "Additional instructions for GFX10.3"
281>;
282
283def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
284  "GFX7GFX8GFX9Insts",
285  "true",
286  "Instructions shared in GFX7, GFX8, GFX9"
287>;
288
289def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
290  "HasSMemRealTime",
291  "true",
292  "Has s_memrealtime instruction"
293>;
294
295def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
296  "HasInv2PiInlineImm",
297  "true",
298  "Has 1 / (2 * pi) as inline immediate"
299>;
300
301def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
302  "Has16BitInsts",
303  "true",
304  "Has i16/f16 instructions"
305>;
306
307def FeatureVOP3P : SubtargetFeature<"vop3p",
308  "HasVOP3PInsts",
309  "true",
310  "Has VOP3P packed instructions"
311>;
312
313def FeatureMovrel : SubtargetFeature<"movrel",
314  "HasMovrel",
315  "true",
316  "Has v_movrel*_b32 instructions"
317>;
318
319def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
320  "HasVGPRIndexMode",
321  "true",
322  "Has VGPR mode register indexing"
323>;
324
325def FeatureScalarStores : SubtargetFeature<"scalar-stores",
326  "HasScalarStores",
327  "true",
328  "Has store scalar memory instructions"
329>;
330
331def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
332  "HasScalarAtomics",
333  "true",
334  "Has atomic scalar memory instructions"
335>;
336
337def FeatureSDWA : SubtargetFeature<"sdwa",
338  "HasSDWA",
339  "true",
340  "Support SDWA (Sub-DWORD Addressing) extension"
341>;
342
343def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
344  "HasSDWAOmod",
345  "true",
346  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
347>;
348
349def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
350  "HasSDWAScalar",
351  "true",
352  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
353>;
354
355def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
356  "HasSDWASdst",
357  "true",
358  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
359>;
360
361def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
362  "HasSDWAMac",
363  "true",
364  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
365>;
366
367def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
368  "HasSDWAOutModsVOPC",
369  "true",
370  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
371>;
372
373def FeatureDPP : SubtargetFeature<"dpp",
374  "HasDPP",
375  "true",
376  "Support DPP (Data Parallel Primitives) extension"
377>;
378
379// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
380def FeatureDPP8 : SubtargetFeature<"dpp8",
381  "HasDPP8",
382  "true",
383  "Support DPP8 (Data Parallel Primitives) extension"
384>;
385
386def FeatureR128A16 : SubtargetFeature<"r128-a16",
387  "HasR128A16",
388  "true",
389  "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
390>;
391
392def FeatureGFX10A16 : SubtargetFeature<"a16",
393  "HasGFX10A16",
394  "true",
395  "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
396>;
397
398def FeatureG16 : SubtargetFeature<"g16",
399  "HasG16",
400  "true",
401  "Support G16 for 16-bit gradient image operands"
402>;
403
404def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
405  "HasNSAEncoding",
406  "true",
407  "Support NSA encoding for image instructions"
408>;
409
410def FeatureGFX10_BEncoding : SubtargetFeature<"gfx10_b-encoding",
411  "GFX10_BEncoding",
412  "true",
413  "Encoding format GFX10_B"
414>;
415
416def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
417  "HasIntClamp",
418  "true",
419  "Support clamp for integer destination"
420>;
421
422def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
423  "HasUnpackedD16VMem",
424  "true",
425  "Has unpacked d16 vmem instructions"
426>;
427
428def FeatureDLInsts : SubtargetFeature<"dl-insts",
429  "HasDLInsts",
430  "true",
431  "Has v_fmac_f32 and v_xnor_b32 instructions"
432>;
433
434def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
435  "HasDot1Insts",
436  "true",
437  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
438>;
439
440def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
441  "HasDot2Insts",
442  "true",
443  "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
444>;
445
446def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
447  "HasDot3Insts",
448  "true",
449  "Has v_dot8c_i32_i4 instruction"
450>;
451
452def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
453  "HasDot4Insts",
454  "true",
455  "Has v_dot2c_i32_i16 instruction"
456>;
457
458def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
459  "HasDot5Insts",
460  "true",
461  "Has v_dot2c_f32_f16 instruction"
462>;
463
464def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
465  "HasDot6Insts",
466  "true",
467  "Has v_dot4c_i32_i8 instruction"
468>;
469
470def FeatureMAIInsts : SubtargetFeature<"mai-insts",
471  "HasMAIInsts",
472  "true",
473  "Has mAI instructions"
474>;
475
476def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
477  "HasPkFmacF16Inst",
478  "true",
479  "Has v_pk_fmac_f16 instruction"
480>;
481
482def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
483  "HasAtomicFaddInsts",
484  "true",
485  "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
486  "global_atomic_pk_add_f16 instructions",
487  [FeatureFlatGlobalInsts]
488>;
489
490def FeatureDoesNotSupportSRAMECC : SubtargetFeature<"no-sram-ecc-support",
491  "DoesNotSupportSRAMECC",
492  "true",
493  "Hardware does not support SRAM ECC"
494>;
495
496def FeatureSRAMECC : SubtargetFeature<"sram-ecc",
497  "EnableSRAMECC",
498  "true",
499  "Enable SRAM ECC"
500>;
501
502def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
503  "HasNoSdstCMPX",
504  "true",
505  "V_CMPX does not write VCC/SGPR in addition to EXEC"
506>;
507
508def FeatureVscnt : SubtargetFeature<"vscnt",
509  "HasVscnt",
510  "true",
511  "Has separate store vscnt counter"
512>;
513
514def FeatureGetWaveIdInst : SubtargetFeature<"get-wave-id-inst",
515  "HasGetWaveIdInst",
516  "true",
517  "Has s_get_waveid_in_workgroup instruction"
518>;
519
520def FeatureSMemTimeInst : SubtargetFeature<"s-memtime-inst",
521  "HasSMemTimeInst",
522  "true",
523  "Has s_memtime instruction"
524>;
525
526def FeatureMadMacF32Insts : SubtargetFeature<"mad-mac-f32-insts",
527  "HasMadMacF32Insts",
528  "true",
529  "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions"
530>;
531
532def FeatureDsSrc2Insts : SubtargetFeature<"ds-src2-insts",
533  "HasDsSrc2Insts",
534  "true",
535  "Has ds_*_src2 instructions"
536>;
537
538def FeatureRegisterBanking : SubtargetFeature<"register-banking",
539  "HasRegisterBanking",
540  "true",
541  "Has register banking"
542>;
543
544def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
545  "HasVOP3Literal",
546  "true",
547  "Can use one literal in VOP3"
548>;
549
550def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
551  "HasNoDataDepHazard",
552  "true",
553  "Does not need SW waitstates"
554>;
555
556//===------------------------------------------------------------===//
557// Subtarget Features (options and debugging)
558//===------------------------------------------------------------===//
559
560class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
561  "max-private-element-size-"#size,
562  "MaxPrivateElementSize",
563  !cast<string>(size),
564  "Maximum private access size may be "#size
565>;
566
567def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
568def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
569def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
570
571def FeatureDumpCode : SubtargetFeature <"DumpCode",
572  "DumpCode",
573  "true",
574  "Dump MachineInstrs in the CodeEmitter"
575>;
576
577def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
578  "DumpCode",
579  "true",
580  "Dump MachineInstrs in the CodeEmitter"
581>;
582
583// XXX - This should probably be removed once enabled by default
584def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
585  "EnableLoadStoreOpt",
586  "true",
587  "Enable SI load/store optimizer pass"
588>;
589
590// Performance debugging feature. Allow using DS instruction immediate
591// offsets even if the base pointer can't be proven to be base. On SI,
592// base pointer values that won't give the same result as a 16-bit add
593// are not safe to fold, but this will override the conservative test
594// for the base pointer.
595def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
596  "unsafe-ds-offset-folding",
597  "EnableUnsafeDSOffsetFolding",
598  "true",
599  "Force using DS instruction immediate offsets on SI"
600>;
601
602def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
603  "EnableSIScheduler",
604  "true",
605  "Enable SI Machine Scheduler"
606>;
607
608def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
609  "EnableDS128",
610  "true",
611  "Use ds_{read|write}_b128"
612>;
613
614// Sparse texture support requires that all result registers are zeroed when
615// PRTStrictNull is set to true. This feature is turned on for all architectures
616// but is enabled as a feature in case there are situations where PRTStrictNull
617// is disabled by the driver.
618def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
619  "EnablePRTStrictNull",
620  "true",
621  "Enable zeroing of result registers for sparse texture fetches"
622>;
623
624// Unless +-flat-for-global is specified, turn on FlatForGlobal for
625// all OS-es on VI and newer hardware to avoid assertion failures due
626// to missing ADDR64 variants of MUBUF instructions.
627// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
628// instructions.
629
630def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
631  "FlatForGlobal",
632  "true",
633  "Force to generate flat instruction for global"
634>;
635
636def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
637  "auto-waitcnt-before-barrier",
638  "AutoWaitcntBeforeBarrier",
639  "true",
640  "Hardware automatically inserts waitcnt before barrier"
641>;
642
643def FeatureCodeObjectV3 : SubtargetFeature <
644  "code-object-v3",
645  "CodeObjectV3",
646  "true",
647  "Generate code object version 3"
648>;
649
650def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
651  "HasTrigReducedRange",
652  "true",
653  "Requires use of fract on arguments to trig instructions"
654>;
655
656// Dummy feature used to disable assembler instructions.
657def FeatureDisable : SubtargetFeature<"",
658  "FeatureDisable","true",
659  "Dummy feature to disable assembler instructions"
660>;
661
662class GCNSubtargetFeatureGeneration <string Value,
663                                     string FeatureName,
664                                     list<SubtargetFeature> Implies> :
665        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
666
667def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
668    "southern-islands",
669  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
670  FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,
671  FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
672  FeatureTrigReducedRange, FeatureDoesNotSupportSRAMECC,
673  FeatureDoesNotSupportXNACK]
674>;
675
676def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
677    "sea-islands",
678  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
679  FeatureWavefrontSize64, FeatureFlatAddressSpace,
680  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
681  FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
682  FeatureDsSrc2Insts, FeatureDoesNotSupportSRAMECC]
683>;
684
685def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
686  "volcanic-islands",
687  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
688   FeatureWavefrontSize64, FeatureFlatAddressSpace,
689   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
690   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
691   FeatureScalarStores, FeatureInv2PiInlineImm,
692   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
693   FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
694   FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
695   FeatureDsSrc2Insts, FeatureDoesNotSupportSRAMECC, FeatureFastDenormalF32
696  ]
697>;
698
699def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
700  "gfx9",
701  [FeatureFP64, FeatureLocalMemorySize65536,
702   FeatureWavefrontSize64, FeatureFlatAddressSpace,
703   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
704   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
705   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
706   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
707   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
708   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
709   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
710   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
711   FeatureSMemTimeInst, FeatureMadMacF32Insts, FeatureDsSrc2Insts,
712   FeatureFastDenormalF32, FeatureUnalignedDSAccess
713  ]
714>;
715
716def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
717  "gfx10",
718  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
719   FeatureFlatAddressSpace,
720   FeatureCIInsts, Feature16BitInsts,
721   FeatureSMemRealTime, FeatureInv2PiInlineImm,
722   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
723   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
724   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
725   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
726   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
727   FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
728   FeatureVOP3Literal, FeatureDPP8,
729   FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureDoesNotSupportSRAMECC,
730   FeatureGFX10A16, FeatureFastDenormalF32, FeatureG16,
731   FeatureUnalignedDSAccess
732  ]
733>;
734
735class FeatureSet<list<SubtargetFeature> Features_> {
736  list<SubtargetFeature> Features = Features_;
737}
738
739def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
740   FeatureFastFMAF32,
741   HalfRate64Ops,
742   FeatureLDSBankCount32,
743   FeatureDoesNotSupportXNACK,
744   FeatureCodeObjectV3]>;
745
746def FeatureISAVersion6_0_1 : FeatureSet<
747  [FeatureSouthernIslands,
748   FeatureLDSBankCount32,
749   FeatureDoesNotSupportXNACK,
750   FeatureCodeObjectV3]>;
751
752def FeatureISAVersion7_0_0 : FeatureSet<
753  [FeatureSeaIslands,
754   FeatureLDSBankCount32,
755   FeatureDoesNotSupportXNACK,
756   FeatureCodeObjectV3]>;
757
758def FeatureISAVersion7_0_1 : FeatureSet<
759  [FeatureSeaIslands,
760   HalfRate64Ops,
761   FeatureLDSBankCount32,
762   FeatureFastFMAF32,
763   FeatureDoesNotSupportXNACK,
764   FeatureCodeObjectV3]>;
765
766def FeatureISAVersion7_0_2 : FeatureSet<
767  [FeatureSeaIslands,
768   FeatureLDSBankCount16,
769   FeatureFastFMAF32,
770   FeatureDoesNotSupportXNACK,
771   FeatureCodeObjectV3]>;
772
773def FeatureISAVersion7_0_3 : FeatureSet<
774  [FeatureSeaIslands,
775   FeatureLDSBankCount16,
776   FeatureDoesNotSupportXNACK,
777   FeatureCodeObjectV3]>;
778
779def FeatureISAVersion7_0_4 : FeatureSet<
780  [FeatureSeaIslands,
781   FeatureLDSBankCount32,
782   FeatureDoesNotSupportXNACK,
783   FeatureCodeObjectV3]>;
784
785def FeatureISAVersion8_0_1 : FeatureSet<
786  [FeatureVolcanicIslands,
787   FeatureFastFMAF32,
788   HalfRate64Ops,
789   FeatureLDSBankCount32,
790   FeatureXNACK,
791   FeatureUnpackedD16VMem,
792   FeatureCodeObjectV3]>;
793
794def FeatureISAVersion8_0_2 : FeatureSet<
795  [FeatureVolcanicIslands,
796   FeatureLDSBankCount32,
797   FeatureSGPRInitBug,
798   FeatureUnpackedD16VMem,
799   FeatureDoesNotSupportXNACK,
800   FeatureCodeObjectV3]>;
801
802def FeatureISAVersion8_0_3 : FeatureSet<
803  [FeatureVolcanicIslands,
804   FeatureLDSBankCount32,
805   FeatureUnpackedD16VMem,
806   FeatureDoesNotSupportXNACK,
807   FeatureCodeObjectV3]>;
808
809def FeatureISAVersion8_1_0 : FeatureSet<
810  [FeatureVolcanicIslands,
811   FeatureLDSBankCount16,
812   FeatureXNACK,
813   FeatureCodeObjectV3]>;
814
815def FeatureISAVersion9_0_0 : FeatureSet<
816  [FeatureGFX9,
817   FeatureMadMixInsts,
818   FeatureLDSBankCount32,
819   FeatureCodeObjectV3,
820   FeatureDoesNotSupportXNACK,
821   FeatureDoesNotSupportSRAMECC]>;
822
823def FeatureISAVersion9_0_2 : FeatureSet<
824  [FeatureGFX9,
825   FeatureMadMixInsts,
826   FeatureLDSBankCount32,
827   FeatureXNACK,
828   FeatureDoesNotSupportSRAMECC,
829   FeatureCodeObjectV3]>;
830
831def FeatureISAVersion9_0_4 : FeatureSet<
832  [FeatureGFX9,
833   FeatureLDSBankCount32,
834   FeatureFmaMixInsts,
835   FeatureDoesNotSupportXNACK,
836   FeatureDoesNotSupportSRAMECC,
837   FeatureCodeObjectV3]>;
838
839def FeatureISAVersion9_0_6 : FeatureSet<
840  [FeatureGFX9,
841   HalfRate64Ops,
842   FeatureFmaMixInsts,
843   FeatureLDSBankCount32,
844   FeatureDLInsts,
845   FeatureDot1Insts,
846   FeatureDot2Insts,
847   FeatureDoesNotSupportXNACK,
848   FeatureCodeObjectV3]>;
849
850def FeatureISAVersion9_0_8 : FeatureSet<
851  [FeatureGFX9,
852   HalfRate64Ops,
853   FeatureFmaMixInsts,
854   FeatureLDSBankCount32,
855   FeatureDLInsts,
856   FeatureDot1Insts,
857   FeatureDot2Insts,
858   FeatureDot3Insts,
859   FeatureDot4Insts,
860   FeatureDot5Insts,
861   FeatureDot6Insts,
862   FeatureMAIInsts,
863   FeaturePkFmacF16Inst,
864   FeatureAtomicFaddInsts,
865   FeatureSRAMECC,
866   FeatureMFMAInlineLiteralBug,
867   FeatureCodeObjectV3]>;
868
869def FeatureISAVersion9_0_9 : FeatureSet<
870  [FeatureGFX9,
871   FeatureMadMixInsts,
872   FeatureLDSBankCount32,
873   FeatureXNACK,
874   FeatureCodeObjectV3]>;
875
876// TODO: Organize more features into groups.
877def FeatureGroup {
878  // Bugs present on gfx10.1.
879  list<SubtargetFeature> GFX10_1_Bugs = [
880    FeatureVcmpxPermlaneHazard,
881    FeatureVMEMtoScalarWriteHazard,
882    FeatureSMEMtoVectorWriteHazard,
883    FeatureInstFwdPrefetchBug,
884    FeatureVcmpxExecWARHazard,
885    FeatureLdsBranchVmemWARHazard,
886    FeatureNSAtoVMEMBug,
887    FeatureOffset3fBug,
888    FeatureFlatSegmentOffsetBug
889   ];
890}
891
892def FeatureISAVersion10_1_0 : FeatureSet<
893  !listconcat(FeatureGroup.GFX10_1_Bugs,
894    [FeatureGFX10,
895     FeatureLDSBankCount32,
896     FeatureDLInsts,
897     FeatureNSAEncoding,
898     FeatureWavefrontSize32,
899     FeatureScalarStores,
900     FeatureScalarAtomics,
901     FeatureScalarFlatScratchInsts,
902     FeatureGetWaveIdInst,
903     FeatureSMemTimeInst,
904     FeatureMadMacF32Insts,
905     FeatureDsSrc2Insts,
906     FeatureLdsMisalignedBug,
907     FeatureDoesNotSupportXNACK,
908     FeatureCodeObjectV3])>;
909
910def FeatureISAVersion10_1_1 : FeatureSet<
911  !listconcat(FeatureGroup.GFX10_1_Bugs,
912    [FeatureGFX10,
913     FeatureLDSBankCount32,
914     FeatureDLInsts,
915     FeatureDot1Insts,
916     FeatureDot2Insts,
917     FeatureDot5Insts,
918     FeatureDot6Insts,
919     FeatureNSAEncoding,
920     FeatureWavefrontSize32,
921     FeatureScalarStores,
922     FeatureScalarAtomics,
923     FeatureScalarFlatScratchInsts,
924     FeatureGetWaveIdInst,
925     FeatureSMemTimeInst,
926     FeatureMadMacF32Insts,
927     FeatureDsSrc2Insts,
928     FeatureLdsMisalignedBug,
929     FeatureDoesNotSupportXNACK,
930     FeatureCodeObjectV3])>;
931
932def FeatureISAVersion10_1_2 : FeatureSet<
933  !listconcat(FeatureGroup.GFX10_1_Bugs,
934    [FeatureGFX10,
935     FeatureLDSBankCount32,
936     FeatureDLInsts,
937     FeatureDot1Insts,
938     FeatureDot2Insts,
939     FeatureDot5Insts,
940     FeatureDot6Insts,
941     FeatureNSAEncoding,
942     FeatureWavefrontSize32,
943     FeatureScalarStores,
944     FeatureScalarAtomics,
945     FeatureScalarFlatScratchInsts,
946     FeatureGetWaveIdInst,
947     FeatureSMemTimeInst,
948     FeatureMadMacF32Insts,
949     FeatureDsSrc2Insts,
950     FeatureLdsMisalignedBug,
951     FeatureDoesNotSupportXNACK,
952     FeatureCodeObjectV3])>;
953
954def FeatureISAVersion10_3_0 : FeatureSet<
955  [FeatureGFX10,
956   FeatureGFX10_BEncoding,
957   FeatureGFX10_3Insts,
958   FeatureLDSBankCount32,
959   FeatureDLInsts,
960   FeatureDot1Insts,
961   FeatureDot2Insts,
962   FeatureDot5Insts,
963   FeatureDot6Insts,
964   FeatureNSAEncoding,
965   FeatureWavefrontSize32,
966   FeatureDoesNotSupportXNACK,
967   FeatureCodeObjectV3]>;
968
969//===----------------------------------------------------------------------===//
970
971def AMDGPUInstrInfo : InstrInfo {
972  let guessInstructionProperties = 1;
973  let noNamedPositionallyEncodedOperands = 1;
974}
975
976def AMDGPUAsmParser : AsmParser {
977  // Some of the R600 registers have the same name, so this crashes.
978  // For example T0_XYZW and T0_XY both have the asm name T0.
979  let ShouldEmitMatchRegisterName = 0;
980}
981
982def AMDGPUAsmWriter : AsmWriter {
983  int PassSubtarget = 1;
984}
985
986def AMDGPUAsmVariants {
987  string Default = "Default";
988  int Default_ID = 0;
989  string VOP3 = "VOP3";
990  int VOP3_ID = 1;
991  string SDWA = "SDWA";
992  int SDWA_ID = 2;
993  string SDWA9 = "SDWA9";
994  int SDWA9_ID = 3;
995  string DPP = "DPP";
996  int DPP_ID = 4;
997  string Disable = "Disable";
998  int Disable_ID = 5;
999}
1000
1001def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
1002  let Variant = AMDGPUAsmVariants.Default_ID;
1003  let Name = AMDGPUAsmVariants.Default;
1004}
1005
1006def VOP3AsmParserVariant : AsmParserVariant {
1007  let Variant = AMDGPUAsmVariants.VOP3_ID;
1008  let Name = AMDGPUAsmVariants.VOP3;
1009}
1010
1011def SDWAAsmParserVariant : AsmParserVariant {
1012  let Variant = AMDGPUAsmVariants.SDWA_ID;
1013  let Name = AMDGPUAsmVariants.SDWA;
1014}
1015
1016def SDWA9AsmParserVariant : AsmParserVariant {
1017  let Variant = AMDGPUAsmVariants.SDWA9_ID;
1018  let Name = AMDGPUAsmVariants.SDWA9;
1019}
1020
1021
1022def DPPAsmParserVariant : AsmParserVariant {
1023  let Variant = AMDGPUAsmVariants.DPP_ID;
1024  let Name = AMDGPUAsmVariants.DPP;
1025}
1026
1027def AMDGPU : Target {
1028  // Pull in Instruction Info:
1029  let InstructionSet = AMDGPUInstrInfo;
1030  let AssemblyParsers = [AMDGPUAsmParser];
1031  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
1032                                VOP3AsmParserVariant,
1033                                SDWAAsmParserVariant,
1034                                SDWA9AsmParserVariant,
1035                                DPPAsmParserVariant];
1036  let AssemblyWriters = [AMDGPUAsmWriter];
1037  let AllowRegisterRenaming = 1;
1038}
1039
1040// Dummy Instruction itineraries for pseudo instructions
1041def ALU_NULL : FuncUnit;
1042def NullALU : InstrItinClass;
1043
1044//===----------------------------------------------------------------------===//
1045// Predicate helper class
1046//===----------------------------------------------------------------------===//
1047
1048def isGFX6 :
1049  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1050  AssemblerPredicate<(all_of FeatureSouthernIslands)>;
1051
1052def isGFX6GFX7 :
1053  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1054            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1055  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
1056
1057def isGFX6GFX7GFX10 :
1058  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1059            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1060            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1061  AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
1062
1063def isGFX7Only :
1064  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1065  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
1066
1067def isGFX7GFX10 :
1068  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1069            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1070  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
1071
1072def isGFX7GFX8 :
1073  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1074            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1075  AssemblerPredicate<(all_of FeatureSouthernIslands, FeatureCIInsts)>;
1076
1077def isGFX7GFX8GFX9 :
1078  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1079            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1080            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1081  AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
1082
1083def isGFX6GFX7GFX8GFX9 :
1084  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1085            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1086            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1087            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1088  AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
1089
1090def isGFX7Plus :
1091  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1092  AssemblerPredicate<(all_of FeatureCIInsts)>;
1093
1094def isGFX8Plus :
1095  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1096  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1097
1098def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1099                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1100  AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1101
1102def isGFX9Plus :
1103  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1104  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1105
1106def isGFX9Only : Predicate <
1107  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1108  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1109
1110def isGFX8GFX9 :
1111  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1112            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1113  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1114
1115def isGFX10Plus :
1116  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1117  AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1118
1119def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1120  AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1121
1122def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1123  AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1124def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1125  AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1126def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1127  AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1128def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1129  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1130
1131def HasGFX10_BEncoding : Predicate<"Subtarget->hasGFX10_BEncoding()">,
1132  AssemblerPredicate<(all_of FeatureGFX10_BEncoding)>;
1133
1134def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1135  AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1136def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1137  AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1138
1139def D16PreservesUnusedBits :
1140  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1141  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1142
1143def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1144def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1145
1146def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1147  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1148
1149def HasLDSFPAtomics : Predicate<"Subtarget->hasLDSFPAtomics()">,
1150  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1151
1152def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1153  AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1154
1155def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1156
1157def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1158  AssemblerPredicate<(all_of Feature16BitInsts)>;
1159def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1160  AssemblerPredicate<(all_of FeatureVOP3P)>;
1161
1162def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
1163def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
1164
1165def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1166  AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1167
1168def HasSDWA9 :
1169  Predicate<"Subtarget->hasSDWA()">,
1170  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1171
1172def HasSDWA10 :
1173  Predicate<"Subtarget->hasSDWA()">,
1174  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1175
1176def HasDPP : Predicate<"Subtarget->hasDPP()">,
1177  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1178
1179def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1180  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1181
1182def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1183  AssemblerPredicate<(all_of FeatureR128A16)>;
1184
1185def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1186  AssemblerPredicate<(all_of FeatureGFX10A16)>;
1187
1188def HasG16 : Predicate<"Subtarget->hasG16()">,
1189  AssemblerPredicate<(all_of FeatureG16)>;
1190
1191def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1192  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1193
1194def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1195  AssemblerPredicate<(all_of FeatureIntClamp)>;
1196
1197def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1198  AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1199
1200def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1201  AssemblerPredicate<(all_of FeatureScalarStores)>;
1202
1203def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1204  AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1205
1206def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1207  AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1208
1209def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1210  AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1211
1212def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1213def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1214def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1215                      AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1216def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1217                AssemblerPredicate<(all_of FeatureMovrel)>;
1218
1219def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1220  AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1221
1222def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1223  AssemblerPredicate<(all_of FeatureDLInsts)>;
1224
1225def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1226  AssemblerPredicate<(all_of FeatureDot1Insts)>;
1227
1228def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1229  AssemblerPredicate<(all_of FeatureDot2Insts)>;
1230
1231def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1232  AssemblerPredicate<(all_of FeatureDot3Insts)>;
1233
1234def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1235  AssemblerPredicate<(all_of FeatureDot4Insts)>;
1236
1237def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1238  AssemblerPredicate<(all_of FeatureDot5Insts)>;
1239
1240def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1241  AssemblerPredicate<(all_of FeatureDot6Insts)>;
1242
1243def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">,
1244  AssemblerPredicate<(all_of FeatureGetWaveIdInst)>;
1245
1246def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1247  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1248
1249def HasSMemTimeInst : Predicate<"Subtarget->hasSMemTimeInst()">,
1250  AssemblerPredicate<(all_of FeatureSMemTimeInst)>;
1251
1252def HasNoSMemTimeInst : Predicate<"!Subtarget->hasSMemTimeInst()">;
1253
1254def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1255  AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1256
1257def HasMadMacF32Insts : Predicate<"Subtarget->hasMadMacF32Insts()">,
1258  AssemblerPredicate<(all_of FeatureMadMacF32Insts)>;
1259
1260def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1261  AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>;
1262
1263def HasNoMadMacF32Insts : Predicate<"!Subtarget->hasMadMacF32Insts()">,
1264  AssemblerPredicate<(all_of (not FeatureMadMacF32Insts))>;
1265
1266def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
1267  AssemblerPredicate<(all_of FeatureDsSrc2Insts)>;
1268
1269def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">,
1270  AssemblerPredicate<(all_of FeatureOffset3fBug)>;
1271
1272def EnableLateCFGStructurize : Predicate<
1273  "EnableLateStructurizeCFG">;
1274
1275// Include AMDGPU TD files
1276include "SISchedule.td"
1277include "GCNProcessors.td"
1278include "AMDGPUInstrInfo.td"
1279include "SIRegisterInfo.td"
1280include "AMDGPURegisterBanks.td"
1281include "AMDGPUInstructions.td"
1282include "SIInstrInfo.td"
1283include "AMDGPUCallingConv.td"
1284include "AMDGPUSearchableTables.td"
1285