1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===------------------------------------------------------------===//
9
10include "llvm/Target/Target.td"
11
12//===------------------------------------------------------------===//
13// Subtarget Features (device properties)
14//===------------------------------------------------------------===//
15
16def FeatureFP64 : SubtargetFeature<"fp64",
17  "FP64",
18  "true",
19  "Enable double precision operations"
20>;
21
22def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
23  "FastFMAF32",
24  "true",
25  "Assuming f32 fma is at least as fast as mul + add"
26>;
27
28def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
29  "HalfRate64Ops",
30  "true",
31  "Most fp64 instructions are half rate instead of quarter"
32>;
33
34def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
35  "R600ALUInst",
36  "false",
37  "Older version of ALU instructions encoding"
38>;
39
40def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
41  "HasVertexCache",
42  "true",
43  "Specify use of dedicated vertex cache"
44>;
45
46def FeatureCaymanISA : SubtargetFeature<"caymanISA",
47  "CaymanISA",
48  "true",
49  "Use Cayman ISA"
50>;
51
52def FeatureCFALUBug : SubtargetFeature<"cfalubug",
53  "CFALUBug",
54  "true",
55  "GPU has CF_ALU bug"
56>;
57
58def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
59  "FlatAddressSpace",
60  "true",
61  "Support flat address space"
62>;
63
64def FeatureXNACK : SubtargetFeature<"xnack",
65  "EnableXNACK",
66  "true",
67  "Enable XNACK support"
68>;
69
70def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
71  "SGPRInitBug",
72  "true",
73  "VI SGPR initilization bug requiring a fixed SGPR allocation size"
74>;
75
76class SubtargetFeatureFetchLimit <string Value> :
77                          SubtargetFeature <"fetch"#Value,
78  "TexVTXClauseSize",
79  Value,
80  "Limit the maximum number of fetches in a clause to "#Value
81>;
82
83def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
84def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
85
86class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
87  "wavefrontsize"#Value,
88  "WavefrontSize",
89  !cast<string>(Value),
90  "The number of threads per wavefront"
91>;
92
93def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
94def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
95def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
96
97class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
98  "ldsbankcount"#Value,
99  "LDSBankCount",
100  !cast<string>(Value),
101  "The number of LDS banks per compute unit."
102>;
103
104def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
105def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
106
107class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping>
108                                 : SubtargetFeature <
109  "isaver"#Major#"."#Minor#"."#Stepping,
110  "IsaVersion",
111  "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
112  "Instruction set version number"
113>;
114
115def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0>;
116def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1>;
117def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0>;
118def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1>;
119def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3>;
120
121class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
122  "localmemorysize"#Value,
123  "LocalMemorySize",
124  !cast<string>(Value),
125  "The size of local memory in bytes"
126>;
127
128def FeatureGCN : SubtargetFeature<"gcn",
129  "IsGCN",
130  "true",
131  "GCN or newer GPU"
132>;
133
134def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",
135  "GCN1Encoding",
136  "true",
137  "Encoding format for SI and CI"
138>;
139
140def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
141  "GCN3Encoding",
142  "true",
143  "Encoding format for VI"
144>;
145
146def FeatureCIInsts : SubtargetFeature<"ci-insts",
147  "CIInsts",
148  "true",
149  "Additional intstructions for CI+"
150>;
151
152def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
153  "HasSMemRealTime",
154  "true",
155  "Has s_memrealtime instruction"
156>;
157
158def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
159  "Has16BitInsts",
160  "true",
161  "Has i16/f16 instructions"
162>;
163
164//===------------------------------------------------------------===//
165// Subtarget Features (options and debugging)
166//===------------------------------------------------------------===//
167
168// Some instructions do not support denormals despite this flag. Using
169// fp32 denormals also causes instructions to run at the double
170// precision rate for the device.
171def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
172  "FP32Denormals",
173  "true",
174  "Enable single precision denormal handling"
175>;
176
177def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
178  "FP64Denormals",
179  "true",
180  "Enable double precision denormal handling",
181  [FeatureFP64]
182>;
183
184def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
185  "FPExceptions",
186  "true",
187  "Enable floating point exceptions"
188>;
189
190class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
191  "max-private-element-size-"#size,
192  "MaxPrivateElementSize",
193  !cast<string>(size),
194  "Maximum private access size may be "#size
195>;
196
197def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
198def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
199def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
200
201def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
202  "EnableVGPRSpilling",
203  "true",
204  "Enable spilling of VGPRs to scratch memory"
205>;
206
207def FeatureDumpCode : SubtargetFeature <"DumpCode",
208  "DumpCode",
209  "true",
210  "Dump MachineInstrs in the CodeEmitter"
211>;
212
213def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
214  "DumpCode",
215  "true",
216  "Dump MachineInstrs in the CodeEmitter"
217>;
218
219def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
220  "EnablePromoteAlloca",
221  "true",
222  "Enable promote alloca pass"
223>;
224
225// XXX - This should probably be removed once enabled by default
226def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
227  "EnableLoadStoreOpt",
228  "true",
229  "Enable SI load/store optimizer pass"
230>;
231
232// Performance debugging feature. Allow using DS instruction immediate
233// offsets even if the base pointer can't be proven to be base. On SI,
234// base pointer values that won't give the same result as a 16-bit add
235// are not safe to fold, but this will override the conservative test
236// for the base pointer.
237def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
238  "unsafe-ds-offset-folding",
239  "EnableUnsafeDSOffsetFolding",
240  "true",
241  "Force using DS instruction immediate offsets on SI"
242>;
243
244def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
245  "EnableSIScheduler",
246  "true",
247  "Enable SI Machine Scheduler"
248>;
249
250def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
251  "FlatForGlobal",
252  "true",
253  "Force to generate flat instruction for global"
254>;
255
256// Dummy feature used to disable assembler instructions.
257def FeatureDisable : SubtargetFeature<"",
258  "FeatureDisable","true",
259  "Dummy feature to disable assembler instructions"
260>;
261
262class SubtargetFeatureGeneration <string Value,
263                                  list<SubtargetFeature> Implies> :
264        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
265                          Value#" GPU generation", Implies>;
266
267def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
268def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
269def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
270
271def FeatureR600 : SubtargetFeatureGeneration<"R600",
272  [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]
273>;
274
275def FeatureR700 : SubtargetFeatureGeneration<"R700",
276  [FeatureFetchLimit16, FeatureLocalMemorySize0]
277>;
278
279def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
280  [FeatureFetchLimit16, FeatureLocalMemorySize32768]
281>;
282
283def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
284  [FeatureFetchLimit16, FeatureWavefrontSize64,
285   FeatureLocalMemorySize32768]
286>;
287
288def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
289  [FeatureFP64, FeatureLocalMemorySize32768,
290  FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
291  FeatureLDSBankCount32]
292>;
293
294def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
295  [FeatureFP64, FeatureLocalMemorySize65536,
296  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
297  FeatureGCN1Encoding, FeatureCIInsts]
298>;
299
300def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
301  [FeatureFP64, FeatureLocalMemorySize65536,
302   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
303   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
304   FeatureSMemRealTime
305  ]
306>;
307
308//===----------------------------------------------------------------------===//
309// Debugger related subtarget features.
310//===----------------------------------------------------------------------===//
311
312def FeatureDebuggerInsertNops : SubtargetFeature<
313  "amdgpu-debugger-insert-nops",
314  "DebuggerInsertNops",
315  "true",
316  "Insert one nop instruction for each high level source statement"
317>;
318
319def FeatureDebuggerReserveRegs : SubtargetFeature<
320  "amdgpu-debugger-reserve-regs",
321  "DebuggerReserveRegs",
322  "true",
323  "Reserve registers for debugger usage"
324>;
325
326def FeatureDebuggerEmitPrologue : SubtargetFeature<
327  "amdgpu-debugger-emit-prologue",
328  "DebuggerEmitPrologue",
329  "true",
330  "Emit debugger prologue"
331>;
332
333//===----------------------------------------------------------------------===//
334
335def AMDGPUInstrInfo : InstrInfo {
336  let guessInstructionProperties = 1;
337  let noNamedPositionallyEncodedOperands = 1;
338}
339
340def AMDGPUAsmParser : AsmParser {
341  // Some of the R600 registers have the same name, so this crashes.
342  // For example T0_XYZW and T0_XY both have the asm name T0.
343  let ShouldEmitMatchRegisterName = 0;
344}
345
346def AMDGPU : Target {
347  // Pull in Instruction Info:
348  let InstructionSet = AMDGPUInstrInfo;
349  let AssemblyParsers = [AMDGPUAsmParser];
350}
351
352// Dummy Instruction itineraries for pseudo instructions
353def ALU_NULL : FuncUnit;
354def NullALU : InstrItinClass;
355
356//===----------------------------------------------------------------------===//
357// Predicate helper class
358//===----------------------------------------------------------------------===//
359
360def TruePredicate : Predicate<"true">;
361
362def isSICI : Predicate<
363  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
364  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
365>, AssemblerPredicate<"FeatureGCN1Encoding">;
366
367def isVI : Predicate <
368  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
369  AssemblerPredicate<"FeatureGCN3Encoding">;
370
371def isCIVI : Predicate <
372  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS || "
373  "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS"
374>, AssemblerPredicate<"FeatureCIInsts">;
375
376def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">;
377
378class PredicateControl {
379  Predicate SubtargetPredicate;
380  Predicate SIAssemblerPredicate = isSICI;
381  Predicate VIAssemblerPredicate = isVI;
382  list<Predicate> AssemblerPredicates = [];
383  Predicate AssemblerPredicate = TruePredicate;
384  list<Predicate> OtherPredicates = [];
385  list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
386                                            AssemblerPredicates,
387                                            OtherPredicates);
388}
389
390// Include AMDGPU TD files
391include "R600Schedule.td"
392include "SISchedule.td"
393include "Processors.td"
394include "AMDGPUInstrInfo.td"
395include "AMDGPUIntrinsics.td"
396include "AMDGPURegisterInfo.td"
397include "AMDGPUInstructions.td"
398include "AMDGPUCallingConv.td"
399