1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===------------------------------------------------------------===//
9
10include "llvm/Target/Target.td"
11
12//===------------------------------------------------------------===//
13// Subtarget Features (device properties)
14//===------------------------------------------------------------===//
15
16def FeatureFP64 : SubtargetFeature<"fp64",
17  "FP64",
18  "true",
19  "Enable double precision operations"
20>;
21
22def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
23  "FastFMAF32",
24  "true",
25  "Assuming f32 fma is at least as fast as mul + add"
26>;
27
28def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
29  "HalfRate64Ops",
30  "true",
31  "Most fp64 instructions are half rate instead of quarter"
32>;
33
34def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
35  "R600ALUInst",
36  "false",
37  "Older version of ALU instructions encoding"
38>;
39
40def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
41  "HasVertexCache",
42  "true",
43  "Specify use of dedicated vertex cache"
44>;
45
46def FeatureCaymanISA : SubtargetFeature<"caymanISA",
47  "CaymanISA",
48  "true",
49  "Use Cayman ISA"
50>;
51
52def FeatureCFALUBug : SubtargetFeature<"cfalubug",
53  "CFALUBug",
54  "true",
55  "GPU has CF_ALU bug"
56>;
57
58def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
59  "FlatAddressSpace",
60  "true",
61  "Support flat address space"
62>;
63
64def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
65  "FlatInstOffsets",
66  "true",
67  "Flat instructions have immediate offset addressing mode"
68>;
69
70def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
71  "FlatGlobalInsts",
72  "true",
73  "Have global_* flat memory instructions"
74>;
75
76def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
77  "FlatScratchInsts",
78  "true",
79  "Have scratch_* flat memory instructions"
80>;
81
82def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
83  "AddNoCarryInsts",
84  "true",
85  "Have VALU add/sub instructions without carry out"
86>;
87
88def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
89  "UnalignedBufferAccess",
90  "true",
91  "Support unaligned global loads and stores"
92>;
93
94def FeatureTrapHandler: SubtargetFeature<"trap-handler",
95  "TrapHandler",
96  "true",
97  "Trap handler support"
98>;
99
100def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
101  "UnalignedScratchAccess",
102  "true",
103  "Support unaligned scratch loads and stores"
104>;
105
106def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
107  "HasApertureRegs",
108  "true",
109  "Has Memory Aperture Base and Size Registers"
110>;
111
112// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
113// XNACK. The current default kernel driver setting is:
114// - graphics ring: XNACK disabled
115// - compute ring: XNACK enabled
116//
117// If XNACK is enabled, the VMEM latency can be worse.
118// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
119def FeatureXNACK : SubtargetFeature<"xnack",
120  "EnableXNACK",
121  "true",
122  "Enable XNACK support"
123>;
124
125def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
126  "SGPRInitBug",
127  "true",
128  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
129>;
130
131class SubtargetFeatureFetchLimit <string Value> :
132                          SubtargetFeature <"fetch"#Value,
133  "TexVTXClauseSize",
134  Value,
135  "Limit the maximum number of fetches in a clause to "#Value
136>;
137
138def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
139def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
140
141class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
142  "wavefrontsize"#Value,
143  "WavefrontSize",
144  !cast<string>(Value),
145  "The number of threads per wavefront"
146>;
147
148def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
149def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
150def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
151
152class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
153  "ldsbankcount"#Value,
154  "LDSBankCount",
155  !cast<string>(Value),
156  "The number of LDS banks per compute unit."
157>;
158
159def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
160def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
161
162class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
163  "localmemorysize"#Value,
164  "LocalMemorySize",
165  !cast<string>(Value),
166  "The size of local memory in bytes"
167>;
168
169def FeatureGCN : SubtargetFeature<"gcn",
170  "IsGCN",
171  "true",
172  "GCN or newer GPU"
173>;
174
175def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
176  "GCN3Encoding",
177  "true",
178  "Encoding format for VI"
179>;
180
181def FeatureCIInsts : SubtargetFeature<"ci-insts",
182  "CIInsts",
183  "true",
184  "Additional instructions for CI+"
185>;
186
187def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
188  "GFX9Insts",
189  "true",
190  "Additional instructions for GFX9+"
191>;
192
193def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
194  "HasSMemRealTime",
195  "true",
196  "Has s_memrealtime instruction"
197>;
198
199def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
200  "HasInv2PiInlineImm",
201  "true",
202  "Has 1 / (2 * pi) as inline immediate"
203>;
204
205def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
206  "Has16BitInsts",
207  "true",
208  "Has i16/f16 instructions"
209>;
210
211def FeatureVOP3P : SubtargetFeature<"vop3p",
212  "HasVOP3PInsts",
213  "true",
214  "Has VOP3P packed instructions"
215>;
216
217def FeatureMovrel : SubtargetFeature<"movrel",
218  "HasMovrel",
219  "true",
220  "Has v_movrel*_b32 instructions"
221>;
222
223def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
224  "HasVGPRIndexMode",
225  "true",
226  "Has VGPR mode register indexing"
227>;
228
229def FeatureScalarStores : SubtargetFeature<"scalar-stores",
230  "HasScalarStores",
231  "true",
232  "Has store scalar memory instructions"
233>;
234
235def FeatureSDWA : SubtargetFeature<"sdwa",
236  "HasSDWA",
237  "true",
238  "Support SDWA (Sub-DWORD Addressing) extension"
239>;
240
241def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
242  "HasSDWAOmod",
243  "true",
244  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
245>;
246
247def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
248  "HasSDWAScalar",
249  "true",
250  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
251>;
252
253def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
254  "HasSDWASdst",
255  "true",
256  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
257>;
258
259def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
260  "HasSDWAMac",
261  "true",
262  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
263>;
264
265def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
266  "HasSDWAOutModsVOPC",
267  "true",
268  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
269>;
270
271def FeatureDPP : SubtargetFeature<"dpp",
272  "HasDPP",
273  "true",
274  "Support DPP (Data Parallel Primitives) extension"
275>;
276
277def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
278  "HasIntClamp",
279  "true",
280  "Support clamp for integer destination"
281>;
282
283//===------------------------------------------------------------===//
284// Subtarget Features (options and debugging)
285//===------------------------------------------------------------===//
286
287// Some instructions do not support denormals despite this flag. Using
288// fp32 denormals also causes instructions to run at the double
289// precision rate for the device.
290def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
291  "FP32Denormals",
292  "true",
293  "Enable single precision denormal handling"
294>;
295
296// Denormal handling for fp64 and fp16 is controlled by the same
297// config register when fp16 supported.
298// TODO: Do we need a separate f16 setting when not legal?
299def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
300  "FP64FP16Denormals",
301  "true",
302  "Enable double and half precision denormal handling",
303  [FeatureFP64]
304>;
305
306def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
307  "FP64FP16Denormals",
308  "true",
309  "Enable double and half precision denormal handling",
310  [FeatureFP64, FeatureFP64FP16Denormals]
311>;
312
313def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
314  "FP64FP16Denormals",
315  "true",
316  "Enable half precision denormal handling",
317  [FeatureFP64FP16Denormals]
318>;
319
320def FeatureDX10Clamp : SubtargetFeature<"dx10-clamp",
321  "DX10Clamp",
322  "true",
323  "clamp modifier clamps NaNs to 0.0"
324>;
325
326def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
327  "FPExceptions",
328  "true",
329  "Enable floating point exceptions"
330>;
331
332class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
333  "max-private-element-size-"#size,
334  "MaxPrivateElementSize",
335  !cast<string>(size),
336  "Maximum private access size may be "#size
337>;
338
339def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
340def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
341def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
342
343def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
344  "EnableVGPRSpilling",
345  "true",
346  "Enable spilling of VGPRs to scratch memory"
347>;
348
349def FeatureDumpCode : SubtargetFeature <"DumpCode",
350  "DumpCode",
351  "true",
352  "Dump MachineInstrs in the CodeEmitter"
353>;
354
355def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
356  "DumpCode",
357  "true",
358  "Dump MachineInstrs in the CodeEmitter"
359>;
360
361def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
362  "EnablePromoteAlloca",
363  "true",
364  "Enable promote alloca pass"
365>;
366
367// XXX - This should probably be removed once enabled by default
368def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
369  "EnableLoadStoreOpt",
370  "true",
371  "Enable SI load/store optimizer pass"
372>;
373
374// Performance debugging feature. Allow using DS instruction immediate
375// offsets even if the base pointer can't be proven to be base. On SI,
376// base pointer values that won't give the same result as a 16-bit add
377// are not safe to fold, but this will override the conservative test
378// for the base pointer.
379def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
380  "unsafe-ds-offset-folding",
381  "EnableUnsafeDSOffsetFolding",
382  "true",
383  "Force using DS instruction immediate offsets on SI"
384>;
385
386def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
387  "EnableSIScheduler",
388  "true",
389  "Enable SI Machine Scheduler"
390>;
391
392// Unless +-flat-for-global is specified, turn on FlatForGlobal for
393// all OS-es on VI and newer hardware to avoid assertion failures due
394// to missing ADDR64 variants of MUBUF instructions.
395// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
396// instructions.
397
398def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
399  "FlatForGlobal",
400  "true",
401  "Force to generate flat instruction for global"
402>;
403
404def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
405  "auto-waitcnt-before-barrier",
406  "AutoWaitcntBeforeBarrier",
407  "true",
408  "Hardware automatically inserts waitcnt before barrier"
409>;
410
411def FeatureCodeObjectV3 : SubtargetFeature <
412  "code-object-v3",
413  "CodeObjectV3",
414  "true",
415  "Generate code object version 3"
416>;
417
418// Dummy feature used to disable assembler instructions.
419def FeatureDisable : SubtargetFeature<"",
420  "FeatureDisable","true",
421  "Dummy feature to disable assembler instructions"
422>;
423
424class SubtargetFeatureGeneration <string Value,
425                                  list<SubtargetFeature> Implies> :
426        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
427                          Value#" GPU generation", Implies>;
428
429def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
430def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
431def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
432
433def FeatureR600 : SubtargetFeatureGeneration<"R600",
434  [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]
435>;
436
437def FeatureR700 : SubtargetFeatureGeneration<"R700",
438  [FeatureFetchLimit16, FeatureLocalMemorySize0]
439>;
440
441def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
442  [FeatureFetchLimit16, FeatureLocalMemorySize32768]
443>;
444
445def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
446  [FeatureFetchLimit16, FeatureWavefrontSize64,
447   FeatureLocalMemorySize32768]
448>;
449
450def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
451  [FeatureFP64, FeatureLocalMemorySize32768,
452  FeatureWavefrontSize64, FeatureGCN,
453  FeatureLDSBankCount32, FeatureMovrel]
454>;
455
456def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
457  [FeatureFP64, FeatureLocalMemorySize65536,
458  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
459  FeatureCIInsts, FeatureMovrel]
460>;
461
462def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
463  [FeatureFP64, FeatureLocalMemorySize65536,
464   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
465   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
466   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
467   FeatureScalarStores, FeatureInv2PiInlineImm,
468   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
469   FeatureIntClamp
470  ]
471>;
472
473def FeatureGFX9 : SubtargetFeatureGeneration<"GFX9",
474  [FeatureFP64, FeatureLocalMemorySize65536,
475   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
476   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
477   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
478   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
479   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
480   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
481   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
482   FeatureAddNoCarryInsts
483  ]
484>;
485
486class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
487                                  list<SubtargetFeature> Implies>
488                                 : SubtargetFeature <
489  "isaver"#Major#"."#Minor#"."#Stepping,
490  "IsaVersion",
491  "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
492  "Instruction set version number",
493  Implies
494>;
495
496def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
497  [FeatureSouthernIslands,
498   FeatureFastFMAF32,
499   HalfRate64Ops,
500   FeatureLDSBankCount32]>;
501
502def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
503  [FeatureSouthernIslands,
504   FeatureLDSBankCount32]>;
505
506def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
507  [FeatureSeaIslands,
508   FeatureLDSBankCount32]>;
509
510def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
511  [FeatureSeaIslands,
512   HalfRate64Ops,
513   FeatureLDSBankCount32,
514   FeatureFastFMAF32]>;
515
516def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
517  [FeatureSeaIslands,
518   FeatureLDSBankCount16]>;
519
520def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
521  [FeatureSeaIslands,
522   FeatureLDSBankCount16]>;
523
524def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0,
525  [FeatureVolcanicIslands,
526   FeatureLDSBankCount32,
527   FeatureSGPRInitBug]>;
528
529def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
530  [FeatureVolcanicIslands,
531   FeatureFastFMAF32,
532   HalfRate64Ops,
533   FeatureLDSBankCount32,
534   FeatureXNACK]>;
535
536def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
537  [FeatureVolcanicIslands,
538   FeatureLDSBankCount32,
539   FeatureSGPRInitBug]>;
540
541def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
542  [FeatureVolcanicIslands,
543   FeatureLDSBankCount32]>;
544
545def FeatureISAVersion8_0_4 : SubtargetFeatureISAVersion <8,0,4,
546  [FeatureVolcanicIslands,
547   FeatureLDSBankCount32]>;
548
549def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
550  [FeatureVolcanicIslands,
551   FeatureLDSBankCount16,
552   FeatureXNACK]>;
553
554def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
555  [FeatureGFX9,
556   FeatureLDSBankCount32]>;
557
558def FeatureISAVersion9_0_1 : SubtargetFeatureISAVersion <9,0,1,
559  [FeatureGFX9,
560   FeatureLDSBankCount32,
561   FeatureXNACK]>;
562
563def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
564  [FeatureGFX9,
565   FeatureLDSBankCount32]>;
566
567def FeatureISAVersion9_0_3 : SubtargetFeatureISAVersion <9,0,3,
568  [FeatureGFX9,
569   FeatureLDSBankCount32,
570   FeatureXNACK]>;
571
572//===----------------------------------------------------------------------===//
573// Debugger related subtarget features.
574//===----------------------------------------------------------------------===//
575
576def FeatureDebuggerInsertNops : SubtargetFeature<
577  "amdgpu-debugger-insert-nops",
578  "DebuggerInsertNops",
579  "true",
580  "Insert one nop instruction for each high level source statement"
581>;
582
583def FeatureDebuggerReserveRegs : SubtargetFeature<
584  "amdgpu-debugger-reserve-regs",
585  "DebuggerReserveRegs",
586  "true",
587  "Reserve registers for debugger usage"
588>;
589
590def FeatureDebuggerEmitPrologue : SubtargetFeature<
591  "amdgpu-debugger-emit-prologue",
592  "DebuggerEmitPrologue",
593  "true",
594  "Emit debugger prologue"
595>;
596
597//===----------------------------------------------------------------------===//
598
599def AMDGPUInstrInfo : InstrInfo {
600  let guessInstructionProperties = 1;
601  let noNamedPositionallyEncodedOperands = 1;
602}
603
604def AMDGPUAsmParser : AsmParser {
605  // Some of the R600 registers have the same name, so this crashes.
606  // For example T0_XYZW and T0_XY both have the asm name T0.
607  let ShouldEmitMatchRegisterName = 0;
608}
609
610def AMDGPUAsmWriter : AsmWriter {
611  int PassSubtarget = 1;
612}
613
614def AMDGPUAsmVariants {
615  string Default = "Default";
616  int Default_ID = 0;
617  string VOP3 = "VOP3";
618  int VOP3_ID = 1;
619  string SDWA = "SDWA";
620  int SDWA_ID = 2;
621  string SDWA9 = "SDWA9";
622  int SDWA9_ID = 3;
623  string DPP = "DPP";
624  int DPP_ID = 4;
625  string Disable = "Disable";
626  int Disable_ID = 5;
627}
628
629def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
630  let Variant = AMDGPUAsmVariants.Default_ID;
631  let Name = AMDGPUAsmVariants.Default;
632}
633
634def VOP3AsmParserVariant : AsmParserVariant {
635  let Variant = AMDGPUAsmVariants.VOP3_ID;
636  let Name = AMDGPUAsmVariants.VOP3;
637}
638
639def SDWAAsmParserVariant : AsmParserVariant {
640  let Variant = AMDGPUAsmVariants.SDWA_ID;
641  let Name = AMDGPUAsmVariants.SDWA;
642}
643
644def SDWA9AsmParserVariant : AsmParserVariant {
645  let Variant = AMDGPUAsmVariants.SDWA9_ID;
646  let Name = AMDGPUAsmVariants.SDWA9;
647}
648
649
650def DPPAsmParserVariant : AsmParserVariant {
651  let Variant = AMDGPUAsmVariants.DPP_ID;
652  let Name = AMDGPUAsmVariants.DPP;
653}
654
655def AMDGPU : Target {
656  // Pull in Instruction Info:
657  let InstructionSet = AMDGPUInstrInfo;
658  let AssemblyParsers = [AMDGPUAsmParser];
659  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
660                                VOP3AsmParserVariant,
661                                SDWAAsmParserVariant,
662                                SDWA9AsmParserVariant,
663                                DPPAsmParserVariant];
664  let AssemblyWriters = [AMDGPUAsmWriter];
665}
666
667// Dummy Instruction itineraries for pseudo instructions
668def ALU_NULL : FuncUnit;
669def NullALU : InstrItinClass;
670
671//===----------------------------------------------------------------------===//
672// Predicate helper class
673//===----------------------------------------------------------------------===//
674
675def TruePredicate : Predicate<"true">;
676
677def isSICI : Predicate<
678  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
679  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
680>, AssemblerPredicate<"!FeatureGCN3Encoding">;
681
682def isVI : Predicate <
683  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
684  AssemblerPredicate<"FeatureGCN3Encoding">;
685
686def isGFX9 : Predicate <
687  "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
688  AssemblerPredicate<"FeatureGFX9Insts">;
689
690// TODO: Either the name to be changed or we simply use IsCI!
691def isCIVI : Predicate <
692  "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
693  AssemblerPredicate<"FeatureCIInsts">;
694
695def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
696  AssemblerPredicate<"FeatureFlatAddressSpace">;
697
698def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
699  AssemblerPredicate<"FeatureFlatGlobalInsts">;
700def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
701  AssemblerPredicate<"FeatureFlatScratchInsts">;
702def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
703  AssemblerPredicate<"FeatureGFX9Insts">;
704
705def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
706  AssemblerPredicate<"FeatureGFX9Insts">;
707
708def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarryInsts()">,
709  AssemblerPredicate<"FeatureAddNoCarryInsts">;
710
711def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarryInsts()">,
712  AssemblerPredicate<"!FeatureAddNoCarryInsts">;
713
714def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
715  AssemblerPredicate<"Feature16BitInsts">;
716def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
717  AssemblerPredicate<"FeatureVOP3P">;
718
719def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
720  AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
721
722def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
723  AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
724
725def HasDPP : Predicate<"Subtarget->hasDPP()">,
726  AssemblerPredicate<"FeatureDPP">;
727
728def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
729  AssemblerPredicate<"FeatureIntClamp">;
730
731def HasMadMix : Predicate<"Subtarget->hasMadMixInsts()">,
732  AssemblerPredicate<"FeatureGFX9Insts">;
733
734def EnableLateCFGStructurize : Predicate<
735  "EnableLateStructurizeCFG">;
736
737// Exists to help track down where SubtargetPredicate isn't set rather
738// than letting tablegen crash with an unhelpful error.
739def InvalidPred : Predicate<"predicate not set on instruction or pattern">;
740
741class PredicateControl {
742  Predicate SubtargetPredicate = InvalidPred;
743  Predicate SIAssemblerPredicate = isSICI;
744  Predicate VIAssemblerPredicate = isVI;
745  list<Predicate> AssemblerPredicates = [];
746  Predicate AssemblerPredicate = TruePredicate;
747  list<Predicate> OtherPredicates = [];
748  list<Predicate> Predicates = !listconcat([SubtargetPredicate,
749                                            AssemblerPredicate],
750                                            AssemblerPredicates,
751                                            OtherPredicates);
752}
753
754class AMDGPUPat<dag pattern, dag result> : Pat<pattern, result>,
755  PredicateControl;
756
757
758// Include AMDGPU TD files
759include "R600Schedule.td"
760include "SISchedule.td"
761include "Processors.td"
762include "AMDGPUInstrInfo.td"
763include "AMDGPUIntrinsics.td"
764include "AMDGPURegisterInfo.td"
765include "AMDGPURegisterBanks.td"
766include "AMDGPUInstructions.td"
767include "AMDGPUCallingConv.td"
768