1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===------------------------------------------------------------===//
9
10include "llvm/Target/Target.td"
11
12//===------------------------------------------------------------===//
13// Subtarget Features (device properties)
14//===------------------------------------------------------------===//
15
16def FeatureFP64 : SubtargetFeature<"fp64",
17  "FP64",
18  "true",
19  "Enable double precision operations"
20>;
21
22def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
23  "FastFMAF32",
24  "true",
25  "Assuming f32 fma is at least as fast as mul + add"
26>;
27
28def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
29  "HalfRate64Ops",
30  "true",
31  "Most fp64 instructions are half rate instead of quarter"
32>;
33
34def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
35  "R600ALUInst",
36  "false",
37  "Older version of ALU instructions encoding"
38>;
39
40def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
41  "HasVertexCache",
42  "true",
43  "Specify use of dedicated vertex cache"
44>;
45
46def FeatureCaymanISA : SubtargetFeature<"caymanISA",
47  "CaymanISA",
48  "true",
49  "Use Cayman ISA"
50>;
51
52def FeatureCFALUBug : SubtargetFeature<"cfalubug",
53  "CFALUBug",
54  "true",
55  "GPU has CF_ALU bug"
56>;
57
58def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
59  "FlatAddressSpace",
60  "true",
61  "Support flat address space"
62>;
63
64def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
65  "FlatInstOffsets",
66  "true",
67  "Flat instructions have immediate offset addressing mode"
68>;
69
70def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
71  "FlatGlobalInsts",
72  "true",
73  "Have global_* flat memory instructions"
74>;
75
76def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
77  "FlatScratchInsts",
78  "true",
79  "Have scratch_* flat memory instructions"
80>;
81
82def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
83  "AddNoCarryInsts",
84  "true",
85  "Have VALU add/sub instructions without carry out"
86>;
87
88def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
89  "UnalignedBufferAccess",
90  "true",
91  "Support unaligned global loads and stores"
92>;
93
94def FeatureTrapHandler: SubtargetFeature<"trap-handler",
95  "TrapHandler",
96  "true",
97  "Trap handler support"
98>;
99
100def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
101  "UnalignedScratchAccess",
102  "true",
103  "Support unaligned scratch loads and stores"
104>;
105
106def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
107  "HasApertureRegs",
108  "true",
109  "Has Memory Aperture Base and Size Registers"
110>;
111
112def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
113  "HasMadMixInsts",
114  "true",
115  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
116>;
117
118// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
119// XNACK. The current default kernel driver setting is:
120// - graphics ring: XNACK disabled
121// - compute ring: XNACK enabled
122//
123// If XNACK is enabled, the VMEM latency can be worse.
124// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
125def FeatureXNACK : SubtargetFeature<"xnack",
126  "EnableXNACK",
127  "true",
128  "Enable XNACK support"
129>;
130
131def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
132  "SGPRInitBug",
133  "true",
134  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
135>;
136
137class SubtargetFeatureFetchLimit <string Value> :
138                          SubtargetFeature <"fetch"#Value,
139  "TexVTXClauseSize",
140  Value,
141  "Limit the maximum number of fetches in a clause to "#Value
142>;
143
144def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
145def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
146
147class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
148  "wavefrontsize"#Value,
149  "WavefrontSize",
150  !cast<string>(Value),
151  "The number of threads per wavefront"
152>;
153
154def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
155def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
156def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
157
158class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
159  "ldsbankcount"#Value,
160  "LDSBankCount",
161  !cast<string>(Value),
162  "The number of LDS banks per compute unit."
163>;
164
165def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
166def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
167
168class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
169  "localmemorysize"#Value,
170  "LocalMemorySize",
171  !cast<string>(Value),
172  "The size of local memory in bytes"
173>;
174
175def FeatureGCN : SubtargetFeature<"gcn",
176  "IsGCN",
177  "true",
178  "GCN or newer GPU"
179>;
180
181def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
182  "GCN3Encoding",
183  "true",
184  "Encoding format for VI"
185>;
186
187def FeatureCIInsts : SubtargetFeature<"ci-insts",
188  "CIInsts",
189  "true",
190  "Additional instructions for CI+"
191>;
192
193def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
194  "GFX9Insts",
195  "true",
196  "Additional instructions for GFX9+"
197>;
198
199def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
200  "HasSMemRealTime",
201  "true",
202  "Has s_memrealtime instruction"
203>;
204
205def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
206  "HasInv2PiInlineImm",
207  "true",
208  "Has 1 / (2 * pi) as inline immediate"
209>;
210
211def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
212  "Has16BitInsts",
213  "true",
214  "Has i16/f16 instructions"
215>;
216
217def FeatureVOP3P : SubtargetFeature<"vop3p",
218  "HasVOP3PInsts",
219  "true",
220  "Has VOP3P packed instructions"
221>;
222
223def FeatureMovrel : SubtargetFeature<"movrel",
224  "HasMovrel",
225  "true",
226  "Has v_movrel*_b32 instructions"
227>;
228
229def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
230  "HasVGPRIndexMode",
231  "true",
232  "Has VGPR mode register indexing"
233>;
234
235def FeatureScalarStores : SubtargetFeature<"scalar-stores",
236  "HasScalarStores",
237  "true",
238  "Has store scalar memory instructions"
239>;
240
241def FeatureSDWA : SubtargetFeature<"sdwa",
242  "HasSDWA",
243  "true",
244  "Support SDWA (Sub-DWORD Addressing) extension"
245>;
246
247def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
248  "HasSDWAOmod",
249  "true",
250  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
251>;
252
253def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
254  "HasSDWAScalar",
255  "true",
256  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
257>;
258
259def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
260  "HasSDWASdst",
261  "true",
262  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
263>;
264
265def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
266  "HasSDWAMac",
267  "true",
268  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
269>;
270
271def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
272  "HasSDWAOutModsVOPC",
273  "true",
274  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
275>;
276
277def FeatureDPP : SubtargetFeature<"dpp",
278  "HasDPP",
279  "true",
280  "Support DPP (Data Parallel Primitives) extension"
281>;
282
283def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
284  "HasIntClamp",
285  "true",
286  "Support clamp for integer destination"
287>;
288
289//===------------------------------------------------------------===//
290// Subtarget Features (options and debugging)
291//===------------------------------------------------------------===//
292
293// Some instructions do not support denormals despite this flag. Using
294// fp32 denormals also causes instructions to run at the double
295// precision rate for the device.
296def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
297  "FP32Denormals",
298  "true",
299  "Enable single precision denormal handling"
300>;
301
302// Denormal handling for fp64 and fp16 is controlled by the same
303// config register when fp16 supported.
304// TODO: Do we need a separate f16 setting when not legal?
305def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
306  "FP64FP16Denormals",
307  "true",
308  "Enable double and half precision denormal handling",
309  [FeatureFP64]
310>;
311
312def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
313  "FP64FP16Denormals",
314  "true",
315  "Enable double and half precision denormal handling",
316  [FeatureFP64, FeatureFP64FP16Denormals]
317>;
318
319def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
320  "FP64FP16Denormals",
321  "true",
322  "Enable half precision denormal handling",
323  [FeatureFP64FP16Denormals]
324>;
325
326def FeatureDX10Clamp : SubtargetFeature<"dx10-clamp",
327  "DX10Clamp",
328  "true",
329  "clamp modifier clamps NaNs to 0.0"
330>;
331
332def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
333  "FPExceptions",
334  "true",
335  "Enable floating point exceptions"
336>;
337
338class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
339  "max-private-element-size-"#size,
340  "MaxPrivateElementSize",
341  !cast<string>(size),
342  "Maximum private access size may be "#size
343>;
344
345def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
346def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
347def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
348
349def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
350  "EnableVGPRSpilling",
351  "true",
352  "Enable spilling of VGPRs to scratch memory"
353>;
354
355def FeatureDumpCode : SubtargetFeature <"DumpCode",
356  "DumpCode",
357  "true",
358  "Dump MachineInstrs in the CodeEmitter"
359>;
360
361def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
362  "DumpCode",
363  "true",
364  "Dump MachineInstrs in the CodeEmitter"
365>;
366
367def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
368  "EnablePromoteAlloca",
369  "true",
370  "Enable promote alloca pass"
371>;
372
373// XXX - This should probably be removed once enabled by default
374def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
375  "EnableLoadStoreOpt",
376  "true",
377  "Enable SI load/store optimizer pass"
378>;
379
380// Performance debugging feature. Allow using DS instruction immediate
381// offsets even if the base pointer can't be proven to be base. On SI,
382// base pointer values that won't give the same result as a 16-bit add
383// are not safe to fold, but this will override the conservative test
384// for the base pointer.
385def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
386  "unsafe-ds-offset-folding",
387  "EnableUnsafeDSOffsetFolding",
388  "true",
389  "Force using DS instruction immediate offsets on SI"
390>;
391
392def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
393  "EnableSIScheduler",
394  "true",
395  "Enable SI Machine Scheduler"
396>;
397
398// Unless +-flat-for-global is specified, turn on FlatForGlobal for
399// all OS-es on VI and newer hardware to avoid assertion failures due
400// to missing ADDR64 variants of MUBUF instructions.
401// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
402// instructions.
403
404def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
405  "FlatForGlobal",
406  "true",
407  "Force to generate flat instruction for global"
408>;
409
410def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
411  "auto-waitcnt-before-barrier",
412  "AutoWaitcntBeforeBarrier",
413  "true",
414  "Hardware automatically inserts waitcnt before barrier"
415>;
416
417def FeatureCodeObjectV3 : SubtargetFeature <
418  "code-object-v3",
419  "CodeObjectV3",
420  "true",
421  "Generate code object version 3"
422>;
423
424// Dummy feature used to disable assembler instructions.
425def FeatureDisable : SubtargetFeature<"",
426  "FeatureDisable","true",
427  "Dummy feature to disable assembler instructions"
428>;
429
430class SubtargetFeatureGeneration <string Value,
431                                  list<SubtargetFeature> Implies> :
432        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
433                          Value#" GPU generation", Implies>;
434
435def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
436def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
437def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
438
439def FeatureR600 : SubtargetFeatureGeneration<"R600",
440  [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]
441>;
442
443def FeatureR700 : SubtargetFeatureGeneration<"R700",
444  [FeatureFetchLimit16, FeatureLocalMemorySize0]
445>;
446
447def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
448  [FeatureFetchLimit16, FeatureLocalMemorySize32768]
449>;
450
451def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
452  [FeatureFetchLimit16, FeatureWavefrontSize64,
453   FeatureLocalMemorySize32768]
454>;
455
456def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
457  [FeatureFP64, FeatureLocalMemorySize32768,
458  FeatureWavefrontSize64, FeatureGCN,
459  FeatureLDSBankCount32, FeatureMovrel]
460>;
461
462def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
463  [FeatureFP64, FeatureLocalMemorySize65536,
464  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
465  FeatureCIInsts, FeatureMovrel]
466>;
467
468def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
469  [FeatureFP64, FeatureLocalMemorySize65536,
470   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
471   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
472   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
473   FeatureScalarStores, FeatureInv2PiInlineImm,
474   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
475   FeatureIntClamp
476  ]
477>;
478
479def FeatureGFX9 : SubtargetFeatureGeneration<"GFX9",
480  [FeatureFP64, FeatureLocalMemorySize65536,
481   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
482   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
483   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
484   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
485   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
486   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
487   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
488   FeatureAddNoCarryInsts
489  ]
490>;
491
492class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
493                                  list<SubtargetFeature> Implies>
494                                 : SubtargetFeature <
495  "isaver"#Major#"."#Minor#"."#Stepping,
496  "IsaVersion",
497  "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
498  "Instruction set version number",
499  Implies
500>;
501
502def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
503  [FeatureSouthernIslands,
504   FeatureFastFMAF32,
505   HalfRate64Ops,
506   FeatureLDSBankCount32]>;
507
508def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
509  [FeatureSouthernIslands,
510   FeatureLDSBankCount32]>;
511
512def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
513  [FeatureSeaIslands,
514   FeatureLDSBankCount32]>;
515
516def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
517  [FeatureSeaIslands,
518   HalfRate64Ops,
519   FeatureLDSBankCount32,
520   FeatureFastFMAF32]>;
521
522def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
523  [FeatureSeaIslands,
524   FeatureLDSBankCount16]>;
525
526def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
527  [FeatureSeaIslands,
528   FeatureLDSBankCount16]>;
529
530def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0,
531  [FeatureVolcanicIslands,
532   FeatureLDSBankCount32,
533   FeatureSGPRInitBug]>;
534
535def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
536  [FeatureVolcanicIslands,
537   FeatureFastFMAF32,
538   HalfRate64Ops,
539   FeatureLDSBankCount32,
540   FeatureXNACK]>;
541
542def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
543  [FeatureVolcanicIslands,
544   FeatureLDSBankCount32,
545   FeatureSGPRInitBug]>;
546
547def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
548  [FeatureVolcanicIslands,
549   FeatureLDSBankCount32]>;
550
551def FeatureISAVersion8_0_4 : SubtargetFeatureISAVersion <8,0,4,
552  [FeatureVolcanicIslands,
553   FeatureLDSBankCount32]>;
554
555def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
556  [FeatureVolcanicIslands,
557   FeatureLDSBankCount16,
558   FeatureXNACK]>;
559
560def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
561  [FeatureGFX9,
562   FeatureMadMixInsts,
563   FeatureLDSBankCount32
564   ]>;
565
566def FeatureISAVersion9_0_1 : SubtargetFeatureISAVersion <9,0,1,
567  [FeatureGFX9,
568   FeatureMadMixInsts,
569   FeatureLDSBankCount32,
570   FeatureXNACK]>;
571
572def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
573  [FeatureGFX9,
574   FeatureMadMixInsts,
575   FeatureLDSBankCount32
576   ]>;
577
578def FeatureISAVersion9_0_3 : SubtargetFeatureISAVersion <9,0,3,
579  [FeatureGFX9,
580   FeatureMadMixInsts,
581   FeatureLDSBankCount32,
582   FeatureXNACK]>;
583
584//===----------------------------------------------------------------------===//
585// Debugger related subtarget features.
586//===----------------------------------------------------------------------===//
587
588def FeatureDebuggerInsertNops : SubtargetFeature<
589  "amdgpu-debugger-insert-nops",
590  "DebuggerInsertNops",
591  "true",
592  "Insert one nop instruction for each high level source statement"
593>;
594
595def FeatureDebuggerReserveRegs : SubtargetFeature<
596  "amdgpu-debugger-reserve-regs",
597  "DebuggerReserveRegs",
598  "true",
599  "Reserve registers for debugger usage"
600>;
601
602def FeatureDebuggerEmitPrologue : SubtargetFeature<
603  "amdgpu-debugger-emit-prologue",
604  "DebuggerEmitPrologue",
605  "true",
606  "Emit debugger prologue"
607>;
608
609//===----------------------------------------------------------------------===//
610
611def AMDGPUInstrInfo : InstrInfo {
612  let guessInstructionProperties = 1;
613  let noNamedPositionallyEncodedOperands = 1;
614}
615
616def AMDGPUAsmParser : AsmParser {
617  // Some of the R600 registers have the same name, so this crashes.
618  // For example T0_XYZW and T0_XY both have the asm name T0.
619  let ShouldEmitMatchRegisterName = 0;
620}
621
622def AMDGPUAsmWriter : AsmWriter {
623  int PassSubtarget = 1;
624}
625
626def AMDGPUAsmVariants {
627  string Default = "Default";
628  int Default_ID = 0;
629  string VOP3 = "VOP3";
630  int VOP3_ID = 1;
631  string SDWA = "SDWA";
632  int SDWA_ID = 2;
633  string SDWA9 = "SDWA9";
634  int SDWA9_ID = 3;
635  string DPP = "DPP";
636  int DPP_ID = 4;
637  string Disable = "Disable";
638  int Disable_ID = 5;
639}
640
641def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
642  let Variant = AMDGPUAsmVariants.Default_ID;
643  let Name = AMDGPUAsmVariants.Default;
644}
645
646def VOP3AsmParserVariant : AsmParserVariant {
647  let Variant = AMDGPUAsmVariants.VOP3_ID;
648  let Name = AMDGPUAsmVariants.VOP3;
649}
650
651def SDWAAsmParserVariant : AsmParserVariant {
652  let Variant = AMDGPUAsmVariants.SDWA_ID;
653  let Name = AMDGPUAsmVariants.SDWA;
654}
655
656def SDWA9AsmParserVariant : AsmParserVariant {
657  let Variant = AMDGPUAsmVariants.SDWA9_ID;
658  let Name = AMDGPUAsmVariants.SDWA9;
659}
660
661
662def DPPAsmParserVariant : AsmParserVariant {
663  let Variant = AMDGPUAsmVariants.DPP_ID;
664  let Name = AMDGPUAsmVariants.DPP;
665}
666
667def AMDGPU : Target {
668  // Pull in Instruction Info:
669  let InstructionSet = AMDGPUInstrInfo;
670  let AssemblyParsers = [AMDGPUAsmParser];
671  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
672                                VOP3AsmParserVariant,
673                                SDWAAsmParserVariant,
674                                SDWA9AsmParserVariant,
675                                DPPAsmParserVariant];
676  let AssemblyWriters = [AMDGPUAsmWriter];
677}
678
679// Dummy Instruction itineraries for pseudo instructions
680def ALU_NULL : FuncUnit;
681def NullALU : InstrItinClass;
682
683//===----------------------------------------------------------------------===//
684// Predicate helper class
685//===----------------------------------------------------------------------===//
686
687def TruePredicate : Predicate<"true">;
688
689def isSICI : Predicate<
690  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
691  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
692>, AssemblerPredicate<"!FeatureGCN3Encoding">;
693
694def isVI : Predicate <
695  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
696  AssemblerPredicate<"FeatureGCN3Encoding">;
697
698def isGFX9 : Predicate <
699  "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
700  AssemblerPredicate<"FeatureGFX9Insts">;
701
702// TODO: Either the name to be changed or we simply use IsCI!
703def isCIVI : Predicate <
704  "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
705  AssemblerPredicate<"FeatureCIInsts">;
706
707def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
708  AssemblerPredicate<"FeatureFlatAddressSpace">;
709
710def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
711  AssemblerPredicate<"FeatureFlatGlobalInsts">;
712def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
713  AssemblerPredicate<"FeatureFlatScratchInsts">;
714def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
715  AssemblerPredicate<"FeatureGFX9Insts">;
716
717def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
718  AssemblerPredicate<"FeatureGFX9Insts">;
719
720def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarryInsts()">,
721  AssemblerPredicate<"FeatureAddNoCarryInsts">;
722
723def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarryInsts()">,
724  AssemblerPredicate<"!FeatureAddNoCarryInsts">;
725
726def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
727  AssemblerPredicate<"Feature16BitInsts">;
728def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
729  AssemblerPredicate<"FeatureVOP3P">;
730
731def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
732  AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
733
734def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
735  AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
736
737def HasDPP : Predicate<"Subtarget->hasDPP()">,
738  AssemblerPredicate<"FeatureDPP">;
739
740def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
741  AssemblerPredicate<"FeatureIntClamp">;
742
743def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
744  AssemblerPredicate<"FeatureMadMixInsts">;
745
746def EnableLateCFGStructurize : Predicate<
747  "EnableLateStructurizeCFG">;
748
749// Exists to help track down where SubtargetPredicate isn't set rather
750// than letting tablegen crash with an unhelpful error.
751def InvalidPred : Predicate<"predicate not set on instruction or pattern">;
752
753class PredicateControl {
754  Predicate SubtargetPredicate = InvalidPred;
755  Predicate SIAssemblerPredicate = isSICI;
756  Predicate VIAssemblerPredicate = isVI;
757  list<Predicate> AssemblerPredicates = [];
758  Predicate AssemblerPredicate = TruePredicate;
759  list<Predicate> OtherPredicates = [];
760  list<Predicate> Predicates = !listconcat([SubtargetPredicate,
761                                            AssemblerPredicate],
762                                            AssemblerPredicates,
763                                            OtherPredicates);
764}
765
766class AMDGPUPat<dag pattern, dag result> : Pat<pattern, result>,
767  PredicateControl;
768
769
770// Include AMDGPU TD files
771include "R600Schedule.td"
772include "SISchedule.td"
773include "Processors.td"
774include "AMDGPUInstrInfo.td"
775include "AMDGPUIntrinsics.td"
776include "AMDGPURegisterInfo.td"
777include "AMDGPURegisterBanks.td"
778include "AMDGPUInstructions.td"
779include "AMDGPUCallingConv.td"
780