1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===------------------------------------------------------------===//
9
10include "llvm/TableGen/SearchableTable.td"
11include "llvm/Target/Target.td"
12include "AMDGPUFeatures.td"
13
14//===------------------------------------------------------------===//
15// Subtarget Features (device properties)
16//===------------------------------------------------------------===//
17
18def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
19  "FastFMAF32",
20  "true",
21  "Assuming f32 fma is at least as fast as mul + add"
22>;
23
24def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
25  "MIMG_R128",
26  "true",
27  "Support 128-bit texture resources"
28>;
29
30def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
31  "HalfRate64Ops",
32  "true",
33  "Most fp64 instructions are half rate instead of quarter"
34>;
35
36def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
37  "FlatAddressSpace",
38  "true",
39  "Support flat address space"
40>;
41
42def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
43  "FlatInstOffsets",
44  "true",
45  "Flat instructions have immediate offset addressing mode"
46>;
47
48def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
49  "FlatGlobalInsts",
50  "true",
51  "Have global_* flat memory instructions"
52>;
53
54def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
55  "FlatScratchInsts",
56  "true",
57  "Have scratch_* flat memory instructions"
58>;
59
60def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
61  "AddNoCarryInsts",
62  "true",
63  "Have VALU add/sub instructions without carry out"
64>;
65
66def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
67  "UnalignedBufferAccess",
68  "true",
69  "Support unaligned global loads and stores"
70>;
71
72def FeatureTrapHandler: SubtargetFeature<"trap-handler",
73  "TrapHandler",
74  "true",
75  "Trap handler support"
76>;
77
78def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
79  "UnalignedScratchAccess",
80  "true",
81  "Support unaligned scratch loads and stores"
82>;
83
84def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
85  "HasApertureRegs",
86  "true",
87  "Has Memory Aperture Base and Size Registers"
88>;
89
90def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
91  "HasMadMixInsts",
92  "true",
93  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
94>;
95
96def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
97  "HasFmaMixInsts",
98  "true",
99  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
100>;
101
102// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
103// XNACK. The current default kernel driver setting is:
104// - graphics ring: XNACK disabled
105// - compute ring: XNACK enabled
106//
107// If XNACK is enabled, the VMEM latency can be worse.
108// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
109def FeatureXNACK : SubtargetFeature<"xnack",
110  "EnableXNACK",
111  "true",
112  "Enable XNACK support"
113>;
114
115def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
116  "SGPRInitBug",
117  "true",
118  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
119>;
120
121class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
122  "ldsbankcount"#Value,
123  "LDSBankCount",
124  !cast<string>(Value),
125  "The number of LDS banks per compute unit."
126>;
127
128def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
129def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
130
131def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
132  "GCN3Encoding",
133  "true",
134  "Encoding format for VI"
135>;
136
137def FeatureCIInsts : SubtargetFeature<"ci-insts",
138  "CIInsts",
139  "true",
140  "Additional instructions for CI+"
141>;
142
143def FeatureVIInsts : SubtargetFeature<"vi-insts",
144  "VIInsts",
145  "true",
146  "Additional instructions for VI+"
147>;
148
149def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
150  "GFX9Insts",
151  "true",
152  "Additional instructions for GFX9+"
153>;
154
155def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
156  "HasSMemRealTime",
157  "true",
158  "Has s_memrealtime instruction"
159>;
160
161def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
162  "HasInv2PiInlineImm",
163  "true",
164  "Has 1 / (2 * pi) as inline immediate"
165>;
166
167def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
168  "Has16BitInsts",
169  "true",
170  "Has i16/f16 instructions"
171>;
172
173def FeatureVOP3P : SubtargetFeature<"vop3p",
174  "HasVOP3PInsts",
175  "true",
176  "Has VOP3P packed instructions"
177>;
178
179def FeatureMovrel : SubtargetFeature<"movrel",
180  "HasMovrel",
181  "true",
182  "Has v_movrel*_b32 instructions"
183>;
184
185def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
186  "HasVGPRIndexMode",
187  "true",
188  "Has VGPR mode register indexing"
189>;
190
191def FeatureScalarStores : SubtargetFeature<"scalar-stores",
192  "HasScalarStores",
193  "true",
194  "Has store scalar memory instructions"
195>;
196
197def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
198  "HasScalarAtomics",
199  "true",
200  "Has atomic scalar memory instructions"
201>;
202
203def FeatureSDWA : SubtargetFeature<"sdwa",
204  "HasSDWA",
205  "true",
206  "Support SDWA (Sub-DWORD Addressing) extension"
207>;
208
209def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
210  "HasSDWAOmod",
211  "true",
212  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
213>;
214
215def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
216  "HasSDWAScalar",
217  "true",
218  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
219>;
220
221def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
222  "HasSDWASdst",
223  "true",
224  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
225>;
226
227def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
228  "HasSDWAMac",
229  "true",
230  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
231>;
232
233def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
234  "HasSDWAOutModsVOPC",
235  "true",
236  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
237>;
238
239def FeatureDPP : SubtargetFeature<"dpp",
240  "HasDPP",
241  "true",
242  "Support DPP (Data Parallel Primitives) extension"
243>;
244
245def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
246  "HasIntClamp",
247  "true",
248  "Support clamp for integer destination"
249>;
250
251def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
252  "HasUnpackedD16VMem",
253  "true",
254  "Has unpacked d16 vmem instructions"
255>;
256
257def FeatureDLInsts : SubtargetFeature<"dl-insts",
258  "HasDLInsts",
259  "true",
260  "Has deep learning instructions"
261>;
262
263def FeatureD16PreservesUnusedBits : SubtargetFeature<
264  "d16-preserves-unused-bits",
265  "D16PreservesUnusedBits",
266  "true",
267  "If present, then instructions defined by HasD16LoadStore predicate preserve "
268  "unused bits. Otherwise instructions defined by HasD16LoadStore predicate "
269  "zero unused bits."
270>;
271
272//===------------------------------------------------------------===//
273// Subtarget Features (options and debugging)
274//===------------------------------------------------------------===//
275
276// Denormal handling for fp64 and fp16 is controlled by the same
277// config register when fp16 supported.
278// TODO: Do we need a separate f16 setting when not legal?
279def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
280  "FP64FP16Denormals",
281  "true",
282  "Enable double and half precision denormal handling",
283  [FeatureFP64]
284>;
285
286def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
287  "FP64FP16Denormals",
288  "true",
289  "Enable double and half precision denormal handling",
290  [FeatureFP64, FeatureFP64FP16Denormals]
291>;
292
293def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
294  "FP64FP16Denormals",
295  "true",
296  "Enable half precision denormal handling",
297  [FeatureFP64FP16Denormals]
298>;
299
300def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
301  "FPExceptions",
302  "true",
303  "Enable floating point exceptions"
304>;
305
306class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
307  "max-private-element-size-"#size,
308  "MaxPrivateElementSize",
309  !cast<string>(size),
310  "Maximum private access size may be "#size
311>;
312
313def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
314def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
315def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
316
317def FeatureEnableHugePrivateBuffer : SubtargetFeature<
318  "huge-private-buffer",
319  "EnableHugePrivateBuffer",
320  "true",
321  "Enable private/scratch buffer sizes greater than 128 GB"
322>;
323
324def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
325  "EnableVGPRSpilling",
326  "true",
327  "Enable spilling of VGPRs to scratch memory"
328>;
329
330def FeatureDumpCode : SubtargetFeature <"DumpCode",
331  "DumpCode",
332  "true",
333  "Dump MachineInstrs in the CodeEmitter"
334>;
335
336def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
337  "DumpCode",
338  "true",
339  "Dump MachineInstrs in the CodeEmitter"
340>;
341
342// XXX - This should probably be removed once enabled by default
343def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
344  "EnableLoadStoreOpt",
345  "true",
346  "Enable SI load/store optimizer pass"
347>;
348
349// Performance debugging feature. Allow using DS instruction immediate
350// offsets even if the base pointer can't be proven to be base. On SI,
351// base pointer values that won't give the same result as a 16-bit add
352// are not safe to fold, but this will override the conservative test
353// for the base pointer.
354def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
355  "unsafe-ds-offset-folding",
356  "EnableUnsafeDSOffsetFolding",
357  "true",
358  "Force using DS instruction immediate offsets on SI"
359>;
360
361def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
362  "EnableSIScheduler",
363  "true",
364  "Enable SI Machine Scheduler"
365>;
366
367def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
368  "EnableDS128",
369  "true",
370  "Use ds_{read|write}_b128"
371>;
372
373// Unless +-flat-for-global is specified, turn on FlatForGlobal for
374// all OS-es on VI and newer hardware to avoid assertion failures due
375// to missing ADDR64 variants of MUBUF instructions.
376// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
377// instructions.
378
379def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
380  "FlatForGlobal",
381  "true",
382  "Force to generate flat instruction for global"
383>;
384
385def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
386  "auto-waitcnt-before-barrier",
387  "AutoWaitcntBeforeBarrier",
388  "true",
389  "Hardware automatically inserts waitcnt before barrier"
390>;
391
392def FeatureCodeObjectV3 : SubtargetFeature <
393  "code-object-v3",
394  "CodeObjectV3",
395  "true",
396  "Generate code object version 3"
397>;
398
399// Dummy feature used to disable assembler instructions.
400def FeatureDisable : SubtargetFeature<"",
401  "FeatureDisable","true",
402  "Dummy feature to disable assembler instructions"
403>;
404
405def FeatureGCN : SubtargetFeature<"gcn",
406  "IsGCN",
407  "true",
408  "GCN or newer GPU"
409>;
410
411class GCNSubtargetFeatureGeneration <string Value,
412                                  list<SubtargetFeature> Implies> :
413        SubtargetFeatureGeneration <Value, "GCNSubtarget", Implies>;
414
415def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
416  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
417  FeatureWavefrontSize64, FeatureGCN,
418  FeatureLDSBankCount32, FeatureMovrel]
419>;
420
421def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
422  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
423  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
424  FeatureCIInsts, FeatureMovrel]
425>;
426
427def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
428  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
429   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
430   FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts,
431   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
432   FeatureScalarStores, FeatureInv2PiInlineImm,
433   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
434   FeatureIntClamp
435  ]
436>;
437
438def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
439  [FeatureFP64, FeatureLocalMemorySize65536,
440   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
441   FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts,
442   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
443   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
444   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
445   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
446   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
447   FeatureAddNoCarryInsts, FeatureScalarAtomics
448  ]
449>;
450
451class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
452                                  list<SubtargetFeature> Implies>
453                                 : SubtargetFeature <
454  "isaver"#Major#"."#Minor#"."#Stepping,
455  "IsaVersion",
456  "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
457  "Instruction set version number",
458  Implies
459>;
460
461def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
462  [FeatureSouthernIslands,
463   FeatureFastFMAF32,
464   HalfRate64Ops,
465   FeatureLDSBankCount32]>;
466
467def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
468  [FeatureSouthernIslands,
469   FeatureLDSBankCount32]>;
470
471def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
472  [FeatureSeaIslands,
473   FeatureLDSBankCount32]>;
474
475def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
476  [FeatureSeaIslands,
477   HalfRate64Ops,
478   FeatureLDSBankCount32,
479   FeatureFastFMAF32]>;
480
481def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
482  [FeatureSeaIslands,
483   FeatureLDSBankCount16,
484   FeatureFastFMAF32]>;
485
486def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
487  [FeatureSeaIslands,
488   FeatureLDSBankCount16]>;
489
490def FeatureISAVersion7_0_4 : SubtargetFeatureISAVersion <7,0,4,
491  [FeatureSeaIslands,
492   FeatureLDSBankCount32]>;
493
494def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
495  [FeatureVolcanicIslands,
496   FeatureFastFMAF32,
497   HalfRate64Ops,
498   FeatureLDSBankCount32,
499   FeatureXNACK,
500   FeatureUnpackedD16VMem]>;
501
502def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
503  [FeatureVolcanicIslands,
504   FeatureLDSBankCount32,
505   FeatureSGPRInitBug,
506   FeatureUnpackedD16VMem]>;
507
508def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
509  [FeatureVolcanicIslands,
510   FeatureLDSBankCount32,
511   FeatureUnpackedD16VMem]>;
512
513def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
514  [FeatureVolcanicIslands,
515   FeatureLDSBankCount16,
516   FeatureXNACK]>;
517
518def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
519  [FeatureGFX9,
520   FeatureMadMixInsts,
521   FeatureLDSBankCount32,
522   FeatureD16PreservesUnusedBits]>;
523
524def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
525  [FeatureGFX9,
526   FeatureMadMixInsts,
527   FeatureLDSBankCount32,
528   FeatureXNACK,
529   FeatureD16PreservesUnusedBits]>;
530
531def FeatureISAVersion9_0_4 : SubtargetFeatureISAVersion <9,0,4,
532  [FeatureGFX9,
533   FeatureLDSBankCount32,
534   FeatureFmaMixInsts,
535   FeatureD16PreservesUnusedBits]>;
536
537def FeatureISAVersion9_0_6 : SubtargetFeatureISAVersion <9,0,6,
538  [FeatureGFX9,
539   HalfRate64Ops,
540   FeatureFmaMixInsts,
541   FeatureLDSBankCount32,
542   FeatureDLInsts]>;
543
544//===----------------------------------------------------------------------===//
545// Debugger related subtarget features.
546//===----------------------------------------------------------------------===//
547
548def FeatureDebuggerInsertNops : SubtargetFeature<
549  "amdgpu-debugger-insert-nops",
550  "DebuggerInsertNops",
551  "true",
552  "Insert one nop instruction for each high level source statement"
553>;
554
555def FeatureDebuggerEmitPrologue : SubtargetFeature<
556  "amdgpu-debugger-emit-prologue",
557  "DebuggerEmitPrologue",
558  "true",
559  "Emit debugger prologue"
560>;
561
562//===----------------------------------------------------------------------===//
563
564def AMDGPUInstrInfo : InstrInfo {
565  let guessInstructionProperties = 1;
566  let noNamedPositionallyEncodedOperands = 1;
567}
568
569def AMDGPUAsmParser : AsmParser {
570  // Some of the R600 registers have the same name, so this crashes.
571  // For example T0_XYZW and T0_XY both have the asm name T0.
572  let ShouldEmitMatchRegisterName = 0;
573}
574
575def AMDGPUAsmWriter : AsmWriter {
576  int PassSubtarget = 1;
577}
578
579def AMDGPUAsmVariants {
580  string Default = "Default";
581  int Default_ID = 0;
582  string VOP3 = "VOP3";
583  int VOP3_ID = 1;
584  string SDWA = "SDWA";
585  int SDWA_ID = 2;
586  string SDWA9 = "SDWA9";
587  int SDWA9_ID = 3;
588  string DPP = "DPP";
589  int DPP_ID = 4;
590  string Disable = "Disable";
591  int Disable_ID = 5;
592}
593
594def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
595  let Variant = AMDGPUAsmVariants.Default_ID;
596  let Name = AMDGPUAsmVariants.Default;
597}
598
599def VOP3AsmParserVariant : AsmParserVariant {
600  let Variant = AMDGPUAsmVariants.VOP3_ID;
601  let Name = AMDGPUAsmVariants.VOP3;
602}
603
604def SDWAAsmParserVariant : AsmParserVariant {
605  let Variant = AMDGPUAsmVariants.SDWA_ID;
606  let Name = AMDGPUAsmVariants.SDWA;
607}
608
609def SDWA9AsmParserVariant : AsmParserVariant {
610  let Variant = AMDGPUAsmVariants.SDWA9_ID;
611  let Name = AMDGPUAsmVariants.SDWA9;
612}
613
614
615def DPPAsmParserVariant : AsmParserVariant {
616  let Variant = AMDGPUAsmVariants.DPP_ID;
617  let Name = AMDGPUAsmVariants.DPP;
618}
619
620def AMDGPU : Target {
621  // Pull in Instruction Info:
622  let InstructionSet = AMDGPUInstrInfo;
623  let AssemblyParsers = [AMDGPUAsmParser];
624  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
625                                VOP3AsmParserVariant,
626                                SDWAAsmParserVariant,
627                                SDWA9AsmParserVariant,
628                                DPPAsmParserVariant];
629  let AssemblyWriters = [AMDGPUAsmWriter];
630  let AllowRegisterRenaming = 1;
631}
632
633// Dummy Instruction itineraries for pseudo instructions
634def ALU_NULL : FuncUnit;
635def NullALU : InstrItinClass;
636
637//===----------------------------------------------------------------------===//
638// Predicate helper class
639//===----------------------------------------------------------------------===//
640
641def isSICI : Predicate<
642  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
643  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
644>, AssemblerPredicate<"!FeatureGCN3Encoding">;
645
646def isVI : Predicate <
647  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
648  AssemblerPredicate<"FeatureGCN3Encoding">;
649
650def isGFX9 : Predicate <
651  "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
652  AssemblerPredicate<"FeatureGFX9Insts">;
653
654// TODO: Either the name to be changed or we simply use IsCI!
655def isCIVI : Predicate <
656  "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
657  AssemblerPredicate<"FeatureCIInsts">;
658
659def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
660  AssemblerPredicate<"FeatureFlatAddressSpace">;
661
662def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
663  AssemblerPredicate<"FeatureFlatGlobalInsts">;
664def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
665  AssemblerPredicate<"FeatureFlatScratchInsts">;
666def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
667  AssemblerPredicate<"FeatureGFX9Insts">;
668
669def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
670  AssemblerPredicate<"FeatureUnpackedD16VMem">;
671def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
672  AssemblerPredicate<"!FeatureUnpackedD16VMem">;
673
674def D16PreservesUnusedBits : Predicate<"Subtarget->d16PreservesUnusedBits()">,
675  AssemblerPredicate<"FeatureD16PreservesUnusedBits">;
676
677def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
678def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
679
680def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
681  AssemblerPredicate<"FeatureGFX9Insts">;
682
683def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarryInsts()">,
684  AssemblerPredicate<"FeatureAddNoCarryInsts">;
685
686def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarryInsts()">,
687  AssemblerPredicate<"!FeatureAddNoCarryInsts">;
688
689def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
690  AssemblerPredicate<"Feature16BitInsts">;
691def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
692  AssemblerPredicate<"FeatureVOP3P">;
693
694def NotHasVOP3PInsts : Predicate<"!Subtarget->hasVOP3PInsts()">,
695  AssemblerPredicate<"!FeatureVOP3P">;
696
697def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
698  AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
699
700def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
701  AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
702
703def HasDPP : Predicate<"Subtarget->hasDPP()">,
704  AssemblerPredicate<"FeatureDPP">;
705
706def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
707  AssemblerPredicate<"FeatureIntClamp">;
708
709def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
710  AssemblerPredicate<"FeatureMadMixInsts">;
711
712def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
713  AssemblerPredicate<"FeatureScalarAtomics">;
714
715def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
716def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
717def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
718                      AssemblerPredicate<"FeatureVGPRIndexMode">;
719def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
720                AssemblerPredicate<"FeatureMovrel">;
721
722def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
723  AssemblerPredicate<"FeatureFmaMixInsts">;
724
725def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
726  AssemblerPredicate<"FeatureDLInsts">;
727
728
729def EnableLateCFGStructurize : Predicate<
730  "EnableLateStructurizeCFG">;
731
732// Include AMDGPU TD files
733include "SISchedule.td"
734include "GCNProcessors.td"
735include "AMDGPUInstrInfo.td"
736include "AMDGPUIntrinsics.td"
737include "SIIntrinsics.td"
738include "AMDGPURegisterInfo.td"
739include "AMDGPURegisterBanks.td"
740include "AMDGPUInstructions.td"
741include "SIInstrInfo.td"
742include "AMDGPUCallingConv.td"
743include "AMDGPUSearchableTables.td"
744