1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===------------------------------------------------------------===//
9
10include "llvm/Target/Target.td"
11
12//===------------------------------------------------------------===//
13// Subtarget Features (device properties)
14//===------------------------------------------------------------===//
15
16def FeatureFP64 : SubtargetFeature<"fp64",
17  "FP64",
18  "true",
19  "Enable double precision operations"
20>;
21
22def FeatureFMA : SubtargetFeature<"fmaf",
23  "FMA",
24  "true",
25  "Enable single precision FMA (not as fast as mul+add, but fused)"
26>;
27
28def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
29  "FastFMAF32",
30  "true",
31  "Assuming f32 fma is at least as fast as mul + add"
32>;
33
34def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
35  "MIMG_R128",
36  "true",
37  "Support 128-bit texture resources"
38>;
39
40def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
41  "HalfRate64Ops",
42  "true",
43  "Most fp64 instructions are half rate instead of quarter"
44>;
45
46def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
47  "R600ALUInst",
48  "false",
49  "Older version of ALU instructions encoding"
50>;
51
52def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
53  "HasVertexCache",
54  "true",
55  "Specify use of dedicated vertex cache"
56>;
57
58def FeatureCaymanISA : SubtargetFeature<"caymanISA",
59  "CaymanISA",
60  "true",
61  "Use Cayman ISA"
62>;
63
64def FeatureCFALUBug : SubtargetFeature<"cfalubug",
65  "CFALUBug",
66  "true",
67  "GPU has CF_ALU bug"
68>;
69
70def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
71  "FlatAddressSpace",
72  "true",
73  "Support flat address space"
74>;
75
76def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
77  "FlatInstOffsets",
78  "true",
79  "Flat instructions have immediate offset addressing mode"
80>;
81
82def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
83  "FlatGlobalInsts",
84  "true",
85  "Have global_* flat memory instructions"
86>;
87
88def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
89  "FlatScratchInsts",
90  "true",
91  "Have scratch_* flat memory instructions"
92>;
93
94def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
95  "AddNoCarryInsts",
96  "true",
97  "Have VALU add/sub instructions without carry out"
98>;
99
100def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
101  "UnalignedBufferAccess",
102  "true",
103  "Support unaligned global loads and stores"
104>;
105
106def FeatureTrapHandler: SubtargetFeature<"trap-handler",
107  "TrapHandler",
108  "true",
109  "Trap handler support"
110>;
111
112def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
113  "UnalignedScratchAccess",
114  "true",
115  "Support unaligned scratch loads and stores"
116>;
117
118def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
119  "HasApertureRegs",
120  "true",
121  "Has Memory Aperture Base and Size Registers"
122>;
123
124def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
125  "HasMadMixInsts",
126  "true",
127  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
128>;
129
130// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
131// XNACK. The current default kernel driver setting is:
132// - graphics ring: XNACK disabled
133// - compute ring: XNACK enabled
134//
135// If XNACK is enabled, the VMEM latency can be worse.
136// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
137def FeatureXNACK : SubtargetFeature<"xnack",
138  "EnableXNACK",
139  "true",
140  "Enable XNACK support"
141>;
142
143def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
144  "SGPRInitBug",
145  "true",
146  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
147>;
148
149class SubtargetFeatureFetchLimit <string Value> :
150                          SubtargetFeature <"fetch"#Value,
151  "TexVTXClauseSize",
152  Value,
153  "Limit the maximum number of fetches in a clause to "#Value
154>;
155
156def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
157def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
158
159class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
160  "wavefrontsize"#Value,
161  "WavefrontSize",
162  !cast<string>(Value),
163  "The number of threads per wavefront"
164>;
165
166def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
167def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
168def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
169
170class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
171  "ldsbankcount"#Value,
172  "LDSBankCount",
173  !cast<string>(Value),
174  "The number of LDS banks per compute unit."
175>;
176
177def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
178def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
179
180class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
181  "localmemorysize"#Value,
182  "LocalMemorySize",
183  !cast<string>(Value),
184  "The size of local memory in bytes"
185>;
186
187def FeatureGCN : SubtargetFeature<"gcn",
188  "IsGCN",
189  "true",
190  "GCN or newer GPU"
191>;
192
193def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
194  "GCN3Encoding",
195  "true",
196  "Encoding format for VI"
197>;
198
199def FeatureCIInsts : SubtargetFeature<"ci-insts",
200  "CIInsts",
201  "true",
202  "Additional instructions for CI+"
203>;
204
205def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
206  "GFX9Insts",
207  "true",
208  "Additional instructions for GFX9+"
209>;
210
211def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
212  "HasSMemRealTime",
213  "true",
214  "Has s_memrealtime instruction"
215>;
216
217def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
218  "HasInv2PiInlineImm",
219  "true",
220  "Has 1 / (2 * pi) as inline immediate"
221>;
222
223def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
224  "Has16BitInsts",
225  "true",
226  "Has i16/f16 instructions"
227>;
228
229def FeatureVOP3P : SubtargetFeature<"vop3p",
230  "HasVOP3PInsts",
231  "true",
232  "Has VOP3P packed instructions"
233>;
234
235def FeatureMovrel : SubtargetFeature<"movrel",
236  "HasMovrel",
237  "true",
238  "Has v_movrel*_b32 instructions"
239>;
240
241def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
242  "HasVGPRIndexMode",
243  "true",
244  "Has VGPR mode register indexing"
245>;
246
247def FeatureScalarStores : SubtargetFeature<"scalar-stores",
248  "HasScalarStores",
249  "true",
250  "Has store scalar memory instructions"
251>;
252
253def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
254  "HasScalarAtomics",
255  "true",
256  "Has atomic scalar memory instructions"
257>;
258
259def FeatureSDWA : SubtargetFeature<"sdwa",
260  "HasSDWA",
261  "true",
262  "Support SDWA (Sub-DWORD Addressing) extension"
263>;
264
265def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
266  "HasSDWAOmod",
267  "true",
268  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
269>;
270
271def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
272  "HasSDWAScalar",
273  "true",
274  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
275>;
276
277def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
278  "HasSDWASdst",
279  "true",
280  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
281>;
282
283def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
284  "HasSDWAMac",
285  "true",
286  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
287>;
288
289def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
290  "HasSDWAOutModsVOPC",
291  "true",
292  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
293>;
294
295def FeatureDPP : SubtargetFeature<"dpp",
296  "HasDPP",
297  "true",
298  "Support DPP (Data Parallel Primitives) extension"
299>;
300
301def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
302  "HasIntClamp",
303  "true",
304  "Support clamp for integer destination"
305>;
306
307def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
308  "HasUnpackedD16VMem",
309  "true",
310  "Has unpacked d16 vmem instructions"
311>;
312
313//===------------------------------------------------------------===//
314// Subtarget Features (options and debugging)
315//===------------------------------------------------------------===//
316
317// Some instructions do not support denormals despite this flag. Using
318// fp32 denormals also causes instructions to run at the double
319// precision rate for the device.
320def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
321  "FP32Denormals",
322  "true",
323  "Enable single precision denormal handling"
324>;
325
326// Denormal handling for fp64 and fp16 is controlled by the same
327// config register when fp16 supported.
328// TODO: Do we need a separate f16 setting when not legal?
329def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
330  "FP64FP16Denormals",
331  "true",
332  "Enable double and half precision denormal handling",
333  [FeatureFP64]
334>;
335
336def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
337  "FP64FP16Denormals",
338  "true",
339  "Enable double and half precision denormal handling",
340  [FeatureFP64, FeatureFP64FP16Denormals]
341>;
342
343def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
344  "FP64FP16Denormals",
345  "true",
346  "Enable half precision denormal handling",
347  [FeatureFP64FP16Denormals]
348>;
349
350def FeatureDX10Clamp : SubtargetFeature<"dx10-clamp",
351  "DX10Clamp",
352  "true",
353  "clamp modifier clamps NaNs to 0.0"
354>;
355
356def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
357  "FPExceptions",
358  "true",
359  "Enable floating point exceptions"
360>;
361
362class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
363  "max-private-element-size-"#size,
364  "MaxPrivateElementSize",
365  !cast<string>(size),
366  "Maximum private access size may be "#size
367>;
368
369def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
370def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
371def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
372
373def FeatureEnableHugePrivateBuffer : SubtargetFeature<
374  "huge-private-buffer",
375  "EnableHugePrivateBuffer",
376  "true",
377  "Enable private/scratch buffer sizes greater than 128 GB"
378>;
379
380def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
381  "EnableVGPRSpilling",
382  "true",
383  "Enable spilling of VGPRs to scratch memory"
384>;
385
386def FeatureDumpCode : SubtargetFeature <"DumpCode",
387  "DumpCode",
388  "true",
389  "Dump MachineInstrs in the CodeEmitter"
390>;
391
392def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
393  "DumpCode",
394  "true",
395  "Dump MachineInstrs in the CodeEmitter"
396>;
397
398def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
399  "EnablePromoteAlloca",
400  "true",
401  "Enable promote alloca pass"
402>;
403
404// XXX - This should probably be removed once enabled by default
405def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
406  "EnableLoadStoreOpt",
407  "true",
408  "Enable SI load/store optimizer pass"
409>;
410
411// Performance debugging feature. Allow using DS instruction immediate
412// offsets even if the base pointer can't be proven to be base. On SI,
413// base pointer values that won't give the same result as a 16-bit add
414// are not safe to fold, but this will override the conservative test
415// for the base pointer.
416def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
417  "unsafe-ds-offset-folding",
418  "EnableUnsafeDSOffsetFolding",
419  "true",
420  "Force using DS instruction immediate offsets on SI"
421>;
422
423def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
424  "EnableSIScheduler",
425  "true",
426  "Enable SI Machine Scheduler"
427>;
428
429// Unless +-flat-for-global is specified, turn on FlatForGlobal for
430// all OS-es on VI and newer hardware to avoid assertion failures due
431// to missing ADDR64 variants of MUBUF instructions.
432// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
433// instructions.
434
435def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
436  "FlatForGlobal",
437  "true",
438  "Force to generate flat instruction for global"
439>;
440
441def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
442  "auto-waitcnt-before-barrier",
443  "AutoWaitcntBeforeBarrier",
444  "true",
445  "Hardware automatically inserts waitcnt before barrier"
446>;
447
448def FeatureCodeObjectV3 : SubtargetFeature <
449  "code-object-v3",
450  "CodeObjectV3",
451  "true",
452  "Generate code object version 3"
453>;
454
455// Dummy feature used to disable assembler instructions.
456def FeatureDisable : SubtargetFeature<"",
457  "FeatureDisable","true",
458  "Dummy feature to disable assembler instructions"
459>;
460
461class SubtargetFeatureGeneration <string Value,
462                                  list<SubtargetFeature> Implies> :
463        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
464                          Value#" GPU generation", Implies>;
465
466def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
467def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
468def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
469
470def FeatureR600 : SubtargetFeatureGeneration<"R600",
471  [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]
472>;
473
474def FeatureR700 : SubtargetFeatureGeneration<"R700",
475  [FeatureFetchLimit16, FeatureLocalMemorySize0]
476>;
477
478def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
479  [FeatureFetchLimit16, FeatureLocalMemorySize32768]
480>;
481
482def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
483  [FeatureFetchLimit16, FeatureWavefrontSize64,
484   FeatureLocalMemorySize32768]
485>;
486
487def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
488  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
489  FeatureWavefrontSize64, FeatureGCN,
490  FeatureLDSBankCount32, FeatureMovrel]
491>;
492
493def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
494  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
495  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
496  FeatureCIInsts, FeatureMovrel]
497>;
498
499def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
500  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
501   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
502   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
503   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
504   FeatureScalarStores, FeatureInv2PiInlineImm,
505   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
506   FeatureIntClamp
507  ]
508>;
509
510def FeatureGFX9 : SubtargetFeatureGeneration<"GFX9",
511  [FeatureFP64, FeatureLocalMemorySize65536,
512   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
513   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
514   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
515   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
516   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
517   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
518   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
519   FeatureAddNoCarryInsts, FeatureScalarAtomics
520  ]
521>;
522
523class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
524                                  list<SubtargetFeature> Implies>
525                                 : SubtargetFeature <
526  "isaver"#Major#"."#Minor#"."#Stepping,
527  "IsaVersion",
528  "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
529  "Instruction set version number",
530  Implies
531>;
532
533def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
534  [FeatureSouthernIslands,
535   FeatureFastFMAF32,
536   HalfRate64Ops,
537   FeatureLDSBankCount32]>;
538
539def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
540  [FeatureSouthernIslands,
541   FeatureLDSBankCount32]>;
542
543def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
544  [FeatureSeaIslands,
545   FeatureLDSBankCount32]>;
546
547def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
548  [FeatureSeaIslands,
549   HalfRate64Ops,
550   FeatureLDSBankCount32,
551   FeatureFastFMAF32]>;
552
553def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
554  [FeatureSeaIslands,
555   FeatureLDSBankCount16,
556   FeatureFastFMAF32]>;
557
558def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
559  [FeatureSeaIslands,
560   FeatureLDSBankCount16]>;
561
562def FeatureISAVersion7_0_4 : SubtargetFeatureISAVersion <7,0,4,
563  [FeatureSeaIslands,
564   FeatureLDSBankCount32]>;
565
566def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
567  [FeatureVolcanicIslands,
568   FeatureFastFMAF32,
569   HalfRate64Ops,
570   FeatureLDSBankCount32,
571   FeatureXNACK,
572   FeatureUnpackedD16VMem]>;
573
574def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
575  [FeatureVolcanicIslands,
576   FeatureLDSBankCount32,
577   FeatureSGPRInitBug,
578   FeatureUnpackedD16VMem]>;
579
580def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
581  [FeatureVolcanicIslands,
582   FeatureLDSBankCount32,
583   FeatureUnpackedD16VMem]>;
584
585def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
586  [FeatureVolcanicIslands,
587   FeatureLDSBankCount16,
588   FeatureXNACK]>;
589
590def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
591  [FeatureGFX9,
592   FeatureMadMixInsts,
593   FeatureLDSBankCount32
594   ]>;
595
596def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
597  [FeatureGFX9,
598   FeatureMadMixInsts,
599   FeatureLDSBankCount32,
600   FeatureXNACK
601   ]>;
602
603//===----------------------------------------------------------------------===//
604// Debugger related subtarget features.
605//===----------------------------------------------------------------------===//
606
607def FeatureDebuggerInsertNops : SubtargetFeature<
608  "amdgpu-debugger-insert-nops",
609  "DebuggerInsertNops",
610  "true",
611  "Insert one nop instruction for each high level source statement"
612>;
613
614def FeatureDebuggerReserveRegs : SubtargetFeature<
615  "amdgpu-debugger-reserve-regs",
616  "DebuggerReserveRegs",
617  "true",
618  "Reserve registers for debugger usage"
619>;
620
621def FeatureDebuggerEmitPrologue : SubtargetFeature<
622  "amdgpu-debugger-emit-prologue",
623  "DebuggerEmitPrologue",
624  "true",
625  "Emit debugger prologue"
626>;
627
628//===----------------------------------------------------------------------===//
629
630def AMDGPUInstrInfo : InstrInfo {
631  let guessInstructionProperties = 1;
632  let noNamedPositionallyEncodedOperands = 1;
633}
634
635def AMDGPUAsmParser : AsmParser {
636  // Some of the R600 registers have the same name, so this crashes.
637  // For example T0_XYZW and T0_XY both have the asm name T0.
638  let ShouldEmitMatchRegisterName = 0;
639}
640
641def AMDGPUAsmWriter : AsmWriter {
642  int PassSubtarget = 1;
643}
644
645def AMDGPUAsmVariants {
646  string Default = "Default";
647  int Default_ID = 0;
648  string VOP3 = "VOP3";
649  int VOP3_ID = 1;
650  string SDWA = "SDWA";
651  int SDWA_ID = 2;
652  string SDWA9 = "SDWA9";
653  int SDWA9_ID = 3;
654  string DPP = "DPP";
655  int DPP_ID = 4;
656  string Disable = "Disable";
657  int Disable_ID = 5;
658}
659
660def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
661  let Variant = AMDGPUAsmVariants.Default_ID;
662  let Name = AMDGPUAsmVariants.Default;
663}
664
665def VOP3AsmParserVariant : AsmParserVariant {
666  let Variant = AMDGPUAsmVariants.VOP3_ID;
667  let Name = AMDGPUAsmVariants.VOP3;
668}
669
670def SDWAAsmParserVariant : AsmParserVariant {
671  let Variant = AMDGPUAsmVariants.SDWA_ID;
672  let Name = AMDGPUAsmVariants.SDWA;
673}
674
675def SDWA9AsmParserVariant : AsmParserVariant {
676  let Variant = AMDGPUAsmVariants.SDWA9_ID;
677  let Name = AMDGPUAsmVariants.SDWA9;
678}
679
680
681def DPPAsmParserVariant : AsmParserVariant {
682  let Variant = AMDGPUAsmVariants.DPP_ID;
683  let Name = AMDGPUAsmVariants.DPP;
684}
685
686def AMDGPU : Target {
687  // Pull in Instruction Info:
688  let InstructionSet = AMDGPUInstrInfo;
689  let AssemblyParsers = [AMDGPUAsmParser];
690  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
691                                VOP3AsmParserVariant,
692                                SDWAAsmParserVariant,
693                                SDWA9AsmParserVariant,
694                                DPPAsmParserVariant];
695  let AssemblyWriters = [AMDGPUAsmWriter];
696  let AllowRegisterRenaming = 1;
697}
698
699// Dummy Instruction itineraries for pseudo instructions
700def ALU_NULL : FuncUnit;
701def NullALU : InstrItinClass;
702
703//===----------------------------------------------------------------------===//
704// Predicate helper class
705//===----------------------------------------------------------------------===//
706
707def TruePredicate : Predicate<"true">;
708
709def isSICI : Predicate<
710  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
711  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
712>, AssemblerPredicate<"!FeatureGCN3Encoding">;
713
714def isVI : Predicate <
715  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
716  AssemblerPredicate<"FeatureGCN3Encoding">;
717
718def isGFX9 : Predicate <
719  "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
720  AssemblerPredicate<"FeatureGFX9Insts">;
721
722// TODO: Either the name to be changed or we simply use IsCI!
723def isCIVI : Predicate <
724  "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
725  AssemblerPredicate<"FeatureCIInsts">;
726
727def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
728  AssemblerPredicate<"FeatureFlatAddressSpace">;
729
730def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
731  AssemblerPredicate<"FeatureFlatGlobalInsts">;
732def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
733  AssemblerPredicate<"FeatureFlatScratchInsts">;
734def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
735  AssemblerPredicate<"FeatureGFX9Insts">;
736
737def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
738  AssemblerPredicate<"FeatureUnpackedD16VMem">;
739def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
740  AssemblerPredicate<"!FeatureUnpackedD16VMem">;
741
742
743def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
744def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
745
746def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
747  AssemblerPredicate<"FeatureGFX9Insts">;
748
749def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarryInsts()">,
750  AssemblerPredicate<"FeatureAddNoCarryInsts">;
751
752def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarryInsts()">,
753  AssemblerPredicate<"!FeatureAddNoCarryInsts">;
754
755def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
756  AssemblerPredicate<"Feature16BitInsts">;
757def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
758  AssemblerPredicate<"FeatureVOP3P">;
759
760def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
761  AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
762
763def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
764  AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
765
766def HasDPP : Predicate<"Subtarget->hasDPP()">,
767  AssemblerPredicate<"FeatureDPP">;
768
769def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
770  AssemblerPredicate<"FeatureIntClamp">;
771
772def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
773  AssemblerPredicate<"FeatureMadMixInsts">;
774
775def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
776  AssemblerPredicate<"FeatureScalarAtomics">;
777
778def EnableLateCFGStructurize : Predicate<
779  "EnableLateStructurizeCFG">;
780
781// Exists to help track down where SubtargetPredicate isn't set rather
782// than letting tablegen crash with an unhelpful error.
783def InvalidPred : Predicate<"predicate not set on instruction or pattern">;
784
785class PredicateControl {
786  Predicate SubtargetPredicate = InvalidPred;
787  Predicate SIAssemblerPredicate = isSICI;
788  Predicate VIAssemblerPredicate = isVI;
789  list<Predicate> AssemblerPredicates = [];
790  Predicate AssemblerPredicate = TruePredicate;
791  list<Predicate> OtherPredicates = [];
792  list<Predicate> Predicates = !listconcat([SubtargetPredicate,
793                                            AssemblerPredicate],
794                                            AssemblerPredicates,
795                                            OtherPredicates);
796}
797
798class AMDGPUPat<dag pattern, dag result> : Pat<pattern, result>,
799  PredicateControl;
800
801
802// Include AMDGPU TD files
803include "R600Schedule.td"
804include "R600Processors.td"
805include "SISchedule.td"
806include "GCNProcessors.td"
807include "AMDGPUInstrInfo.td"
808include "AMDGPUIntrinsics.td"
809include "AMDGPURegisterInfo.td"
810include "AMDGPURegisterBanks.td"
811include "AMDGPUInstructions.td"
812include "AMDGPUCallingConv.td"
813include "AMDGPUSearchableTables.td"
814