1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===------------------------------------------------------------===//
9
10include "llvm/Target/Target.td"
11
12//===------------------------------------------------------------===//
13// Subtarget Features (device properties)
14//===------------------------------------------------------------===//
15
16def FeatureFP64 : SubtargetFeature<"fp64",
17  "FP64",
18  "true",
19  "Enable double precision operations"
20>;
21
22def FeatureFMA : SubtargetFeature<"fmaf",
23  "FMA",
24  "true",
25  "Enable single precision FMA (not as fast as mul+add, but fused)"
26>;
27
28def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
29  "FastFMAF32",
30  "true",
31  "Assuming f32 fma is at least as fast as mul + add"
32>;
33
34def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
35  "HalfRate64Ops",
36  "true",
37  "Most fp64 instructions are half rate instead of quarter"
38>;
39
40def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
41  "R600ALUInst",
42  "false",
43  "Older version of ALU instructions encoding"
44>;
45
46def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
47  "HasVertexCache",
48  "true",
49  "Specify use of dedicated vertex cache"
50>;
51
52def FeatureCaymanISA : SubtargetFeature<"caymanISA",
53  "CaymanISA",
54  "true",
55  "Use Cayman ISA"
56>;
57
58def FeatureCFALUBug : SubtargetFeature<"cfalubug",
59  "CFALUBug",
60  "true",
61  "GPU has CF_ALU bug"
62>;
63
64def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
65  "FlatAddressSpace",
66  "true",
67  "Support flat address space"
68>;
69
70def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
71  "FlatInstOffsets",
72  "true",
73  "Flat instructions have immediate offset addressing mode"
74>;
75
76def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
77  "FlatGlobalInsts",
78  "true",
79  "Have global_* flat memory instructions"
80>;
81
82def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
83  "FlatScratchInsts",
84  "true",
85  "Have scratch_* flat memory instructions"
86>;
87
88def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
89  "AddNoCarryInsts",
90  "true",
91  "Have VALU add/sub instructions without carry out"
92>;
93
94def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
95  "UnalignedBufferAccess",
96  "true",
97  "Support unaligned global loads and stores"
98>;
99
100def FeatureTrapHandler: SubtargetFeature<"trap-handler",
101  "TrapHandler",
102  "true",
103  "Trap handler support"
104>;
105
106def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
107  "UnalignedScratchAccess",
108  "true",
109  "Support unaligned scratch loads and stores"
110>;
111
112def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
113  "HasApertureRegs",
114  "true",
115  "Has Memory Aperture Base and Size Registers"
116>;
117
118def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
119  "HasMadMixInsts",
120  "true",
121  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
122>;
123
124// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
125// XNACK. The current default kernel driver setting is:
126// - graphics ring: XNACK disabled
127// - compute ring: XNACK enabled
128//
129// If XNACK is enabled, the VMEM latency can be worse.
130// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
131def FeatureXNACK : SubtargetFeature<"xnack",
132  "EnableXNACK",
133  "true",
134  "Enable XNACK support"
135>;
136
137def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
138  "SGPRInitBug",
139  "true",
140  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
141>;
142
143class SubtargetFeatureFetchLimit <string Value> :
144                          SubtargetFeature <"fetch"#Value,
145  "TexVTXClauseSize",
146  Value,
147  "Limit the maximum number of fetches in a clause to "#Value
148>;
149
150def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
151def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
152
153class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
154  "wavefrontsize"#Value,
155  "WavefrontSize",
156  !cast<string>(Value),
157  "The number of threads per wavefront"
158>;
159
160def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
161def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
162def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
163
164class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
165  "ldsbankcount"#Value,
166  "LDSBankCount",
167  !cast<string>(Value),
168  "The number of LDS banks per compute unit."
169>;
170
171def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
172def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
173
174class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
175  "localmemorysize"#Value,
176  "LocalMemorySize",
177  !cast<string>(Value),
178  "The size of local memory in bytes"
179>;
180
181def FeatureGCN : SubtargetFeature<"gcn",
182  "IsGCN",
183  "true",
184  "GCN or newer GPU"
185>;
186
187def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
188  "GCN3Encoding",
189  "true",
190  "Encoding format for VI"
191>;
192
193def FeatureCIInsts : SubtargetFeature<"ci-insts",
194  "CIInsts",
195  "true",
196  "Additional instructions for CI+"
197>;
198
199def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
200  "GFX9Insts",
201  "true",
202  "Additional instructions for GFX9+"
203>;
204
205def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
206  "HasSMemRealTime",
207  "true",
208  "Has s_memrealtime instruction"
209>;
210
211def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
212  "HasInv2PiInlineImm",
213  "true",
214  "Has 1 / (2 * pi) as inline immediate"
215>;
216
217def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
218  "Has16BitInsts",
219  "true",
220  "Has i16/f16 instructions"
221>;
222
223def FeatureVOP3P : SubtargetFeature<"vop3p",
224  "HasVOP3PInsts",
225  "true",
226  "Has VOP3P packed instructions"
227>;
228
229def FeatureMovrel : SubtargetFeature<"movrel",
230  "HasMovrel",
231  "true",
232  "Has v_movrel*_b32 instructions"
233>;
234
235def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
236  "HasVGPRIndexMode",
237  "true",
238  "Has VGPR mode register indexing"
239>;
240
241def FeatureScalarStores : SubtargetFeature<"scalar-stores",
242  "HasScalarStores",
243  "true",
244  "Has store scalar memory instructions"
245>;
246
247def FeatureSDWA : SubtargetFeature<"sdwa",
248  "HasSDWA",
249  "true",
250  "Support SDWA (Sub-DWORD Addressing) extension"
251>;
252
253def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
254  "HasSDWAOmod",
255  "true",
256  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
257>;
258
259def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
260  "HasSDWAScalar",
261  "true",
262  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
263>;
264
265def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
266  "HasSDWASdst",
267  "true",
268  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
269>;
270
271def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
272  "HasSDWAMac",
273  "true",
274  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
275>;
276
277def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
278  "HasSDWAOutModsVOPC",
279  "true",
280  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
281>;
282
283def FeatureDPP : SubtargetFeature<"dpp",
284  "HasDPP",
285  "true",
286  "Support DPP (Data Parallel Primitives) extension"
287>;
288
289def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
290  "HasIntClamp",
291  "true",
292  "Support clamp for integer destination"
293>;
294
295def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
296  "HasUnpackedD16VMem",
297  "true",
298  "Has unpacked d16 vmem instructions"
299>;
300
301//===------------------------------------------------------------===//
302// Subtarget Features (options and debugging)
303//===------------------------------------------------------------===//
304
305// Some instructions do not support denormals despite this flag. Using
306// fp32 denormals also causes instructions to run at the double
307// precision rate for the device.
308def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
309  "FP32Denormals",
310  "true",
311  "Enable single precision denormal handling"
312>;
313
314// Denormal handling for fp64 and fp16 is controlled by the same
315// config register when fp16 supported.
316// TODO: Do we need a separate f16 setting when not legal?
317def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
318  "FP64FP16Denormals",
319  "true",
320  "Enable double and half precision denormal handling",
321  [FeatureFP64]
322>;
323
324def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
325  "FP64FP16Denormals",
326  "true",
327  "Enable double and half precision denormal handling",
328  [FeatureFP64, FeatureFP64FP16Denormals]
329>;
330
331def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
332  "FP64FP16Denormals",
333  "true",
334  "Enable half precision denormal handling",
335  [FeatureFP64FP16Denormals]
336>;
337
338def FeatureDX10Clamp : SubtargetFeature<"dx10-clamp",
339  "DX10Clamp",
340  "true",
341  "clamp modifier clamps NaNs to 0.0"
342>;
343
344def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
345  "FPExceptions",
346  "true",
347  "Enable floating point exceptions"
348>;
349
350class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
351  "max-private-element-size-"#size,
352  "MaxPrivateElementSize",
353  !cast<string>(size),
354  "Maximum private access size may be "#size
355>;
356
357def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
358def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
359def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
360
361def FeatureEnableHugePrivateBuffer : SubtargetFeature<
362  "huge-private-buffer",
363  "EnableHugePrivateBuffer",
364  "true",
365  "Enable private/scratch buffer sizes greater than 128 GB"
366>;
367
368def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
369  "EnableVGPRSpilling",
370  "true",
371  "Enable spilling of VGPRs to scratch memory"
372>;
373
374def FeatureDumpCode : SubtargetFeature <"DumpCode",
375  "DumpCode",
376  "true",
377  "Dump MachineInstrs in the CodeEmitter"
378>;
379
380def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
381  "DumpCode",
382  "true",
383  "Dump MachineInstrs in the CodeEmitter"
384>;
385
386def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
387  "EnablePromoteAlloca",
388  "true",
389  "Enable promote alloca pass"
390>;
391
392// XXX - This should probably be removed once enabled by default
393def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
394  "EnableLoadStoreOpt",
395  "true",
396  "Enable SI load/store optimizer pass"
397>;
398
399// Performance debugging feature. Allow using DS instruction immediate
400// offsets even if the base pointer can't be proven to be base. On SI,
401// base pointer values that won't give the same result as a 16-bit add
402// are not safe to fold, but this will override the conservative test
403// for the base pointer.
404def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
405  "unsafe-ds-offset-folding",
406  "EnableUnsafeDSOffsetFolding",
407  "true",
408  "Force using DS instruction immediate offsets on SI"
409>;
410
411def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
412  "EnableSIScheduler",
413  "true",
414  "Enable SI Machine Scheduler"
415>;
416
417// Unless +-flat-for-global is specified, turn on FlatForGlobal for
418// all OS-es on VI and newer hardware to avoid assertion failures due
419// to missing ADDR64 variants of MUBUF instructions.
420// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
421// instructions.
422
423def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
424  "FlatForGlobal",
425  "true",
426  "Force to generate flat instruction for global"
427>;
428
429def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
430  "auto-waitcnt-before-barrier",
431  "AutoWaitcntBeforeBarrier",
432  "true",
433  "Hardware automatically inserts waitcnt before barrier"
434>;
435
436def FeatureCodeObjectV3 : SubtargetFeature <
437  "code-object-v3",
438  "CodeObjectV3",
439  "true",
440  "Generate code object version 3"
441>;
442
443// Dummy feature used to disable assembler instructions.
444def FeatureDisable : SubtargetFeature<"",
445  "FeatureDisable","true",
446  "Dummy feature to disable assembler instructions"
447>;
448
449class SubtargetFeatureGeneration <string Value,
450                                  list<SubtargetFeature> Implies> :
451        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
452                          Value#" GPU generation", Implies>;
453
454def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
455def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
456def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
457
458def FeatureR600 : SubtargetFeatureGeneration<"R600",
459  [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]
460>;
461
462def FeatureR700 : SubtargetFeatureGeneration<"R700",
463  [FeatureFetchLimit16, FeatureLocalMemorySize0]
464>;
465
466def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
467  [FeatureFetchLimit16, FeatureLocalMemorySize32768]
468>;
469
470def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
471  [FeatureFetchLimit16, FeatureWavefrontSize64,
472   FeatureLocalMemorySize32768]
473>;
474
475def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
476  [FeatureFP64, FeatureLocalMemorySize32768,
477  FeatureWavefrontSize64, FeatureGCN,
478  FeatureLDSBankCount32, FeatureMovrel]
479>;
480
481def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
482  [FeatureFP64, FeatureLocalMemorySize65536,
483  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
484  FeatureCIInsts, FeatureMovrel]
485>;
486
487def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
488  [FeatureFP64, FeatureLocalMemorySize65536,
489   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
490   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
491   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
492   FeatureScalarStores, FeatureInv2PiInlineImm,
493   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
494   FeatureIntClamp
495  ]
496>;
497
498def FeatureGFX9 : SubtargetFeatureGeneration<"GFX9",
499  [FeatureFP64, FeatureLocalMemorySize65536,
500   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
501   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
502   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
503   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
504   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
505   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
506   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
507   FeatureAddNoCarryInsts
508  ]
509>;
510
511class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
512                                  list<SubtargetFeature> Implies>
513                                 : SubtargetFeature <
514  "isaver"#Major#"."#Minor#"."#Stepping,
515  "IsaVersion",
516  "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
517  "Instruction set version number",
518  Implies
519>;
520
521def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
522  [FeatureSouthernIslands,
523   FeatureFastFMAF32,
524   HalfRate64Ops,
525   FeatureLDSBankCount32]>;
526
527def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
528  [FeatureSouthernIslands,
529   FeatureLDSBankCount32]>;
530
531def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
532  [FeatureSeaIslands,
533   FeatureLDSBankCount32]>;
534
535def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
536  [FeatureSeaIslands,
537   HalfRate64Ops,
538   FeatureLDSBankCount32,
539   FeatureFastFMAF32]>;
540
541def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
542  [FeatureSeaIslands,
543   FeatureLDSBankCount16]>;
544
545def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
546  [FeatureSeaIslands,
547   FeatureLDSBankCount16]>;
548
549def FeatureISAVersion7_0_4 : SubtargetFeatureISAVersion <7,0,4,
550  [FeatureSeaIslands,
551   FeatureLDSBankCount32]>;
552
553def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0,
554  [FeatureVolcanicIslands,
555   FeatureLDSBankCount32,
556   FeatureSGPRInitBug,
557   FeatureUnpackedD16VMem]>;
558
559def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
560  [FeatureVolcanicIslands,
561   FeatureFastFMAF32,
562   HalfRate64Ops,
563   FeatureLDSBankCount32,
564   FeatureXNACK,
565   FeatureUnpackedD16VMem]>;
566
567def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
568  [FeatureVolcanicIslands,
569   FeatureLDSBankCount32,
570   FeatureSGPRInitBug,
571   FeatureUnpackedD16VMem]>;
572
573def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
574  [FeatureVolcanicIslands,
575   FeatureLDSBankCount32,
576   FeatureUnpackedD16VMem]>;
577
578def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
579  [FeatureVolcanicIslands,
580   FeatureLDSBankCount16,
581   FeatureXNACK]>;
582
583def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
584  [FeatureGFX9,
585   FeatureMadMixInsts,
586   FeatureLDSBankCount32
587   ]>;
588
589def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
590  [FeatureGFX9,
591   FeatureMadMixInsts,
592   FeatureLDSBankCount32
593   ]>;
594
595//===----------------------------------------------------------------------===//
596// Debugger related subtarget features.
597//===----------------------------------------------------------------------===//
598
599def FeatureDebuggerInsertNops : SubtargetFeature<
600  "amdgpu-debugger-insert-nops",
601  "DebuggerInsertNops",
602  "true",
603  "Insert one nop instruction for each high level source statement"
604>;
605
606def FeatureDebuggerReserveRegs : SubtargetFeature<
607  "amdgpu-debugger-reserve-regs",
608  "DebuggerReserveRegs",
609  "true",
610  "Reserve registers for debugger usage"
611>;
612
613def FeatureDebuggerEmitPrologue : SubtargetFeature<
614  "amdgpu-debugger-emit-prologue",
615  "DebuggerEmitPrologue",
616  "true",
617  "Emit debugger prologue"
618>;
619
620//===----------------------------------------------------------------------===//
621
622def AMDGPUInstrInfo : InstrInfo {
623  let guessInstructionProperties = 1;
624  let noNamedPositionallyEncodedOperands = 1;
625}
626
627def AMDGPUAsmParser : AsmParser {
628  // Some of the R600 registers have the same name, so this crashes.
629  // For example T0_XYZW and T0_XY both have the asm name T0.
630  let ShouldEmitMatchRegisterName = 0;
631}
632
633def AMDGPUAsmWriter : AsmWriter {
634  int PassSubtarget = 1;
635}
636
637def AMDGPUAsmVariants {
638  string Default = "Default";
639  int Default_ID = 0;
640  string VOP3 = "VOP3";
641  int VOP3_ID = 1;
642  string SDWA = "SDWA";
643  int SDWA_ID = 2;
644  string SDWA9 = "SDWA9";
645  int SDWA9_ID = 3;
646  string DPP = "DPP";
647  int DPP_ID = 4;
648  string Disable = "Disable";
649  int Disable_ID = 5;
650}
651
652def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
653  let Variant = AMDGPUAsmVariants.Default_ID;
654  let Name = AMDGPUAsmVariants.Default;
655}
656
657def VOP3AsmParserVariant : AsmParserVariant {
658  let Variant = AMDGPUAsmVariants.VOP3_ID;
659  let Name = AMDGPUAsmVariants.VOP3;
660}
661
662def SDWAAsmParserVariant : AsmParserVariant {
663  let Variant = AMDGPUAsmVariants.SDWA_ID;
664  let Name = AMDGPUAsmVariants.SDWA;
665}
666
667def SDWA9AsmParserVariant : AsmParserVariant {
668  let Variant = AMDGPUAsmVariants.SDWA9_ID;
669  let Name = AMDGPUAsmVariants.SDWA9;
670}
671
672
673def DPPAsmParserVariant : AsmParserVariant {
674  let Variant = AMDGPUAsmVariants.DPP_ID;
675  let Name = AMDGPUAsmVariants.DPP;
676}
677
678def AMDGPU : Target {
679  // Pull in Instruction Info:
680  let InstructionSet = AMDGPUInstrInfo;
681  let AssemblyParsers = [AMDGPUAsmParser];
682  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
683                                VOP3AsmParserVariant,
684                                SDWAAsmParserVariant,
685                                SDWA9AsmParserVariant,
686                                DPPAsmParserVariant];
687  let AssemblyWriters = [AMDGPUAsmWriter];
688}
689
690// Dummy Instruction itineraries for pseudo instructions
691def ALU_NULL : FuncUnit;
692def NullALU : InstrItinClass;
693
694//===----------------------------------------------------------------------===//
695// Predicate helper class
696//===----------------------------------------------------------------------===//
697
698def TruePredicate : Predicate<"true">;
699
700def isSICI : Predicate<
701  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
702  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
703>, AssemblerPredicate<"!FeatureGCN3Encoding">;
704
705def isVI : Predicate <
706  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
707  AssemblerPredicate<"FeatureGCN3Encoding">;
708
709def isGFX9 : Predicate <
710  "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
711  AssemblerPredicate<"FeatureGFX9Insts">;
712
713// TODO: Either the name to be changed or we simply use IsCI!
714def isCIVI : Predicate <
715  "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
716  AssemblerPredicate<"FeatureCIInsts">;
717
718def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
719  AssemblerPredicate<"FeatureFlatAddressSpace">;
720
721def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
722  AssemblerPredicate<"FeatureFlatGlobalInsts">;
723def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
724  AssemblerPredicate<"FeatureFlatScratchInsts">;
725def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
726  AssemblerPredicate<"FeatureGFX9Insts">;
727
728def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
729  AssemblerPredicate<"FeatureUnpackedD16VMem">;
730def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
731  AssemblerPredicate<"!FeatureUnpackedD16VMem">;
732
733
734def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
735def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
736
737def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
738  AssemblerPredicate<"FeatureGFX9Insts">;
739
740def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarryInsts()">,
741  AssemblerPredicate<"FeatureAddNoCarryInsts">;
742
743def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarryInsts()">,
744  AssemblerPredicate<"!FeatureAddNoCarryInsts">;
745
746def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
747  AssemblerPredicate<"Feature16BitInsts">;
748def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
749  AssemblerPredicate<"FeatureVOP3P">;
750
751def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
752  AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
753
754def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
755  AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
756
757def HasDPP : Predicate<"Subtarget->hasDPP()">,
758  AssemblerPredicate<"FeatureDPP">;
759
760def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
761  AssemblerPredicate<"FeatureIntClamp">;
762
763def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
764  AssemblerPredicate<"FeatureMadMixInsts">;
765
766def EnableLateCFGStructurize : Predicate<
767  "EnableLateStructurizeCFG">;
768
769// Exists to help track down where SubtargetPredicate isn't set rather
770// than letting tablegen crash with an unhelpful error.
771def InvalidPred : Predicate<"predicate not set on instruction or pattern">;
772
773class PredicateControl {
774  Predicate SubtargetPredicate = InvalidPred;
775  Predicate SIAssemblerPredicate = isSICI;
776  Predicate VIAssemblerPredicate = isVI;
777  list<Predicate> AssemblerPredicates = [];
778  Predicate AssemblerPredicate = TruePredicate;
779  list<Predicate> OtherPredicates = [];
780  list<Predicate> Predicates = !listconcat([SubtargetPredicate,
781                                            AssemblerPredicate],
782                                            AssemblerPredicates,
783                                            OtherPredicates);
784}
785
786class AMDGPUPat<dag pattern, dag result> : Pat<pattern, result>,
787  PredicateControl;
788
789
790// Include AMDGPU TD files
791include "R600Schedule.td"
792include "R600Processors.td"
793include "SISchedule.td"
794include "GCNProcessors.td"
795include "AMDGPUInstrInfo.td"
796include "AMDGPUIntrinsics.td"
797include "AMDGPURegisterInfo.td"
798include "AMDGPURegisterBanks.td"
799include "AMDGPUInstructions.td"
800include "AMDGPUCallingConv.td"
801