1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===------------------------------------------------------------===//
9
10include "llvm/TableGen/SearchableTable.td"
11include "llvm/Target/Target.td"
12
13//===------------------------------------------------------------===//
14// Subtarget Features (device properties)
15//===------------------------------------------------------------===//
16
17def FeatureFP64 : SubtargetFeature<"fp64",
18  "FP64",
19  "true",
20  "Enable double precision operations"
21>;
22
23def FeatureFMA : SubtargetFeature<"fmaf",
24  "FMA",
25  "true",
26  "Enable single precision FMA (not as fast as mul+add, but fused)"
27>;
28
29def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
30  "FastFMAF32",
31  "true",
32  "Assuming f32 fma is at least as fast as mul + add"
33>;
34
35def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
36  "MIMG_R128",
37  "true",
38  "Support 128-bit texture resources"
39>;
40
41def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
42  "HalfRate64Ops",
43  "true",
44  "Most fp64 instructions are half rate instead of quarter"
45>;
46
47def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
48  "R600ALUInst",
49  "false",
50  "Older version of ALU instructions encoding"
51>;
52
53def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
54  "HasVertexCache",
55  "true",
56  "Specify use of dedicated vertex cache"
57>;
58
59def FeatureCaymanISA : SubtargetFeature<"caymanISA",
60  "CaymanISA",
61  "true",
62  "Use Cayman ISA"
63>;
64
65def FeatureCFALUBug : SubtargetFeature<"cfalubug",
66  "CFALUBug",
67  "true",
68  "GPU has CF_ALU bug"
69>;
70
71def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
72  "FlatAddressSpace",
73  "true",
74  "Support flat address space"
75>;
76
77def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
78  "FlatInstOffsets",
79  "true",
80  "Flat instructions have immediate offset addressing mode"
81>;
82
83def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
84  "FlatGlobalInsts",
85  "true",
86  "Have global_* flat memory instructions"
87>;
88
89def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
90  "FlatScratchInsts",
91  "true",
92  "Have scratch_* flat memory instructions"
93>;
94
95def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
96  "AddNoCarryInsts",
97  "true",
98  "Have VALU add/sub instructions without carry out"
99>;
100
101def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
102  "UnalignedBufferAccess",
103  "true",
104  "Support unaligned global loads and stores"
105>;
106
107def FeatureTrapHandler: SubtargetFeature<"trap-handler",
108  "TrapHandler",
109  "true",
110  "Trap handler support"
111>;
112
113def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
114  "UnalignedScratchAccess",
115  "true",
116  "Support unaligned scratch loads and stores"
117>;
118
119def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
120  "HasApertureRegs",
121  "true",
122  "Has Memory Aperture Base and Size Registers"
123>;
124
125def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
126  "HasMadMixInsts",
127  "true",
128  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
129>;
130
131def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
132  "HasFmaMixInsts",
133  "true",
134  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
135>;
136
137// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
138// XNACK. The current default kernel driver setting is:
139// - graphics ring: XNACK disabled
140// - compute ring: XNACK enabled
141//
142// If XNACK is enabled, the VMEM latency can be worse.
143// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
144def FeatureXNACK : SubtargetFeature<"xnack",
145  "EnableXNACK",
146  "true",
147  "Enable XNACK support"
148>;
149
150def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
151  "SGPRInitBug",
152  "true",
153  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
154>;
155
156class SubtargetFeatureFetchLimit <string Value> :
157                          SubtargetFeature <"fetch"#Value,
158  "TexVTXClauseSize",
159  Value,
160  "Limit the maximum number of fetches in a clause to "#Value
161>;
162
163def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
164def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
165
166class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
167  "wavefrontsize"#Value,
168  "WavefrontSize",
169  !cast<string>(Value),
170  "The number of threads per wavefront"
171>;
172
173def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
174def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
175def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
176
177class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
178  "ldsbankcount"#Value,
179  "LDSBankCount",
180  !cast<string>(Value),
181  "The number of LDS banks per compute unit."
182>;
183
184def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
185def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
186
187class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
188  "localmemorysize"#Value,
189  "LocalMemorySize",
190  !cast<string>(Value),
191  "The size of local memory in bytes"
192>;
193
194def FeatureGCN : SubtargetFeature<"gcn",
195  "IsGCN",
196  "true",
197  "GCN or newer GPU"
198>;
199
200def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
201  "GCN3Encoding",
202  "true",
203  "Encoding format for VI"
204>;
205
206def FeatureCIInsts : SubtargetFeature<"ci-insts",
207  "CIInsts",
208  "true",
209  "Additional instructions for CI+"
210>;
211
212def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
213  "GFX9Insts",
214  "true",
215  "Additional instructions for GFX9+"
216>;
217
218def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
219  "HasSMemRealTime",
220  "true",
221  "Has s_memrealtime instruction"
222>;
223
224def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
225  "HasInv2PiInlineImm",
226  "true",
227  "Has 1 / (2 * pi) as inline immediate"
228>;
229
230def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
231  "Has16BitInsts",
232  "true",
233  "Has i16/f16 instructions"
234>;
235
236def FeatureVOP3P : SubtargetFeature<"vop3p",
237  "HasVOP3PInsts",
238  "true",
239  "Has VOP3P packed instructions"
240>;
241
242def FeatureMovrel : SubtargetFeature<"movrel",
243  "HasMovrel",
244  "true",
245  "Has v_movrel*_b32 instructions"
246>;
247
248def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
249  "HasVGPRIndexMode",
250  "true",
251  "Has VGPR mode register indexing"
252>;
253
254def FeatureScalarStores : SubtargetFeature<"scalar-stores",
255  "HasScalarStores",
256  "true",
257  "Has store scalar memory instructions"
258>;
259
260def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
261  "HasScalarAtomics",
262  "true",
263  "Has atomic scalar memory instructions"
264>;
265
266def FeatureSDWA : SubtargetFeature<"sdwa",
267  "HasSDWA",
268  "true",
269  "Support SDWA (Sub-DWORD Addressing) extension"
270>;
271
272def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
273  "HasSDWAOmod",
274  "true",
275  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
276>;
277
278def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
279  "HasSDWAScalar",
280  "true",
281  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
282>;
283
284def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
285  "HasSDWASdst",
286  "true",
287  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
288>;
289
290def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
291  "HasSDWAMac",
292  "true",
293  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
294>;
295
296def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
297  "HasSDWAOutModsVOPC",
298  "true",
299  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
300>;
301
302def FeatureDPP : SubtargetFeature<"dpp",
303  "HasDPP",
304  "true",
305  "Support DPP (Data Parallel Primitives) extension"
306>;
307
308def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
309  "HasIntClamp",
310  "true",
311  "Support clamp for integer destination"
312>;
313
314def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
315  "HasUnpackedD16VMem",
316  "true",
317  "Has unpacked d16 vmem instructions"
318>;
319
320def FeatureDLInsts : SubtargetFeature<"dl-insts",
321  "HasDLInsts",
322  "true",
323  "Has deep learning instructions"
324>;
325
326def FeatureD16PreservesUnusedBits : SubtargetFeature<
327  "d16-preserves-unused-bits",
328  "D16PreservesUnusedBits",
329  "true",
330  "If present, then instructions defined by HasD16LoadStore predicate preserve "
331  "unused bits. Otherwise instructions defined by HasD16LoadStore predicate "
332  "zero unused bits."
333>;
334
335//===------------------------------------------------------------===//
336// Subtarget Features (options and debugging)
337//===------------------------------------------------------------===//
338
339// Some instructions do not support denormals despite this flag. Using
340// fp32 denormals also causes instructions to run at the double
341// precision rate for the device.
342def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
343  "FP32Denormals",
344  "true",
345  "Enable single precision denormal handling"
346>;
347
348// Denormal handling for fp64 and fp16 is controlled by the same
349// config register when fp16 supported.
350// TODO: Do we need a separate f16 setting when not legal?
351def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
352  "FP64FP16Denormals",
353  "true",
354  "Enable double and half precision denormal handling",
355  [FeatureFP64]
356>;
357
358def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
359  "FP64FP16Denormals",
360  "true",
361  "Enable double and half precision denormal handling",
362  [FeatureFP64, FeatureFP64FP16Denormals]
363>;
364
365def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
366  "FP64FP16Denormals",
367  "true",
368  "Enable half precision denormal handling",
369  [FeatureFP64FP16Denormals]
370>;
371
372def FeatureDX10Clamp : SubtargetFeature<"dx10-clamp",
373  "DX10Clamp",
374  "true",
375  "clamp modifier clamps NaNs to 0.0"
376>;
377
378def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
379  "FPExceptions",
380  "true",
381  "Enable floating point exceptions"
382>;
383
384class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
385  "max-private-element-size-"#size,
386  "MaxPrivateElementSize",
387  !cast<string>(size),
388  "Maximum private access size may be "#size
389>;
390
391def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
392def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
393def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
394
395def FeatureEnableHugePrivateBuffer : SubtargetFeature<
396  "huge-private-buffer",
397  "EnableHugePrivateBuffer",
398  "true",
399  "Enable private/scratch buffer sizes greater than 128 GB"
400>;
401
402def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
403  "EnableVGPRSpilling",
404  "true",
405  "Enable spilling of VGPRs to scratch memory"
406>;
407
408def FeatureDumpCode : SubtargetFeature <"DumpCode",
409  "DumpCode",
410  "true",
411  "Dump MachineInstrs in the CodeEmitter"
412>;
413
414def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
415  "DumpCode",
416  "true",
417  "Dump MachineInstrs in the CodeEmitter"
418>;
419
420def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
421  "EnablePromoteAlloca",
422  "true",
423  "Enable promote alloca pass"
424>;
425
426// XXX - This should probably be removed once enabled by default
427def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
428  "EnableLoadStoreOpt",
429  "true",
430  "Enable SI load/store optimizer pass"
431>;
432
433// Performance debugging feature. Allow using DS instruction immediate
434// offsets even if the base pointer can't be proven to be base. On SI,
435// base pointer values that won't give the same result as a 16-bit add
436// are not safe to fold, but this will override the conservative test
437// for the base pointer.
438def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
439  "unsafe-ds-offset-folding",
440  "EnableUnsafeDSOffsetFolding",
441  "true",
442  "Force using DS instruction immediate offsets on SI"
443>;
444
445def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
446  "EnableSIScheduler",
447  "true",
448  "Enable SI Machine Scheduler"
449>;
450
451def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
452  "EnableDS128",
453  "true",
454  "Use ds_{read|write}_b128"
455>;
456
457// Unless +-flat-for-global is specified, turn on FlatForGlobal for
458// all OS-es on VI and newer hardware to avoid assertion failures due
459// to missing ADDR64 variants of MUBUF instructions.
460// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
461// instructions.
462
463def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
464  "FlatForGlobal",
465  "true",
466  "Force to generate flat instruction for global"
467>;
468
469def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
470  "auto-waitcnt-before-barrier",
471  "AutoWaitcntBeforeBarrier",
472  "true",
473  "Hardware automatically inserts waitcnt before barrier"
474>;
475
476def FeatureCodeObjectV3 : SubtargetFeature <
477  "code-object-v3",
478  "CodeObjectV3",
479  "true",
480  "Generate code object version 3"
481>;
482
483// Dummy feature used to disable assembler instructions.
484def FeatureDisable : SubtargetFeature<"",
485  "FeatureDisable","true",
486  "Dummy feature to disable assembler instructions"
487>;
488
489class SubtargetFeatureGeneration <string Value,
490                                  list<SubtargetFeature> Implies> :
491        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
492                          Value#" GPU generation", Implies>;
493
494def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
495def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
496def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
497
498def FeatureR600 : SubtargetFeatureGeneration<"R600",
499  [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]
500>;
501
502def FeatureR700 : SubtargetFeatureGeneration<"R700",
503  [FeatureFetchLimit16, FeatureLocalMemorySize0]
504>;
505
506def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
507  [FeatureFetchLimit16, FeatureLocalMemorySize32768]
508>;
509
510def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
511  [FeatureFetchLimit16, FeatureWavefrontSize64,
512   FeatureLocalMemorySize32768]
513>;
514
515def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
516  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
517  FeatureWavefrontSize64, FeatureGCN,
518  FeatureLDSBankCount32, FeatureMovrel]
519>;
520
521def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
522  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
523  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
524  FeatureCIInsts, FeatureMovrel]
525>;
526
527def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
528  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
529   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
530   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
531   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
532   FeatureScalarStores, FeatureInv2PiInlineImm,
533   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
534   FeatureIntClamp
535  ]
536>;
537
538def FeatureGFX9 : SubtargetFeatureGeneration<"GFX9",
539  [FeatureFP64, FeatureLocalMemorySize65536,
540   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
541   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
542   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
543   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
544   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
545   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
546   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
547   FeatureAddNoCarryInsts, FeatureScalarAtomics
548  ]
549>;
550
551class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
552                                  list<SubtargetFeature> Implies>
553                                 : SubtargetFeature <
554  "isaver"#Major#"."#Minor#"."#Stepping,
555  "IsaVersion",
556  "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
557  "Instruction set version number",
558  Implies
559>;
560
561def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
562  [FeatureSouthernIslands,
563   FeatureFastFMAF32,
564   HalfRate64Ops,
565   FeatureLDSBankCount32]>;
566
567def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
568  [FeatureSouthernIslands,
569   FeatureLDSBankCount32]>;
570
571def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
572  [FeatureSeaIslands,
573   FeatureLDSBankCount32]>;
574
575def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
576  [FeatureSeaIslands,
577   HalfRate64Ops,
578   FeatureLDSBankCount32,
579   FeatureFastFMAF32]>;
580
581def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
582  [FeatureSeaIslands,
583   FeatureLDSBankCount16,
584   FeatureFastFMAF32]>;
585
586def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
587  [FeatureSeaIslands,
588   FeatureLDSBankCount16]>;
589
590def FeatureISAVersion7_0_4 : SubtargetFeatureISAVersion <7,0,4,
591  [FeatureSeaIslands,
592   FeatureLDSBankCount32]>;
593
594def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
595  [FeatureVolcanicIslands,
596   FeatureFastFMAF32,
597   HalfRate64Ops,
598   FeatureLDSBankCount32,
599   FeatureXNACK,
600   FeatureUnpackedD16VMem]>;
601
602def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
603  [FeatureVolcanicIslands,
604   FeatureLDSBankCount32,
605   FeatureSGPRInitBug,
606   FeatureUnpackedD16VMem]>;
607
608def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
609  [FeatureVolcanicIslands,
610   FeatureLDSBankCount32,
611   FeatureUnpackedD16VMem]>;
612
613def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
614  [FeatureVolcanicIslands,
615   FeatureLDSBankCount16,
616   FeatureXNACK]>;
617
618def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
619  [FeatureGFX9,
620   FeatureMadMixInsts,
621   FeatureLDSBankCount32,
622   FeatureD16PreservesUnusedBits]>;
623
624def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
625  [FeatureGFX9,
626   FeatureMadMixInsts,
627   FeatureLDSBankCount32,
628   FeatureXNACK,
629   FeatureD16PreservesUnusedBits]>;
630
631def FeatureISAVersion9_0_4 : SubtargetFeatureISAVersion <9,0,4,
632  [FeatureGFX9,
633   FeatureLDSBankCount32,
634   FeatureFmaMixInsts,
635   FeatureD16PreservesUnusedBits]>;
636
637def FeatureISAVersion9_0_6 : SubtargetFeatureISAVersion <9,0,6,
638  [FeatureGFX9,
639   HalfRate64Ops,
640   FeatureFmaMixInsts,
641   FeatureLDSBankCount32,
642   FeatureDLInsts]>;
643
644//===----------------------------------------------------------------------===//
645// Debugger related subtarget features.
646//===----------------------------------------------------------------------===//
647
648def FeatureDebuggerInsertNops : SubtargetFeature<
649  "amdgpu-debugger-insert-nops",
650  "DebuggerInsertNops",
651  "true",
652  "Insert one nop instruction for each high level source statement"
653>;
654
655def FeatureDebuggerEmitPrologue : SubtargetFeature<
656  "amdgpu-debugger-emit-prologue",
657  "DebuggerEmitPrologue",
658  "true",
659  "Emit debugger prologue"
660>;
661
662//===----------------------------------------------------------------------===//
663
664def AMDGPUInstrInfo : InstrInfo {
665  let guessInstructionProperties = 1;
666  let noNamedPositionallyEncodedOperands = 1;
667}
668
669def AMDGPUAsmParser : AsmParser {
670  // Some of the R600 registers have the same name, so this crashes.
671  // For example T0_XYZW and T0_XY both have the asm name T0.
672  let ShouldEmitMatchRegisterName = 0;
673}
674
675def AMDGPUAsmWriter : AsmWriter {
676  int PassSubtarget = 1;
677}
678
679def AMDGPUAsmVariants {
680  string Default = "Default";
681  int Default_ID = 0;
682  string VOP3 = "VOP3";
683  int VOP3_ID = 1;
684  string SDWA = "SDWA";
685  int SDWA_ID = 2;
686  string SDWA9 = "SDWA9";
687  int SDWA9_ID = 3;
688  string DPP = "DPP";
689  int DPP_ID = 4;
690  string Disable = "Disable";
691  int Disable_ID = 5;
692}
693
694def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
695  let Variant = AMDGPUAsmVariants.Default_ID;
696  let Name = AMDGPUAsmVariants.Default;
697}
698
699def VOP3AsmParserVariant : AsmParserVariant {
700  let Variant = AMDGPUAsmVariants.VOP3_ID;
701  let Name = AMDGPUAsmVariants.VOP3;
702}
703
704def SDWAAsmParserVariant : AsmParserVariant {
705  let Variant = AMDGPUAsmVariants.SDWA_ID;
706  let Name = AMDGPUAsmVariants.SDWA;
707}
708
709def SDWA9AsmParserVariant : AsmParserVariant {
710  let Variant = AMDGPUAsmVariants.SDWA9_ID;
711  let Name = AMDGPUAsmVariants.SDWA9;
712}
713
714
715def DPPAsmParserVariant : AsmParserVariant {
716  let Variant = AMDGPUAsmVariants.DPP_ID;
717  let Name = AMDGPUAsmVariants.DPP;
718}
719
720def AMDGPU : Target {
721  // Pull in Instruction Info:
722  let InstructionSet = AMDGPUInstrInfo;
723  let AssemblyParsers = [AMDGPUAsmParser];
724  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
725                                VOP3AsmParserVariant,
726                                SDWAAsmParserVariant,
727                                SDWA9AsmParserVariant,
728                                DPPAsmParserVariant];
729  let AssemblyWriters = [AMDGPUAsmWriter];
730  let AllowRegisterRenaming = 1;
731}
732
733// Dummy Instruction itineraries for pseudo instructions
734def ALU_NULL : FuncUnit;
735def NullALU : InstrItinClass;
736
737//===----------------------------------------------------------------------===//
738// Predicate helper class
739//===----------------------------------------------------------------------===//
740
741def TruePredicate : Predicate<"true">;
742
743def isSICI : Predicate<
744  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
745  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
746>, AssemblerPredicate<"!FeatureGCN3Encoding">;
747
748def isVI : Predicate <
749  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
750  AssemblerPredicate<"FeatureGCN3Encoding">;
751
752def isGFX9 : Predicate <
753  "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
754  AssemblerPredicate<"FeatureGFX9Insts">;
755
756// TODO: Either the name to be changed or we simply use IsCI!
757def isCIVI : Predicate <
758  "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
759  AssemblerPredicate<"FeatureCIInsts">;
760
761def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
762  AssemblerPredicate<"FeatureFlatAddressSpace">;
763
764def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
765  AssemblerPredicate<"FeatureFlatGlobalInsts">;
766def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
767  AssemblerPredicate<"FeatureFlatScratchInsts">;
768def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
769  AssemblerPredicate<"FeatureGFX9Insts">;
770
771def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
772  AssemblerPredicate<"FeatureUnpackedD16VMem">;
773def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
774  AssemblerPredicate<"!FeatureUnpackedD16VMem">;
775
776def D16PreservesUnusedBits : Predicate<"Subtarget->d16PreservesUnusedBits()">,
777  AssemblerPredicate<"FeatureD16PreservesUnusedBits">;
778
779def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
780def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
781
782def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
783  AssemblerPredicate<"FeatureGFX9Insts">;
784
785def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarryInsts()">,
786  AssemblerPredicate<"FeatureAddNoCarryInsts">;
787
788def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarryInsts()">,
789  AssemblerPredicate<"!FeatureAddNoCarryInsts">;
790
791def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
792  AssemblerPredicate<"Feature16BitInsts">;
793def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
794  AssemblerPredicate<"FeatureVOP3P">;
795
796def NotHasVOP3PInsts : Predicate<"!Subtarget->hasVOP3PInsts()">,
797  AssemblerPredicate<"!FeatureVOP3P">;
798
799def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
800  AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
801
802def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
803  AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
804
805def HasDPP : Predicate<"Subtarget->hasDPP()">,
806  AssemblerPredicate<"FeatureDPP">;
807
808def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
809  AssemblerPredicate<"FeatureIntClamp">;
810
811def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
812  AssemblerPredicate<"FeatureMadMixInsts">;
813
814def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
815  AssemblerPredicate<"FeatureScalarAtomics">;
816
817def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
818def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
819def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
820                      AssemblerPredicate<"FeatureVGPRIndexMode">;
821def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
822                AssemblerPredicate<"FeatureMovrel">;
823
824def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
825  AssemblerPredicate<"FeatureFmaMixInsts">;
826
827def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
828  AssemblerPredicate<"FeatureDLInsts">;
829
830
831def EnableLateCFGStructurize : Predicate<
832  "EnableLateStructurizeCFG">;
833
834// Exists to help track down where SubtargetPredicate isn't set rather
835// than letting tablegen crash with an unhelpful error.
836def InvalidPred : Predicate<"predicate not set on instruction or pattern">;
837
838class PredicateControl {
839  Predicate SubtargetPredicate = InvalidPred;
840  Predicate SIAssemblerPredicate = isSICI;
841  Predicate VIAssemblerPredicate = isVI;
842  list<Predicate> AssemblerPredicates = [];
843  Predicate AssemblerPredicate = TruePredicate;
844  list<Predicate> OtherPredicates = [];
845  list<Predicate> Predicates = !listconcat([SubtargetPredicate,
846                                            AssemblerPredicate],
847                                            AssemblerPredicates,
848                                            OtherPredicates);
849}
850
851class AMDGPUPat<dag pattern, dag result> : Pat<pattern, result>,
852  PredicateControl;
853
854
855// Include AMDGPU TD files
856include "R600Schedule.td"
857include "R600Processors.td"
858include "SISchedule.td"
859include "GCNProcessors.td"
860include "AMDGPUInstrInfo.td"
861include "AMDGPUIntrinsics.td"
862include "AMDGPURegisterInfo.td"
863include "AMDGPURegisterBanks.td"
864include "AMDGPUInstructions.td"
865include "AMDGPUCallingConv.td"
866include "AMDGPUSearchableTables.td"
867