1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21
22class BoolToList<bit Value> {
23  list<int> ret = !if(Value, [1]<int>, []<int>);
24}
25
26//===------------------------------------------------------------===//
27// Subtarget Features (device properties)
28//===------------------------------------------------------------===//
29
30def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
31  "FastFMAF32",
32  "true",
33  "Assuming f32 fma is at least as fast as mul + add"
34>;
35
36def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
37  "FastDenormalF32",
38  "true",
39  "Enabling denormals does not cause f32 instructions to run at f64 rates"
40>;
41
42def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
43  "MIMG_R128",
44  "true",
45  "Support 128-bit texture resources"
46>;
47
48def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
49  "HalfRate64Ops",
50  "true",
51  "Most fp64 instructions are half rate instead of quarter"
52>;
53
54def FullRate64Ops : SubtargetFeature<"full-rate-64-ops",
55  "FullRate64Ops",
56  "true",
57  "Most fp64 instructions are full rate"
58>;
59
60def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
61  "FlatAddressSpace",
62  "true",
63  "Support flat address space"
64>;
65
66def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
67  "FlatInstOffsets",
68  "true",
69  "Flat instructions have immediate offset addressing mode"
70>;
71
72def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
73  "FlatGlobalInsts",
74  "true",
75  "Have global_* flat memory instructions"
76>;
77
78def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
79  "FlatScratchInsts",
80  "true",
81  "Have scratch_* flat memory instructions"
82>;
83
84def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
85  "ScalarFlatScratchInsts",
86  "true",
87  "Have s_scratch_* flat memory instructions"
88>;
89
90def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
91  "AddNoCarryInsts",
92  "true",
93  "Have VALU add/sub instructions without carry out"
94>;
95
96def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
97  "UnalignedBufferAccess",
98  "true",
99  "Hardware supports unaligned global loads and stores"
100>;
101
102def FeatureTrapHandler: SubtargetFeature<"trap-handler",
103  "TrapHandler",
104  "true",
105  "Trap handler support"
106>;
107
108def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
109  "UnalignedScratchAccess",
110  "true",
111  "Support unaligned scratch loads and stores"
112>;
113
114def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access",
115  "UnalignedDSAccess",
116  "true",
117  "Hardware supports unaligned local and region loads and stores"
118>;
119
120def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
121  "HasApertureRegs",
122  "true",
123  "Has Memory Aperture Base and Size Registers"
124>;
125
126def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
127  "HasMadMixInsts",
128  "true",
129  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
130>;
131
132def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
133  "HasFmaMixInsts",
134  "true",
135  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
136>;
137
138def FeatureSupportsXNACK : SubtargetFeature<"xnack-support",
139  "SupportsXNACK",
140  "true",
141  "Hardware supports XNACK"
142>;
143
144// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
145// XNACK. The current default kernel driver setting is:
146// - graphics ring: XNACK disabled
147// - compute ring: XNACK enabled
148//
149// If XNACK is enabled, the VMEM latency can be worse.
150// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
151def FeatureXNACK : SubtargetFeature<"xnack",
152  "EnableXNACK",
153  "true",
154  "Enable XNACK support"
155>;
156
157def FeatureTgSplit : SubtargetFeature<"tgsplit",
158  "EnableTgSplit",
159  "true",
160  "Enable threadgroup split execution"
161>;
162
163def FeatureCuMode : SubtargetFeature<"cumode",
164  "EnableCuMode",
165  "true",
166  "Enable CU wavefront execution mode"
167>;
168
169def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
170  "SGPRInitBug",
171  "true",
172  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
173>;
174
175def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
176  "LDSMisalignedBug",
177  "true",
178  "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode"
179>;
180
181def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
182  "HasMFMAInlineLiteralBug",
183  "true",
184  "MFMA cannot use inline literal as SrcC"
185>;
186
187def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
188  "HasVcmpxPermlaneHazard",
189  "true",
190  "TODO: describe me"
191>;
192
193def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
194  "HasVMEMtoScalarWriteHazard",
195  "true",
196  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
197>;
198
199def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
200  "HasSMEMtoVectorWriteHazard",
201  "true",
202  "s_load_dword followed by v_cmp page faults"
203>;
204
205def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
206  "HasInstFwdPrefetchBug",
207  "true",
208  "S_INST_PREFETCH instruction causes shader to hang"
209>;
210
211def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
212  "HasVcmpxExecWARHazard",
213  "true",
214  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
215>;
216
217def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
218  "HasLdsBranchVmemWARHazard",
219  "true",
220  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
221>;
222
223def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
224  "HasNSAtoVMEMBug",
225  "true",
226  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
227>;
228
229def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
230  "HasFlatSegmentOffsetBug",
231  "true",
232  "GFX10 bug, inst_offset ignored in flat segment"
233>;
234
235def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
236  "HasOffset3fBug",
237  "true",
238  "Branch offset of 3f hardware bug"
239>;
240
241def FeatureImageStoreD16Bug : SubtargetFeature<"image-store-d16-bug",
242  "HasImageStoreD16Bug",
243  "true",
244  "Image Store D16 hardware bug"
245>;
246
247def FeatureImageGather4D16Bug : SubtargetFeature<"image-gather4-d16-bug",
248  "HasImageGather4D16Bug",
249  "true",
250  "Image Gather4 D16 hardware bug"
251>;
252
253class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
254  "ldsbankcount"#Value,
255  "LDSBankCount",
256  !cast<string>(Value),
257  "The number of LDS banks per compute unit."
258>;
259
260def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
261def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
262
263def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
264  "GCN3Encoding",
265  "true",
266  "Encoding format for VI"
267>;
268
269def FeatureCIInsts : SubtargetFeature<"ci-insts",
270  "CIInsts",
271  "true",
272  "Additional instructions for CI+"
273>;
274
275def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
276  "GFX8Insts",
277  "true",
278  "Additional instructions for GFX8+"
279>;
280
281def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
282  "GFX9Insts",
283  "true",
284  "Additional instructions for GFX9+"
285>;
286
287def FeatureGFX90AInsts : SubtargetFeature<"gfx90a-insts",
288  "GFX90AInsts",
289  "true",
290  "Additional instructions for GFX90A+"
291>;
292
293def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
294  "GFX10Insts",
295  "true",
296  "Additional instructions for GFX10+"
297>;
298
299def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts",
300  "GFX10_3Insts",
301  "true",
302  "Additional instructions for GFX10.3"
303>;
304
305def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
306  "GFX7GFX8GFX9Insts",
307  "true",
308  "Instructions shared in GFX7, GFX8, GFX9"
309>;
310
311def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
312  "HasSMemRealTime",
313  "true",
314  "Has s_memrealtime instruction"
315>;
316
317def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
318  "HasInv2PiInlineImm",
319  "true",
320  "Has 1 / (2 * pi) as inline immediate"
321>;
322
323def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
324  "Has16BitInsts",
325  "true",
326  "Has i16/f16 instructions"
327>;
328
329def FeatureVOP3P : SubtargetFeature<"vop3p",
330  "HasVOP3PInsts",
331  "true",
332  "Has VOP3P packed instructions"
333>;
334
335def FeatureMovrel : SubtargetFeature<"movrel",
336  "HasMovrel",
337  "true",
338  "Has v_movrel*_b32 instructions"
339>;
340
341def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
342  "HasVGPRIndexMode",
343  "true",
344  "Has VGPR mode register indexing"
345>;
346
347def FeatureScalarStores : SubtargetFeature<"scalar-stores",
348  "HasScalarStores",
349  "true",
350  "Has store scalar memory instructions"
351>;
352
353def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
354  "HasScalarAtomics",
355  "true",
356  "Has atomic scalar memory instructions"
357>;
358
359def FeatureSDWA : SubtargetFeature<"sdwa",
360  "HasSDWA",
361  "true",
362  "Support SDWA (Sub-DWORD Addressing) extension"
363>;
364
365def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
366  "HasSDWAOmod",
367  "true",
368  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
369>;
370
371def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
372  "HasSDWAScalar",
373  "true",
374  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
375>;
376
377def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
378  "HasSDWASdst",
379  "true",
380  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
381>;
382
383def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
384  "HasSDWAMac",
385  "true",
386  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
387>;
388
389def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
390  "HasSDWAOutModsVOPC",
391  "true",
392  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
393>;
394
395def FeatureDPP : SubtargetFeature<"dpp",
396  "HasDPP",
397  "true",
398  "Support DPP (Data Parallel Primitives) extension"
399>;
400
401// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
402def FeatureDPP8 : SubtargetFeature<"dpp8",
403  "HasDPP8",
404  "true",
405  "Support DPP8 (Data Parallel Primitives) extension"
406>;
407
408def Feature64BitDPP : SubtargetFeature<"dpp-64bit",
409  "Has64BitDPP",
410  "true",
411  "Support DPP (Data Parallel Primitives) extension"
412>;
413
414def FeaturePackedFP32Ops : SubtargetFeature<"packed-fp32-ops",
415  "HasPackedFP32Ops",
416  "true",
417  "Support packed fp32 instructions"
418>;
419
420def FeatureR128A16 : SubtargetFeature<"r128-a16",
421  "HasR128A16",
422  "true",
423  "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
424>;
425
426def FeatureGFX10A16 : SubtargetFeature<"a16",
427  "HasGFX10A16",
428  "true",
429  "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
430>;
431
432def FeatureG16 : SubtargetFeature<"g16",
433  "HasG16",
434  "true",
435  "Support G16 for 16-bit gradient image operands"
436>;
437
438def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
439  "HasNSAEncoding",
440  "true",
441  "Support NSA encoding for image instructions"
442>;
443
444def FeatureExtendedImageInsts : SubtargetFeature<"extended-image-insts",
445  "HasExtendedImageInsts",
446  "true",
447  "Support mips != 0, lod != 0, gather4, and get_lod"
448>;
449
450def FeatureGFX10_BEncoding : SubtargetFeature<"gfx10_b-encoding",
451  "GFX10_BEncoding",
452  "true",
453  "Encoding format GFX10_B"
454>;
455
456def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
457  "HasIntClamp",
458  "true",
459  "Support clamp for integer destination"
460>;
461
462def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
463  "HasUnpackedD16VMem",
464  "true",
465  "Has unpacked d16 vmem instructions"
466>;
467
468def FeatureDLInsts : SubtargetFeature<"dl-insts",
469  "HasDLInsts",
470  "true",
471  "Has v_fmac_f32 and v_xnor_b32 instructions"
472>;
473
474def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
475  "HasDot1Insts",
476  "true",
477  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
478>;
479
480def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
481  "HasDot2Insts",
482  "true",
483  "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
484>;
485
486def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
487  "HasDot3Insts",
488  "true",
489  "Has v_dot8c_i32_i4 instruction"
490>;
491
492def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
493  "HasDot4Insts",
494  "true",
495  "Has v_dot2c_i32_i16 instruction"
496>;
497
498def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
499  "HasDot5Insts",
500  "true",
501  "Has v_dot2c_f32_f16 instruction"
502>;
503
504def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
505  "HasDot6Insts",
506  "true",
507  "Has v_dot4c_i32_i8 instruction"
508>;
509
510def FeatureMAIInsts : SubtargetFeature<"mai-insts",
511  "HasMAIInsts",
512  "true",
513  "Has mAI instructions"
514>;
515
516def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
517  "HasPkFmacF16Inst",
518  "true",
519  "Has v_pk_fmac_f16 instruction"
520>;
521
522def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
523  "HasAtomicFaddInsts",
524  "true",
525  "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
526  "global_atomic_pk_add_f16 instructions",
527  [FeatureFlatGlobalInsts]
528>;
529
530def FeatureSupportsSRAMECC : SubtargetFeature<"sramecc-support",
531  "SupportsSRAMECC",
532  "true",
533  "Hardware supports SRAMECC"
534>;
535
536def FeatureSRAMECC : SubtargetFeature<"sramecc",
537  "EnableSRAMECC",
538  "true",
539  "Enable SRAMECC"
540>;
541
542def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
543  "HasNoSdstCMPX",
544  "true",
545  "V_CMPX does not write VCC/SGPR in addition to EXEC"
546>;
547
548def FeatureVscnt : SubtargetFeature<"vscnt",
549  "HasVscnt",
550  "true",
551  "Has separate store vscnt counter"
552>;
553
554def FeatureGetWaveIdInst : SubtargetFeature<"get-wave-id-inst",
555  "HasGetWaveIdInst",
556  "true",
557  "Has s_get_waveid_in_workgroup instruction"
558>;
559
560def FeatureSMemTimeInst : SubtargetFeature<"s-memtime-inst",
561  "HasSMemTimeInst",
562  "true",
563  "Has s_memtime instruction"
564>;
565
566def FeatureMadMacF32Insts : SubtargetFeature<"mad-mac-f32-insts",
567  "HasMadMacF32Insts",
568  "true",
569  "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions"
570>;
571
572def FeatureDsSrc2Insts : SubtargetFeature<"ds-src2-insts",
573  "HasDsSrc2Insts",
574  "true",
575  "Has ds_*_src2 instructions"
576>;
577
578def FeatureRegisterBanking : SubtargetFeature<"register-banking",
579  "HasRegisterBanking",
580  "true",
581  "Has register banking"
582>;
583
584def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
585  "HasVOP3Literal",
586  "true",
587  "Can use one literal in VOP3"
588>;
589
590def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
591  "HasNoDataDepHazard",
592  "true",
593  "Does not need SW waitstates"
594>;
595
596//===------------------------------------------------------------===//
597// Subtarget Features (options and debugging)
598//===------------------------------------------------------------===//
599
600class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
601  "max-private-element-size-"#size,
602  "MaxPrivateElementSize",
603  !cast<string>(size),
604  "Maximum private access size may be "#size
605>;
606
607def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
608def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
609def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
610
611def FeatureDumpCode : SubtargetFeature <"DumpCode",
612  "DumpCode",
613  "true",
614  "Dump MachineInstrs in the CodeEmitter"
615>;
616
617def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
618  "DumpCode",
619  "true",
620  "Dump MachineInstrs in the CodeEmitter"
621>;
622
623// XXX - This should probably be removed once enabled by default
624def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
625  "EnableLoadStoreOpt",
626  "true",
627  "Enable SI load/store optimizer pass"
628>;
629
630// Performance debugging feature. Allow using DS instruction immediate
631// offsets even if the base pointer can't be proven to be base. On SI,
632// base pointer values that won't give the same result as a 16-bit add
633// are not safe to fold, but this will override the conservative test
634// for the base pointer.
635def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
636  "unsafe-ds-offset-folding",
637  "EnableUnsafeDSOffsetFolding",
638  "true",
639  "Force using DS instruction immediate offsets on SI"
640>;
641
642def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
643  "EnableSIScheduler",
644  "true",
645  "Enable SI Machine Scheduler"
646>;
647
648def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
649  "EnableDS128",
650  "true",
651  "Use ds_{read|write}_b128"
652>;
653
654// Sparse texture support requires that all result registers are zeroed when
655// PRTStrictNull is set to true. This feature is turned on for all architectures
656// but is enabled as a feature in case there are situations where PRTStrictNull
657// is disabled by the driver.
658def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
659  "EnablePRTStrictNull",
660  "true",
661  "Enable zeroing of result registers for sparse texture fetches"
662>;
663
664// Unless +-flat-for-global is specified, turn on FlatForGlobal for
665// all OS-es on VI and newer hardware to avoid assertion failures due
666// to missing ADDR64 variants of MUBUF instructions.
667// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
668// instructions.
669
670def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
671  "FlatForGlobal",
672  "true",
673  "Force to generate flat instruction for global"
674>;
675
676def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
677  "auto-waitcnt-before-barrier",
678  "AutoWaitcntBeforeBarrier",
679  "true",
680  "Hardware automatically inserts waitcnt before barrier"
681>;
682
683def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
684  "HasTrigReducedRange",
685  "true",
686  "Requires use of fract on arguments to trig instructions"
687>;
688
689// Alignment enforcement is controlled by a configuration register:
690// SH_MEM_CONFIG.alignment_mode
691def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode",
692  "UnalignedAccessMode",
693  "true",
694  "Enable unaligned global, local and region loads and stores if the hardware"
695  " supports it"
696>;
697
698def FeaturePackedTID : SubtargetFeature<"packed-tid",
699  "HasPackedTID",
700  "true",
701  "Workitem IDs are packed into v0 at kernel launch"
702>;
703
704// Dummy feature used to disable assembler instructions.
705def FeatureDisable : SubtargetFeature<"",
706  "FeatureDisable","true",
707  "Dummy feature to disable assembler instructions"
708>;
709
710class GCNSubtargetFeatureGeneration <string Value,
711                                     string FeatureName,
712                                     list<SubtargetFeature> Implies> :
713        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
714
715def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
716    "southern-islands",
717  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
718  FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,
719  FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
720  FeatureTrigReducedRange, FeatureExtendedImageInsts
721  ]
722>;
723
724def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
725    "sea-islands",
726  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
727  FeatureWavefrontSize64, FeatureFlatAddressSpace,
728  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
729  FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
730  FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureUnalignedBufferAccess
731  ]
732>;
733
734def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
735  "volcanic-islands",
736  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
737   FeatureWavefrontSize64, FeatureFlatAddressSpace,
738   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
739   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
740   FeatureScalarStores, FeatureInv2PiInlineImm,
741   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
742   FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
743   FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
744   FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureFastDenormalF32,
745   FeatureUnalignedBufferAccess
746  ]
747>;
748
749def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
750  "gfx9",
751  [FeatureFP64, FeatureLocalMemorySize65536,
752   FeatureWavefrontSize64, FeatureFlatAddressSpace,
753   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
754   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
755   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
756   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
757   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
758   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
759   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
760   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
761   FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureSupportsXNACK,
762   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess
763  ]
764>;
765
766def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
767  "gfx10",
768  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
769   FeatureFlatAddressSpace,
770   FeatureCIInsts, Feature16BitInsts,
771   FeatureSMemRealTime, FeatureInv2PiInlineImm,
772   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
773   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
774   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
775   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
776   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
777   FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
778   FeatureVOP3Literal, FeatureDPP8, FeatureExtendedImageInsts,
779   FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
780   FeatureGFX10A16, FeatureFastDenormalF32, FeatureG16,
781   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess
782  ]
783>;
784
785class FeatureSet<list<SubtargetFeature> Features_> {
786  list<SubtargetFeature> Features = Features_;
787}
788
789def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
790   FeatureFastFMAF32,
791   HalfRate64Ops,
792   FeatureLDSBankCount32]>;
793
794def FeatureISAVersion6_0_1 : FeatureSet<
795  [FeatureSouthernIslands,
796   FeatureLDSBankCount32]>;
797
798def FeatureISAVersion6_0_2 : FeatureSet<
799  [FeatureSouthernIslands,
800   FeatureLDSBankCount32]>;
801
802def FeatureISAVersion7_0_0 : FeatureSet<
803  [FeatureSeaIslands,
804   FeatureLDSBankCount32]>;
805
806def FeatureISAVersion7_0_1 : FeatureSet<
807  [FeatureSeaIslands,
808   HalfRate64Ops,
809   FeatureLDSBankCount32,
810   FeatureFastFMAF32]>;
811
812def FeatureISAVersion7_0_2 : FeatureSet<
813  [FeatureSeaIslands,
814   FeatureLDSBankCount16,
815   FeatureFastFMAF32]>;
816
817def FeatureISAVersion7_0_3 : FeatureSet<
818  [FeatureSeaIslands,
819   FeatureLDSBankCount16]>;
820
821def FeatureISAVersion7_0_4 : FeatureSet<
822  [FeatureSeaIslands,
823   FeatureLDSBankCount32]>;
824
825def FeatureISAVersion7_0_5 : FeatureSet<
826  [FeatureSeaIslands,
827   FeatureLDSBankCount16]>;
828
829def FeatureISAVersion8_0_1 : FeatureSet<
830  [FeatureVolcanicIslands,
831   FeatureFastFMAF32,
832   HalfRate64Ops,
833   FeatureLDSBankCount32,
834   FeatureSupportsXNACK,
835   FeatureUnpackedD16VMem]>;
836
837def FeatureISAVersion8_0_2 : FeatureSet<
838  [FeatureVolcanicIslands,
839   FeatureLDSBankCount32,
840   FeatureSGPRInitBug,
841   FeatureUnpackedD16VMem]>;
842
843def FeatureISAVersion8_0_3 : FeatureSet<
844  [FeatureVolcanicIslands,
845   FeatureLDSBankCount32,
846   FeatureUnpackedD16VMem]>;
847
848def FeatureISAVersion8_0_5 : FeatureSet<
849  [FeatureVolcanicIslands,
850   FeatureLDSBankCount32,
851   FeatureSGPRInitBug,
852   FeatureUnpackedD16VMem]>;
853
854def FeatureISAVersion8_1_0 : FeatureSet<
855  [FeatureVolcanicIslands,
856   FeatureLDSBankCount16,
857   FeatureSupportsXNACK,
858   FeatureImageStoreD16Bug,
859   FeatureImageGather4D16Bug]>;
860
861def FeatureISAVersion9_0_0 : FeatureSet<
862  [FeatureGFX9,
863   FeatureMadMixInsts,
864   FeatureLDSBankCount32,
865   FeatureDsSrc2Insts,
866   FeatureExtendedImageInsts,
867   FeatureMadMacF32Insts,
868   FeatureImageGather4D16Bug]>;
869
870def FeatureISAVersion9_0_2 : FeatureSet<
871  [FeatureGFX9,
872   FeatureMadMixInsts,
873   FeatureLDSBankCount32,
874   FeatureDsSrc2Insts,
875   FeatureExtendedImageInsts,
876   FeatureMadMacF32Insts,
877   FeatureImageGather4D16Bug]>;
878
879def FeatureISAVersion9_0_4 : FeatureSet<
880  [FeatureGFX9,
881   FeatureLDSBankCount32,
882   FeatureDsSrc2Insts,
883   FeatureExtendedImageInsts,
884   FeatureMadMacF32Insts,
885   FeatureFmaMixInsts,
886   FeatureImageGather4D16Bug]>;
887
888def FeatureISAVersion9_0_6 : FeatureSet<
889  [FeatureGFX9,
890   HalfRate64Ops,
891   FeatureFmaMixInsts,
892   FeatureLDSBankCount32,
893   FeatureDsSrc2Insts,
894   FeatureExtendedImageInsts,
895   FeatureMadMacF32Insts,
896   FeatureDLInsts,
897   FeatureDot1Insts,
898   FeatureDot2Insts,
899   FeatureSupportsSRAMECC,
900   FeatureImageGather4D16Bug]>;
901
902def FeatureISAVersion9_0_8 : FeatureSet<
903  [FeatureGFX9,
904   HalfRate64Ops,
905   FeatureFmaMixInsts,
906   FeatureLDSBankCount32,
907   FeatureDsSrc2Insts,
908   FeatureExtendedImageInsts,
909   FeatureMadMacF32Insts,
910   FeatureDLInsts,
911   FeatureDot1Insts,
912   FeatureDot2Insts,
913   FeatureDot3Insts,
914   FeatureDot4Insts,
915   FeatureDot5Insts,
916   FeatureDot6Insts,
917   FeatureMAIInsts,
918   FeaturePkFmacF16Inst,
919   FeatureAtomicFaddInsts,
920   FeatureSupportsSRAMECC,
921   FeatureMFMAInlineLiteralBug,
922   FeatureImageGather4D16Bug]>;
923
924def FeatureISAVersion9_0_9 : FeatureSet<
925  [FeatureGFX9,
926   FeatureMadMixInsts,
927   FeatureLDSBankCount32,
928   FeatureDsSrc2Insts,
929   FeatureExtendedImageInsts,
930   FeatureMadMacF32Insts,
931   FeatureImageGather4D16Bug]>;
932
933def FeatureISAVersion9_0_A : FeatureSet<
934  [FeatureGFX9,
935   FeatureGFX90AInsts,
936   FeatureFmaMixInsts,
937   FeatureLDSBankCount32,
938   FeatureDLInsts,
939   FeatureDot1Insts,
940   FeatureDot2Insts,
941   FeatureDot3Insts,
942   FeatureDot4Insts,
943   FeatureDot5Insts,
944   FeatureDot6Insts,
945   Feature64BitDPP,
946   FeaturePackedFP32Ops,
947   FeatureMAIInsts,
948   FeaturePkFmacF16Inst,
949   FeatureAtomicFaddInsts,
950   FeatureMadMacF32Insts,
951   FeatureSupportsSRAMECC,
952   FeaturePackedTID,
953   FullRate64Ops]>;
954
955def FeatureISAVersion9_0_C : FeatureSet<
956  [FeatureGFX9,
957   FeatureMadMixInsts,
958   FeatureLDSBankCount32,
959   FeatureXNACK,
960   FeatureDsSrc2Insts,
961   FeatureExtendedImageInsts,
962   FeatureImageGather4D16Bug]>;
963
964// TODO: Organize more features into groups.
965def FeatureGroup {
966  // Bugs present on gfx10.1.
967  list<SubtargetFeature> GFX10_1_Bugs = [
968    FeatureVcmpxPermlaneHazard,
969    FeatureVMEMtoScalarWriteHazard,
970    FeatureSMEMtoVectorWriteHazard,
971    FeatureInstFwdPrefetchBug,
972    FeatureVcmpxExecWARHazard,
973    FeatureLdsBranchVmemWARHazard,
974    FeatureNSAtoVMEMBug,
975    FeatureOffset3fBug,
976    FeatureFlatSegmentOffsetBug
977   ];
978}
979
980def FeatureISAVersion10_1_0 : FeatureSet<
981  !listconcat(FeatureGroup.GFX10_1_Bugs,
982    [FeatureGFX10,
983     FeatureLDSBankCount32,
984     FeatureDLInsts,
985     FeatureNSAEncoding,
986     FeatureWavefrontSize32,
987     FeatureScalarStores,
988     FeatureScalarAtomics,
989     FeatureScalarFlatScratchInsts,
990     FeatureGetWaveIdInst,
991     FeatureSMemTimeInst,
992     FeatureMadMacF32Insts,
993     FeatureDsSrc2Insts,
994     FeatureLdsMisalignedBug,
995     FeatureSupportsXNACK])>;
996
997def FeatureISAVersion10_1_1 : FeatureSet<
998  !listconcat(FeatureGroup.GFX10_1_Bugs,
999    [FeatureGFX10,
1000     FeatureLDSBankCount32,
1001     FeatureDLInsts,
1002     FeatureDot1Insts,
1003     FeatureDot2Insts,
1004     FeatureDot5Insts,
1005     FeatureDot6Insts,
1006     FeatureNSAEncoding,
1007     FeatureWavefrontSize32,
1008     FeatureScalarStores,
1009     FeatureScalarAtomics,
1010     FeatureScalarFlatScratchInsts,
1011     FeatureGetWaveIdInst,
1012     FeatureSMemTimeInst,
1013     FeatureMadMacF32Insts,
1014     FeatureDsSrc2Insts,
1015     FeatureLdsMisalignedBug,
1016     FeatureSupportsXNACK])>;
1017
1018def FeatureISAVersion10_1_2 : FeatureSet<
1019  !listconcat(FeatureGroup.GFX10_1_Bugs,
1020    [FeatureGFX10,
1021     FeatureLDSBankCount32,
1022     FeatureDLInsts,
1023     FeatureDot1Insts,
1024     FeatureDot2Insts,
1025     FeatureDot5Insts,
1026     FeatureDot6Insts,
1027     FeatureNSAEncoding,
1028     FeatureWavefrontSize32,
1029     FeatureScalarStores,
1030     FeatureScalarAtomics,
1031     FeatureScalarFlatScratchInsts,
1032     FeatureGetWaveIdInst,
1033     FeatureSMemTimeInst,
1034     FeatureMadMacF32Insts,
1035     FeatureDsSrc2Insts,
1036     FeatureLdsMisalignedBug,
1037     FeatureSupportsXNACK])>;
1038
1039def FeatureISAVersion10_3_0 : FeatureSet<
1040  [FeatureGFX10,
1041   FeatureGFX10_BEncoding,
1042   FeatureGFX10_3Insts,
1043   FeatureLDSBankCount32,
1044   FeatureDLInsts,
1045   FeatureDot1Insts,
1046   FeatureDot2Insts,
1047   FeatureDot5Insts,
1048   FeatureDot6Insts,
1049   FeatureNSAEncoding,
1050   FeatureWavefrontSize32]>;
1051
1052//===----------------------------------------------------------------------===//
1053
1054def AMDGPUInstrInfo : InstrInfo {
1055  let guessInstructionProperties = 1;
1056  let noNamedPositionallyEncodedOperands = 1;
1057}
1058
1059def AMDGPUAsmParser : AsmParser {
1060  // Some of the R600 registers have the same name, so this crashes.
1061  // For example T0_XYZW and T0_XY both have the asm name T0.
1062  let ShouldEmitMatchRegisterName = 0;
1063}
1064
1065def AMDGPUAsmWriter : AsmWriter {
1066  int PassSubtarget = 1;
1067}
1068
1069def AMDGPUAsmVariants {
1070  string Default = "Default";
1071  int Default_ID = 0;
1072  string VOP3 = "VOP3";
1073  int VOP3_ID = 1;
1074  string SDWA = "SDWA";
1075  int SDWA_ID = 2;
1076  string SDWA9 = "SDWA9";
1077  int SDWA9_ID = 3;
1078  string DPP = "DPP";
1079  int DPP_ID = 4;
1080  string Disable = "Disable";
1081  int Disable_ID = 5;
1082}
1083
1084def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
1085  let Variant = AMDGPUAsmVariants.Default_ID;
1086  let Name = AMDGPUAsmVariants.Default;
1087}
1088
1089def VOP3AsmParserVariant : AsmParserVariant {
1090  let Variant = AMDGPUAsmVariants.VOP3_ID;
1091  let Name = AMDGPUAsmVariants.VOP3;
1092}
1093
1094def SDWAAsmParserVariant : AsmParserVariant {
1095  let Variant = AMDGPUAsmVariants.SDWA_ID;
1096  let Name = AMDGPUAsmVariants.SDWA;
1097}
1098
1099def SDWA9AsmParserVariant : AsmParserVariant {
1100  let Variant = AMDGPUAsmVariants.SDWA9_ID;
1101  let Name = AMDGPUAsmVariants.SDWA9;
1102}
1103
1104
1105def DPPAsmParserVariant : AsmParserVariant {
1106  let Variant = AMDGPUAsmVariants.DPP_ID;
1107  let Name = AMDGPUAsmVariants.DPP;
1108}
1109
1110def AMDGPU : Target {
1111  // Pull in Instruction Info:
1112  let InstructionSet = AMDGPUInstrInfo;
1113  let AssemblyParsers = [AMDGPUAsmParser];
1114  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
1115                                VOP3AsmParserVariant,
1116                                SDWAAsmParserVariant,
1117                                SDWA9AsmParserVariant,
1118                                DPPAsmParserVariant];
1119  let AssemblyWriters = [AMDGPUAsmWriter];
1120  let AllowRegisterRenaming = 1;
1121}
1122
1123// Dummy Instruction itineraries for pseudo instructions
1124def ALU_NULL : FuncUnit;
1125def NullALU : InstrItinClass;
1126
1127//===----------------------------------------------------------------------===//
1128// Predicate helper class
1129//===----------------------------------------------------------------------===//
1130
1131def isGFX6 :
1132  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1133  AssemblerPredicate<(all_of FeatureSouthernIslands)>;
1134
1135def isGFX6GFX7 :
1136  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1137            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1138  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
1139
1140def isGFX6GFX7GFX10 :
1141  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1142            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1143            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1144  AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
1145
1146def isGFX7Only :
1147  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1148  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
1149
1150def isGFX7GFX10 :
1151  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1152            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1153  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
1154
1155def isGFX7GFX8GFX9 :
1156  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1157            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1158            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1159  AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
1160
1161def isGFX6GFX7GFX8GFX9 :
1162  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1163            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1164            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1165            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1166  AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
1167
1168def isGFX6GFX7GFX8GFX9NotGFX90A :
1169  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1170            "(Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1171            " Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1172            " Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1173            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1174  AssemblerPredicate<(all_of (not FeatureGFX10Insts), (not FeatureGFX90AInsts))>;
1175
1176def isGFX7Plus :
1177  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1178  AssemblerPredicate<(all_of FeatureCIInsts)>;
1179
1180def isGFX8Plus :
1181  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1182  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1183
1184def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1185                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1186  AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1187
1188def isGFX9Plus :
1189  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1190  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1191
1192def isGFX9Only : Predicate <
1193  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1194  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1195
1196def isGCN3ExcludingGFX90A :
1197  Predicate<"Subtarget->isGCN3Encoding() && !Subtarget->hasGFX90AInsts()">,
1198  AssemblerPredicate<(all_of FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1199
1200def isGFX90APlus :
1201  Predicate<"Subtarget->hasGFX90AInsts()">,
1202  AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1203
1204def isNotGFX90APlus :
1205  Predicate<"!Subtarget->hasGFX90AInsts()">,
1206  AssemblerPredicate<(all_of (not FeatureGFX90AInsts))>;
1207
1208def isGFX8GFX9NotGFX90A :
1209  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1210            "(Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1211            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1212  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1213
1214def isGFX90AOnly :
1215  Predicate<"Subtarget->hasGFX90AInsts()">,
1216  AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1217
1218def isGFX8GFX9 :
1219  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1220            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1221  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1222
1223def isGFX10Plus :
1224  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1225  AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1226
1227def isGFX10Before1030 :
1228  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 &&"
1229            "!Subtarget->hasGFX10_3Insts()">,
1230  AssemblerPredicate<(all_of FeatureGFX10Insts,(not FeatureGFX10_3Insts))>;
1231
1232def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1233  AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1234
1235def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1236  AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1237def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1238  AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1239def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1240  AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1241def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1242  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1243
1244def HasFlatScratchSTMode : Predicate<"Subtarget->hasFlatScratchSTMode()">,
1245  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1246
1247def HasGFX10_BEncoding : Predicate<"Subtarget->hasGFX10_BEncoding()">,
1248  AssemblerPredicate<(all_of FeatureGFX10_BEncoding)>;
1249
1250def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1251  AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1252def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1253  AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1254
1255def D16PreservesUnusedBits :
1256  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1257  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1258
1259def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1260def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1261
1262def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1263  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1264
1265def HasLDSFPAtomics : Predicate<"Subtarget->hasLDSFPAtomics()">,
1266  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1267
1268def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1269  AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1270
1271def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1272
1273def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1274  AssemblerPredicate<(all_of Feature16BitInsts)>;
1275def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1276  AssemblerPredicate<(all_of FeatureVOP3P)>;
1277
1278def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
1279def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
1280
1281def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1282  AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1283
1284def HasSDWA9 :
1285  Predicate<"Subtarget->hasSDWA()">,
1286  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1287
1288def HasSDWA10 :
1289  Predicate<"Subtarget->hasSDWA()">,
1290  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1291
1292def HasDPP : Predicate<"Subtarget->hasDPP()">,
1293  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1294
1295def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1296  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1297
1298def Has64BitDPP : Predicate<"Subtarget->has64BitDPP()">,
1299  AssemblerPredicate<(all_of Feature64BitDPP)>;
1300
1301def HasPackedFP32Ops : Predicate<"Subtarget->hasPackedFP32Ops()">,
1302  AssemblerPredicate<(all_of FeaturePackedFP32Ops)>;
1303
1304def HasExtendedImageInsts : Predicate<"Subtarget->hasExtendedImageInsts()">,
1305  AssemblerPredicate<(all_of FeatureExtendedImageInsts)>;
1306
1307def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1308  AssemblerPredicate<(all_of FeatureR128A16)>;
1309
1310def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1311  AssemblerPredicate<(all_of FeatureGFX10A16)>;
1312
1313def HasG16 : Predicate<"Subtarget->hasG16()">,
1314  AssemblerPredicate<(all_of FeatureG16)>;
1315
1316def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1317  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1318
1319def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1320  AssemblerPredicate<(all_of FeatureIntClamp)>;
1321
1322def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1323  AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1324
1325def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1326  AssemblerPredicate<(all_of FeatureScalarStores)>;
1327
1328def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1329  AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1330
1331def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1332  AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1333
1334def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1335  AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1336
1337def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1338def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1339def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1340                      AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1341def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1342                AssemblerPredicate<(all_of FeatureMovrel)>;
1343
1344def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1345  AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1346
1347def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1348  AssemblerPredicate<(all_of FeatureDLInsts)>;
1349
1350def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1351  AssemblerPredicate<(all_of FeatureDot1Insts)>;
1352
1353def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1354  AssemblerPredicate<(all_of FeatureDot2Insts)>;
1355
1356def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1357  AssemblerPredicate<(all_of FeatureDot3Insts)>;
1358
1359def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1360  AssemblerPredicate<(all_of FeatureDot4Insts)>;
1361
1362def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1363  AssemblerPredicate<(all_of FeatureDot5Insts)>;
1364
1365def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1366  AssemblerPredicate<(all_of FeatureDot6Insts)>;
1367
1368def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">,
1369  AssemblerPredicate<(all_of FeatureGetWaveIdInst)>;
1370
1371def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1372  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1373
1374def HasSMemRealTime : Predicate<"Subtarget->hasSMemRealTime()">,
1375  AssemblerPredicate<(all_of FeatureSMemRealTime)>;
1376
1377def HasSMemTimeInst : Predicate<"Subtarget->hasSMemTimeInst()">,
1378  AssemblerPredicate<(all_of FeatureSMemTimeInst)>;
1379
1380def HasNoSMemTimeInst : Predicate<"!Subtarget->hasSMemTimeInst()">;
1381
1382def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1383  AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1384
1385def HasMadMacF32Insts : Predicate<"Subtarget->hasMadMacF32Insts()">,
1386  AssemblerPredicate<(all_of FeatureMadMacF32Insts)>;
1387
1388def HasFmaLegacy32 : Predicate<"Subtarget->hasGFX10_3Insts()">,
1389  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1390
1391def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1392  AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>;
1393
1394def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
1395  AssemblerPredicate<(all_of FeatureDsSrc2Insts)>;
1396
1397def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">,
1398  AssemblerPredicate<(all_of FeatureOffset3fBug)>;
1399
1400def EnableLateCFGStructurize : Predicate<
1401  "EnableLateStructurizeCFG">;
1402
1403def EnableFlatScratch : Predicate<"Subtarget->enableFlatScratch()">;
1404
1405def DisableFlatScratch : Predicate<"!Subtarget->enableFlatScratch()">;
1406
1407def HasUnalignedAccessMode : Predicate<"Subtarget->hasUnalignedAccessMode()">,
1408  AssemblerPredicate<(all_of FeatureUnalignedAccessMode)>;
1409
1410// Include AMDGPU TD files
1411include "SISchedule.td"
1412include "GCNProcessors.td"
1413include "AMDGPUInstrInfo.td"
1414include "SIRegisterInfo.td"
1415include "AMDGPURegisterBanks.td"
1416include "AMDGPUInstructions.td"
1417include "SIInstrInfo.td"
1418include "AMDGPUCallingConv.td"
1419include "AMDGPUSearchableTables.td"
1420