1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===------------------------------------------------------------===//
9
10include "llvm/TableGen/SearchableTable.td"
11include "llvm/Target/Target.td"
12include "AMDGPUFeatures.td"
13
14//===------------------------------------------------------------===//
15// Subtarget Features (device properties)
16//===------------------------------------------------------------===//
17
18def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
19  "FastFMAF32",
20  "true",
21  "Assuming f32 fma is at least as fast as mul + add"
22>;
23
24def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
25  "MIMG_R128",
26  "true",
27  "Support 128-bit texture resources"
28>;
29
30def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
31  "HalfRate64Ops",
32  "true",
33  "Most fp64 instructions are half rate instead of quarter"
34>;
35
36def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
37  "FlatAddressSpace",
38  "true",
39  "Support flat address space"
40>;
41
42def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
43  "FlatInstOffsets",
44  "true",
45  "Flat instructions have immediate offset addressing mode"
46>;
47
48def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
49  "FlatGlobalInsts",
50  "true",
51  "Have global_* flat memory instructions"
52>;
53
54def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
55  "FlatScratchInsts",
56  "true",
57  "Have scratch_* flat memory instructions"
58>;
59
60def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
61  "AddNoCarryInsts",
62  "true",
63  "Have VALU add/sub instructions without carry out"
64>;
65
66def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
67  "UnalignedBufferAccess",
68  "true",
69  "Support unaligned global loads and stores"
70>;
71
72def FeatureTrapHandler: SubtargetFeature<"trap-handler",
73  "TrapHandler",
74  "true",
75  "Trap handler support"
76>;
77
78def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
79  "UnalignedScratchAccess",
80  "true",
81  "Support unaligned scratch loads and stores"
82>;
83
84def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
85  "HasApertureRegs",
86  "true",
87  "Has Memory Aperture Base and Size Registers"
88>;
89
90def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
91  "HasMadMixInsts",
92  "true",
93  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
94>;
95
96def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
97  "HasFmaMixInsts",
98  "true",
99  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
100>;
101
102// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
103// XNACK. The current default kernel driver setting is:
104// - graphics ring: XNACK disabled
105// - compute ring: XNACK enabled
106//
107// If XNACK is enabled, the VMEM latency can be worse.
108// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
109def FeatureXNACK : SubtargetFeature<"xnack",
110  "EnableXNACK",
111  "true",
112  "Enable XNACK support"
113>;
114
115def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
116  "SGPRInitBug",
117  "true",
118  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
119>;
120
121class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
122  "ldsbankcount"#Value,
123  "LDSBankCount",
124  !cast<string>(Value),
125  "The number of LDS banks per compute unit."
126>;
127
128def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
129def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
130
131def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
132  "GCN3Encoding",
133  "true",
134  "Encoding format for VI"
135>;
136
137def FeatureCIInsts : SubtargetFeature<"ci-insts",
138  "CIInsts",
139  "true",
140  "Additional instructions for CI+"
141>;
142
143def FeatureVIInsts : SubtargetFeature<"vi-insts",
144  "VIInsts",
145  "true",
146  "Additional instructions for VI+"
147>;
148
149def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
150  "GFX9Insts",
151  "true",
152  "Additional instructions for GFX9+"
153>;
154
155def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
156  "HasSMemRealTime",
157  "true",
158  "Has s_memrealtime instruction"
159>;
160
161def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
162  "HasInv2PiInlineImm",
163  "true",
164  "Has 1 / (2 * pi) as inline immediate"
165>;
166
167def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
168  "Has16BitInsts",
169  "true",
170  "Has i16/f16 instructions"
171>;
172
173def FeatureVOP3P : SubtargetFeature<"vop3p",
174  "HasVOP3PInsts",
175  "true",
176  "Has VOP3P packed instructions"
177>;
178
179def FeatureMovrel : SubtargetFeature<"movrel",
180  "HasMovrel",
181  "true",
182  "Has v_movrel*_b32 instructions"
183>;
184
185def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
186  "HasVGPRIndexMode",
187  "true",
188  "Has VGPR mode register indexing"
189>;
190
191def FeatureScalarStores : SubtargetFeature<"scalar-stores",
192  "HasScalarStores",
193  "true",
194  "Has store scalar memory instructions"
195>;
196
197def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
198  "HasScalarAtomics",
199  "true",
200  "Has atomic scalar memory instructions"
201>;
202
203def FeatureSDWA : SubtargetFeature<"sdwa",
204  "HasSDWA",
205  "true",
206  "Support SDWA (Sub-DWORD Addressing) extension"
207>;
208
209def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
210  "HasSDWAOmod",
211  "true",
212  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
213>;
214
215def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
216  "HasSDWAScalar",
217  "true",
218  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
219>;
220
221def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
222  "HasSDWASdst",
223  "true",
224  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
225>;
226
227def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
228  "HasSDWAMac",
229  "true",
230  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
231>;
232
233def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
234  "HasSDWAOutModsVOPC",
235  "true",
236  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
237>;
238
239def FeatureDPP : SubtargetFeature<"dpp",
240  "HasDPP",
241  "true",
242  "Support DPP (Data Parallel Primitives) extension"
243>;
244
245def FeatureR128A16 : SubtargetFeature<"r128-a16",
246  "HasR128A16",
247  "true",
248  "Support 16 bit coordindates/gradients/lod/clamp/mip types on gfx9"
249>;
250
251def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
252  "HasIntClamp",
253  "true",
254  "Support clamp for integer destination"
255>;
256
257def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
258  "HasUnpackedD16VMem",
259  "true",
260  "Has unpacked d16 vmem instructions"
261>;
262
263def FeatureDLInsts : SubtargetFeature<"dl-insts",
264  "HasDLInsts",
265  "true",
266  "Has deep learning instructions"
267>;
268
269def FeatureD16PreservesUnusedBits : SubtargetFeature<
270  "d16-preserves-unused-bits",
271  "D16PreservesUnusedBits",
272  "true",
273  "If present, then instructions defined by HasD16LoadStore predicate preserve "
274  "unused bits. Otherwise instructions defined by HasD16LoadStore predicate "
275  "zero unused bits."
276>;
277
278//===------------------------------------------------------------===//
279// Subtarget Features (options and debugging)
280//===------------------------------------------------------------===//
281
282// Denormal handling for fp64 and fp16 is controlled by the same
283// config register when fp16 supported.
284// TODO: Do we need a separate f16 setting when not legal?
285def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
286  "FP64FP16Denormals",
287  "true",
288  "Enable double and half precision denormal handling",
289  [FeatureFP64]
290>;
291
292def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
293  "FP64FP16Denormals",
294  "true",
295  "Enable double and half precision denormal handling",
296  [FeatureFP64, FeatureFP64FP16Denormals]
297>;
298
299def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
300  "FP64FP16Denormals",
301  "true",
302  "Enable half precision denormal handling",
303  [FeatureFP64FP16Denormals]
304>;
305
306def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
307  "FPExceptions",
308  "true",
309  "Enable floating point exceptions"
310>;
311
312class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
313  "max-private-element-size-"#size,
314  "MaxPrivateElementSize",
315  !cast<string>(size),
316  "Maximum private access size may be "#size
317>;
318
319def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
320def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
321def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
322
323def FeatureEnableHugePrivateBuffer : SubtargetFeature<
324  "huge-private-buffer",
325  "EnableHugePrivateBuffer",
326  "true",
327  "Enable private/scratch buffer sizes greater than 128 GB"
328>;
329
330def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
331  "EnableVGPRSpilling",
332  "true",
333  "Enable spilling of VGPRs to scratch memory"
334>;
335
336def FeatureDumpCode : SubtargetFeature <"DumpCode",
337  "DumpCode",
338  "true",
339  "Dump MachineInstrs in the CodeEmitter"
340>;
341
342def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
343  "DumpCode",
344  "true",
345  "Dump MachineInstrs in the CodeEmitter"
346>;
347
348// XXX - This should probably be removed once enabled by default
349def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
350  "EnableLoadStoreOpt",
351  "true",
352  "Enable SI load/store optimizer pass"
353>;
354
355// Performance debugging feature. Allow using DS instruction immediate
356// offsets even if the base pointer can't be proven to be base. On SI,
357// base pointer values that won't give the same result as a 16-bit add
358// are not safe to fold, but this will override the conservative test
359// for the base pointer.
360def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
361  "unsafe-ds-offset-folding",
362  "EnableUnsafeDSOffsetFolding",
363  "true",
364  "Force using DS instruction immediate offsets on SI"
365>;
366
367def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
368  "EnableSIScheduler",
369  "true",
370  "Enable SI Machine Scheduler"
371>;
372
373def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
374  "EnableDS128",
375  "true",
376  "Use ds_{read|write}_b128"
377>;
378
379// Unless +-flat-for-global is specified, turn on FlatForGlobal for
380// all OS-es on VI and newer hardware to avoid assertion failures due
381// to missing ADDR64 variants of MUBUF instructions.
382// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
383// instructions.
384
385def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
386  "FlatForGlobal",
387  "true",
388  "Force to generate flat instruction for global"
389>;
390
391def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
392  "auto-waitcnt-before-barrier",
393  "AutoWaitcntBeforeBarrier",
394  "true",
395  "Hardware automatically inserts waitcnt before barrier"
396>;
397
398def FeatureCodeObjectV3 : SubtargetFeature <
399  "code-object-v3",
400  "CodeObjectV3",
401  "true",
402  "Generate code object version 3"
403>;
404
405def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
406  "HasTrigReducedRange",
407  "true",
408  "Requires use of fract on arguments to trig instructions"
409>;
410
411// Dummy feature used to disable assembler instructions.
412def FeatureDisable : SubtargetFeature<"",
413  "FeatureDisable","true",
414  "Dummy feature to disable assembler instructions"
415>;
416
417def FeatureGCN : SubtargetFeature<"gcn",
418  "IsGCN",
419  "true",
420  "GCN or newer GPU"
421>;
422
423class GCNSubtargetFeatureGeneration <string Value,
424                                  list<SubtargetFeature> Implies> :
425        SubtargetFeatureGeneration <Value, "GCNSubtarget", Implies>;
426
427def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
428  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
429  FeatureWavefrontSize64, FeatureGCN,
430  FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange]
431>;
432
433def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
434  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
435  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
436  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange]
437>;
438
439def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
440  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
441   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
442   FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts,
443   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
444   FeatureScalarStores, FeatureInv2PiInlineImm,
445   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
446   FeatureIntClamp, FeatureTrigReducedRange
447  ]
448>;
449
450def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
451  [FeatureFP64, FeatureLocalMemorySize65536,
452   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
453   FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts,
454   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
455   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
456   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
457   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
458   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
459   FeatureAddNoCarryInsts, FeatureScalarAtomics, FeatureR128A16
460  ]
461>;
462
463class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
464                                  list<SubtargetFeature> Implies>
465                                 : SubtargetFeature <
466  "isaver"#Major#"."#Minor#"."#Stepping,
467  "IsaVersion",
468  "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
469  "Instruction set version number",
470  Implies
471>;
472
473def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
474  [FeatureSouthernIslands,
475   FeatureFastFMAF32,
476   HalfRate64Ops,
477   FeatureLDSBankCount32,
478   FeatureCodeObjectV3]>;
479
480def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
481  [FeatureSouthernIslands,
482   FeatureLDSBankCount32,
483   FeatureCodeObjectV3]>;
484
485def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
486  [FeatureSeaIslands,
487   FeatureLDSBankCount32,
488   FeatureCodeObjectV3]>;
489
490def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
491  [FeatureSeaIslands,
492   HalfRate64Ops,
493   FeatureLDSBankCount32,
494   FeatureFastFMAF32,
495   FeatureCodeObjectV3]>;
496
497def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
498  [FeatureSeaIslands,
499   FeatureLDSBankCount16,
500   FeatureFastFMAF32,
501   FeatureCodeObjectV3]>;
502
503def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
504  [FeatureSeaIslands,
505   FeatureLDSBankCount16,
506   FeatureCodeObjectV3]>;
507
508def FeatureISAVersion7_0_4 : SubtargetFeatureISAVersion <7,0,4,
509  [FeatureSeaIslands,
510   FeatureLDSBankCount32,
511   FeatureCodeObjectV3]>;
512
513def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
514  [FeatureVolcanicIslands,
515   FeatureFastFMAF32,
516   HalfRate64Ops,
517   FeatureLDSBankCount32,
518   FeatureXNACK,
519   FeatureUnpackedD16VMem,
520   FeatureCodeObjectV3]>;
521
522def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
523  [FeatureVolcanicIslands,
524   FeatureLDSBankCount32,
525   FeatureSGPRInitBug,
526   FeatureUnpackedD16VMem,
527   FeatureCodeObjectV3]>;
528
529def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
530  [FeatureVolcanicIslands,
531   FeatureLDSBankCount32,
532   FeatureUnpackedD16VMem,
533   FeatureCodeObjectV3]>;
534
535def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
536  [FeatureVolcanicIslands,
537   FeatureLDSBankCount16,
538   FeatureXNACK,
539   FeatureCodeObjectV3]>;
540
541def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
542  [FeatureGFX9,
543   FeatureMadMixInsts,
544   FeatureLDSBankCount32,
545   FeatureD16PreservesUnusedBits,
546   FeatureCodeObjectV3]>;
547
548def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
549  [FeatureGFX9,
550   FeatureMadMixInsts,
551   FeatureLDSBankCount32,
552   FeatureXNACK,
553   FeatureD16PreservesUnusedBits,
554   FeatureCodeObjectV3]>;
555
556def FeatureISAVersion9_0_4 : SubtargetFeatureISAVersion <9,0,4,
557  [FeatureGFX9,
558   FeatureLDSBankCount32,
559   FeatureFmaMixInsts,
560   FeatureD16PreservesUnusedBits,
561   FeatureCodeObjectV3]>;
562
563def FeatureISAVersion9_0_6 : SubtargetFeatureISAVersion <9,0,6,
564  [FeatureGFX9,
565   HalfRate64Ops,
566   FeatureFmaMixInsts,
567   FeatureLDSBankCount32,
568   FeatureDLInsts,
569   FeatureCodeObjectV3]>;
570
571def FeatureISAVersion9_0_9 : SubtargetFeatureISAVersion <9,0,9,
572  [FeatureGFX9,
573   FeatureMadMixInsts,
574   FeatureLDSBankCount32,
575   FeatureXNACK,
576   FeatureD16PreservesUnusedBits]>;
577
578//===----------------------------------------------------------------------===//
579// Debugger related subtarget features.
580//===----------------------------------------------------------------------===//
581
582def FeatureDebuggerInsertNops : SubtargetFeature<
583  "amdgpu-debugger-insert-nops",
584  "DebuggerInsertNops",
585  "true",
586  "Insert one nop instruction for each high level source statement"
587>;
588
589def FeatureDebuggerEmitPrologue : SubtargetFeature<
590  "amdgpu-debugger-emit-prologue",
591  "DebuggerEmitPrologue",
592  "true",
593  "Emit debugger prologue"
594>;
595
596//===----------------------------------------------------------------------===//
597
598def AMDGPUInstrInfo : InstrInfo {
599  let guessInstructionProperties = 1;
600  let noNamedPositionallyEncodedOperands = 1;
601}
602
603def AMDGPUAsmParser : AsmParser {
604  // Some of the R600 registers have the same name, so this crashes.
605  // For example T0_XYZW and T0_XY both have the asm name T0.
606  let ShouldEmitMatchRegisterName = 0;
607}
608
609def AMDGPUAsmWriter : AsmWriter {
610  int PassSubtarget = 1;
611}
612
613def AMDGPUAsmVariants {
614  string Default = "Default";
615  int Default_ID = 0;
616  string VOP3 = "VOP3";
617  int VOP3_ID = 1;
618  string SDWA = "SDWA";
619  int SDWA_ID = 2;
620  string SDWA9 = "SDWA9";
621  int SDWA9_ID = 3;
622  string DPP = "DPP";
623  int DPP_ID = 4;
624  string Disable = "Disable";
625  int Disable_ID = 5;
626}
627
628def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
629  let Variant = AMDGPUAsmVariants.Default_ID;
630  let Name = AMDGPUAsmVariants.Default;
631}
632
633def VOP3AsmParserVariant : AsmParserVariant {
634  let Variant = AMDGPUAsmVariants.VOP3_ID;
635  let Name = AMDGPUAsmVariants.VOP3;
636}
637
638def SDWAAsmParserVariant : AsmParserVariant {
639  let Variant = AMDGPUAsmVariants.SDWA_ID;
640  let Name = AMDGPUAsmVariants.SDWA;
641}
642
643def SDWA9AsmParserVariant : AsmParserVariant {
644  let Variant = AMDGPUAsmVariants.SDWA9_ID;
645  let Name = AMDGPUAsmVariants.SDWA9;
646}
647
648
649def DPPAsmParserVariant : AsmParserVariant {
650  let Variant = AMDGPUAsmVariants.DPP_ID;
651  let Name = AMDGPUAsmVariants.DPP;
652}
653
654def AMDGPU : Target {
655  // Pull in Instruction Info:
656  let InstructionSet = AMDGPUInstrInfo;
657  let AssemblyParsers = [AMDGPUAsmParser];
658  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
659                                VOP3AsmParserVariant,
660                                SDWAAsmParserVariant,
661                                SDWA9AsmParserVariant,
662                                DPPAsmParserVariant];
663  let AssemblyWriters = [AMDGPUAsmWriter];
664  let AllowRegisterRenaming = 1;
665}
666
667// Dummy Instruction itineraries for pseudo instructions
668def ALU_NULL : FuncUnit;
669def NullALU : InstrItinClass;
670
671//===----------------------------------------------------------------------===//
672// Predicate helper class
673//===----------------------------------------------------------------------===//
674
675def isSICI : Predicate<
676  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
677  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
678>, AssemblerPredicate<"!FeatureGCN3Encoding">;
679
680def isVI : Predicate <
681  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
682  AssemblerPredicate<"FeatureGCN3Encoding">;
683
684def isGFX9 : Predicate <
685  "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
686  AssemblerPredicate<"FeatureGFX9Insts">;
687
688// TODO: Either the name to be changed or we simply use IsCI!
689def isCIVI : Predicate <
690  "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
691  AssemblerPredicate<"FeatureCIInsts">;
692
693def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
694  AssemblerPredicate<"FeatureFlatAddressSpace">;
695
696def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
697  AssemblerPredicate<"FeatureFlatGlobalInsts">;
698def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
699  AssemblerPredicate<"FeatureFlatScratchInsts">;
700def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
701  AssemblerPredicate<"FeatureGFX9Insts">;
702
703def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
704  AssemblerPredicate<"FeatureUnpackedD16VMem">;
705def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
706  AssemblerPredicate<"!FeatureUnpackedD16VMem">;
707
708def D16PreservesUnusedBits : Predicate<"Subtarget->d16PreservesUnusedBits()">,
709  AssemblerPredicate<"FeatureD16PreservesUnusedBits">;
710
711def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
712def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
713
714def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
715  AssemblerPredicate<"FeatureGFX9Insts">;
716
717def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
718  AssemblerPredicate<"FeatureAddNoCarryInsts">;
719
720def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">,
721  AssemblerPredicate<"!FeatureAddNoCarryInsts">;
722
723def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
724  AssemblerPredicate<"Feature16BitInsts">;
725def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
726  AssemblerPredicate<"FeatureVOP3P">;
727
728def NotHasVOP3PInsts : Predicate<"!Subtarget->hasVOP3PInsts()">,
729  AssemblerPredicate<"!FeatureVOP3P">;
730
731def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
732  AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
733
734def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
735  AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
736
737def HasDPP : Predicate<"Subtarget->hasDPP()">,
738  AssemblerPredicate<"FeatureDPP">;
739
740def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
741  AssemblerPredicate<"FeatureR128A16">;
742
743def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
744  AssemblerPredicate<"FeatureIntClamp">;
745
746def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
747  AssemblerPredicate<"FeatureMadMixInsts">;
748
749def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
750  AssemblerPredicate<"FeatureScalarAtomics">;
751
752def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
753def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
754def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
755                      AssemblerPredicate<"FeatureVGPRIndexMode">;
756def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
757                AssemblerPredicate<"FeatureMovrel">;
758
759def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
760  AssemblerPredicate<"FeatureFmaMixInsts">;
761
762def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
763  AssemblerPredicate<"FeatureDLInsts">;
764
765
766def EnableLateCFGStructurize : Predicate<
767  "EnableLateStructurizeCFG">;
768
769// Include AMDGPU TD files
770include "SISchedule.td"
771include "GCNProcessors.td"
772include "AMDGPUInstrInfo.td"
773include "AMDGPUIntrinsics.td"
774include "SIIntrinsics.td"
775include "AMDGPURegisterInfo.td"
776include "AMDGPURegisterBanks.td"
777include "AMDGPUInstructions.td"
778include "SIInstrInfo.td"
779include "AMDGPUCallingConv.td"
780include "AMDGPUSearchableTables.td"
781