1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21
22class BoolToList<bit Value> {
23  list<int> ret = !if(Value, [1]<int>, []<int>);
24}
25
26//===------------------------------------------------------------===//
27// Subtarget Features (device properties)
28//===------------------------------------------------------------===//
29
30def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
31  "FastFMAF32",
32  "true",
33  "Assuming f32 fma is at least as fast as mul + add"
34>;
35
36def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
37  "FastDenormalF32",
38  "true",
39  "Enabling denormals does not cause f32 instructions to run at f64 rates"
40>;
41
42def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
43  "MIMG_R128",
44  "true",
45  "Support 128-bit texture resources"
46>;
47
48def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
49  "HalfRate64Ops",
50  "true",
51  "Most fp64 instructions are half rate instead of quarter"
52>;
53
54def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
55  "FlatAddressSpace",
56  "true",
57  "Support flat address space"
58>;
59
60def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
61  "FlatInstOffsets",
62  "true",
63  "Flat instructions have immediate offset addressing mode"
64>;
65
66def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
67  "FlatGlobalInsts",
68  "true",
69  "Have global_* flat memory instructions"
70>;
71
72def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
73  "FlatScratchInsts",
74  "true",
75  "Have scratch_* flat memory instructions"
76>;
77
78def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
79  "ScalarFlatScratchInsts",
80  "true",
81  "Have s_scratch_* flat memory instructions"
82>;
83
84def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
85  "AddNoCarryInsts",
86  "true",
87  "Have VALU add/sub instructions without carry out"
88>;
89
90def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
91  "UnalignedBufferAccess",
92  "true",
93  "Hardware supports unaligned global loads and stores"
94>;
95
96def FeatureTrapHandler: SubtargetFeature<"trap-handler",
97  "TrapHandler",
98  "true",
99  "Trap handler support"
100>;
101
102def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
103  "UnalignedScratchAccess",
104  "true",
105  "Support unaligned scratch loads and stores"
106>;
107
108def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access",
109  "UnalignedDSAccess",
110  "true",
111  "Hardware supports unaligned local and region loads and stores"
112>;
113
114def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
115  "HasApertureRegs",
116  "true",
117  "Has Memory Aperture Base and Size Registers"
118>;
119
120def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
121  "HasMadMixInsts",
122  "true",
123  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
124>;
125
126def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
127  "HasFmaMixInsts",
128  "true",
129  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
130>;
131
132def FeatureDoesNotSupportXNACK : SubtargetFeature<"no-xnack-support",
133  "DoesNotSupportXNACK",
134  "true",
135  "Hardware does not support XNACK"
136>;
137
138// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
139// XNACK. The current default kernel driver setting is:
140// - graphics ring: XNACK disabled
141// - compute ring: XNACK enabled
142//
143// If XNACK is enabled, the VMEM latency can be worse.
144// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
145def FeatureXNACK : SubtargetFeature<"xnack",
146  "EnableXNACK",
147  "true",
148  "Enable XNACK support"
149>;
150
151def FeatureCuMode : SubtargetFeature<"cumode",
152  "EnableCuMode",
153  "true",
154  "Enable CU wavefront execution mode"
155>;
156
157def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
158  "SGPRInitBug",
159  "true",
160  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
161>;
162
163def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
164  "LDSMisalignedBug",
165  "true",
166  "Some GFX10 bug with misaligned multi-dword LDS access in WGP mode"
167>;
168
169def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
170  "HasMFMAInlineLiteralBug",
171  "true",
172  "MFMA cannot use inline literal as SrcC"
173>;
174
175def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
176  "HasVcmpxPermlaneHazard",
177  "true",
178  "TODO: describe me"
179>;
180
181def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
182  "HasVMEMtoScalarWriteHazard",
183  "true",
184  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
185>;
186
187def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
188  "HasSMEMtoVectorWriteHazard",
189  "true",
190  "s_load_dword followed by v_cmp page faults"
191>;
192
193def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
194  "HasInstFwdPrefetchBug",
195  "true",
196  "S_INST_PREFETCH instruction causes shader to hang"
197>;
198
199def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
200  "HasVcmpxExecWARHazard",
201  "true",
202  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
203>;
204
205def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
206  "HasLdsBranchVmemWARHazard",
207  "true",
208  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
209>;
210
211def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
212  "HasNSAtoVMEMBug",
213  "true",
214  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
215>;
216
217def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
218  "HasFlatSegmentOffsetBug",
219  "true",
220  "GFX10 bug, inst_offset ignored in flat segment"
221>;
222
223def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
224  "HasOffset3fBug",
225  "true",
226  "Branch offset of 3f hardware bug"
227>;
228
229class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
230  "ldsbankcount"#Value,
231  "LDSBankCount",
232  !cast<string>(Value),
233  "The number of LDS banks per compute unit."
234>;
235
236def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
237def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
238
239def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
240  "GCN3Encoding",
241  "true",
242  "Encoding format for VI"
243>;
244
245def FeatureCIInsts : SubtargetFeature<"ci-insts",
246  "CIInsts",
247  "true",
248  "Additional instructions for CI+"
249>;
250
251def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
252  "GFX8Insts",
253  "true",
254  "Additional instructions for GFX8+"
255>;
256
257def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
258  "GFX9Insts",
259  "true",
260  "Additional instructions for GFX9+"
261>;
262
263def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
264  "GFX10Insts",
265  "true",
266  "Additional instructions for GFX10+"
267>;
268
269def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts",
270  "GFX10_3Insts",
271  "true",
272  "Additional instructions for GFX10.3"
273>;
274
275def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
276  "GFX7GFX8GFX9Insts",
277  "true",
278  "Instructions shared in GFX7, GFX8, GFX9"
279>;
280
281def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
282  "HasSMemRealTime",
283  "true",
284  "Has s_memrealtime instruction"
285>;
286
287def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
288  "HasInv2PiInlineImm",
289  "true",
290  "Has 1 / (2 * pi) as inline immediate"
291>;
292
293def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
294  "Has16BitInsts",
295  "true",
296  "Has i16/f16 instructions"
297>;
298
299def FeatureVOP3P : SubtargetFeature<"vop3p",
300  "HasVOP3PInsts",
301  "true",
302  "Has VOP3P packed instructions"
303>;
304
305def FeatureMovrel : SubtargetFeature<"movrel",
306  "HasMovrel",
307  "true",
308  "Has v_movrel*_b32 instructions"
309>;
310
311def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
312  "HasVGPRIndexMode",
313  "true",
314  "Has VGPR mode register indexing"
315>;
316
317def FeatureScalarStores : SubtargetFeature<"scalar-stores",
318  "HasScalarStores",
319  "true",
320  "Has store scalar memory instructions"
321>;
322
323def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
324  "HasScalarAtomics",
325  "true",
326  "Has atomic scalar memory instructions"
327>;
328
329def FeatureSDWA : SubtargetFeature<"sdwa",
330  "HasSDWA",
331  "true",
332  "Support SDWA (Sub-DWORD Addressing) extension"
333>;
334
335def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
336  "HasSDWAOmod",
337  "true",
338  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
339>;
340
341def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
342  "HasSDWAScalar",
343  "true",
344  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
345>;
346
347def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
348  "HasSDWASdst",
349  "true",
350  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
351>;
352
353def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
354  "HasSDWAMac",
355  "true",
356  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
357>;
358
359def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
360  "HasSDWAOutModsVOPC",
361  "true",
362  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
363>;
364
365def FeatureDPP : SubtargetFeature<"dpp",
366  "HasDPP",
367  "true",
368  "Support DPP (Data Parallel Primitives) extension"
369>;
370
371// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
372def FeatureDPP8 : SubtargetFeature<"dpp8",
373  "HasDPP8",
374  "true",
375  "Support DPP8 (Data Parallel Primitives) extension"
376>;
377
378def FeatureR128A16 : SubtargetFeature<"r128-a16",
379  "HasR128A16",
380  "true",
381  "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
382>;
383
384def FeatureGFX10A16 : SubtargetFeature<"a16",
385  "HasGFX10A16",
386  "true",
387  "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
388>;
389
390def FeatureG16 : SubtargetFeature<"g16",
391  "HasG16",
392  "true",
393  "Support G16 for 16-bit gradient image operands"
394>;
395
396def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
397  "HasNSAEncoding",
398  "true",
399  "Support NSA encoding for image instructions"
400>;
401
402def FeatureGFX10_BEncoding : SubtargetFeature<"gfx10_b-encoding",
403  "GFX10_BEncoding",
404  "true",
405  "Encoding format GFX10_B"
406>;
407
408def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
409  "HasIntClamp",
410  "true",
411  "Support clamp for integer destination"
412>;
413
414def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
415  "HasUnpackedD16VMem",
416  "true",
417  "Has unpacked d16 vmem instructions"
418>;
419
420def FeatureDLInsts : SubtargetFeature<"dl-insts",
421  "HasDLInsts",
422  "true",
423  "Has v_fmac_f32 and v_xnor_b32 instructions"
424>;
425
426def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
427  "HasDot1Insts",
428  "true",
429  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
430>;
431
432def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
433  "HasDot2Insts",
434  "true",
435  "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
436>;
437
438def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
439  "HasDot3Insts",
440  "true",
441  "Has v_dot8c_i32_i4 instruction"
442>;
443
444def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
445  "HasDot4Insts",
446  "true",
447  "Has v_dot2c_i32_i16 instruction"
448>;
449
450def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
451  "HasDot5Insts",
452  "true",
453  "Has v_dot2c_f32_f16 instruction"
454>;
455
456def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
457  "HasDot6Insts",
458  "true",
459  "Has v_dot4c_i32_i8 instruction"
460>;
461
462def FeatureMAIInsts : SubtargetFeature<"mai-insts",
463  "HasMAIInsts",
464  "true",
465  "Has mAI instructions"
466>;
467
468def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
469  "HasPkFmacF16Inst",
470  "true",
471  "Has v_pk_fmac_f16 instruction"
472>;
473
474def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
475  "HasAtomicFaddInsts",
476  "true",
477  "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
478  "global_atomic_pk_add_f16 instructions",
479  [FeatureFlatGlobalInsts]
480>;
481
482def FeatureDoesNotSupportSRAMECC : SubtargetFeature<"no-sram-ecc-support",
483  "DoesNotSupportSRAMECC",
484  "true",
485  "Hardware does not support SRAM ECC"
486>;
487
488def FeatureSRAMECC : SubtargetFeature<"sram-ecc",
489  "EnableSRAMECC",
490  "true",
491  "Enable SRAM ECC"
492>;
493
494def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
495  "HasNoSdstCMPX",
496  "true",
497  "V_CMPX does not write VCC/SGPR in addition to EXEC"
498>;
499
500def FeatureVscnt : SubtargetFeature<"vscnt",
501  "HasVscnt",
502  "true",
503  "Has separate store vscnt counter"
504>;
505
506def FeatureGetWaveIdInst : SubtargetFeature<"get-wave-id-inst",
507  "HasGetWaveIdInst",
508  "true",
509  "Has s_get_waveid_in_workgroup instruction"
510>;
511
512def FeatureSMemTimeInst : SubtargetFeature<"s-memtime-inst",
513  "HasSMemTimeInst",
514  "true",
515  "Has s_memtime instruction"
516>;
517
518def FeatureMadMacF32Insts : SubtargetFeature<"mad-mac-f32-insts",
519  "HasMadMacF32Insts",
520  "true",
521  "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions"
522>;
523
524def FeatureDsSrc2Insts : SubtargetFeature<"ds-src2-insts",
525  "HasDsSrc2Insts",
526  "true",
527  "Has ds_*_src2 instructions"
528>;
529
530def FeatureRegisterBanking : SubtargetFeature<"register-banking",
531  "HasRegisterBanking",
532  "true",
533  "Has register banking"
534>;
535
536def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
537  "HasVOP3Literal",
538  "true",
539  "Can use one literal in VOP3"
540>;
541
542def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
543  "HasNoDataDepHazard",
544  "true",
545  "Does not need SW waitstates"
546>;
547
548//===------------------------------------------------------------===//
549// Subtarget Features (options and debugging)
550//===------------------------------------------------------------===//
551
552class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
553  "max-private-element-size-"#size,
554  "MaxPrivateElementSize",
555  !cast<string>(size),
556  "Maximum private access size may be "#size
557>;
558
559def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
560def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
561def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
562
563def FeatureDumpCode : SubtargetFeature <"DumpCode",
564  "DumpCode",
565  "true",
566  "Dump MachineInstrs in the CodeEmitter"
567>;
568
569def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
570  "DumpCode",
571  "true",
572  "Dump MachineInstrs in the CodeEmitter"
573>;
574
575// XXX - This should probably be removed once enabled by default
576def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
577  "EnableLoadStoreOpt",
578  "true",
579  "Enable SI load/store optimizer pass"
580>;
581
582// Performance debugging feature. Allow using DS instruction immediate
583// offsets even if the base pointer can't be proven to be base. On SI,
584// base pointer values that won't give the same result as a 16-bit add
585// are not safe to fold, but this will override the conservative test
586// for the base pointer.
587def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
588  "unsafe-ds-offset-folding",
589  "EnableUnsafeDSOffsetFolding",
590  "true",
591  "Force using DS instruction immediate offsets on SI"
592>;
593
594def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
595  "EnableSIScheduler",
596  "true",
597  "Enable SI Machine Scheduler"
598>;
599
600def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
601  "EnableDS128",
602  "true",
603  "Use ds_{read|write}_b128"
604>;
605
606// Sparse texture support requires that all result registers are zeroed when
607// PRTStrictNull is set to true. This feature is turned on for all architectures
608// but is enabled as a feature in case there are situations where PRTStrictNull
609// is disabled by the driver.
610def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
611  "EnablePRTStrictNull",
612  "true",
613  "Enable zeroing of result registers for sparse texture fetches"
614>;
615
616// Unless +-flat-for-global is specified, turn on FlatForGlobal for
617// all OS-es on VI and newer hardware to avoid assertion failures due
618// to missing ADDR64 variants of MUBUF instructions.
619// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
620// instructions.
621
622def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
623  "FlatForGlobal",
624  "true",
625  "Force to generate flat instruction for global"
626>;
627
628def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
629  "auto-waitcnt-before-barrier",
630  "AutoWaitcntBeforeBarrier",
631  "true",
632  "Hardware automatically inserts waitcnt before barrier"
633>;
634
635def FeatureCodeObjectV3 : SubtargetFeature <
636  "code-object-v3",
637  "CodeObjectV3",
638  "true",
639  "Generate code object version 3"
640>;
641
642def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
643  "HasTrigReducedRange",
644  "true",
645  "Requires use of fract on arguments to trig instructions"
646>;
647
648// Alignment enforcement is controlled by a configuration register:
649// SH_MEM_CONFIG.alignment_mode
650def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode",
651  "UnalignedAccessMode",
652  "true",
653  "Enable unaligned global, local and region loads and stores if the hardware"
654  " supports it"
655>;
656
657// Dummy feature used to disable assembler instructions.
658def FeatureDisable : SubtargetFeature<"",
659  "FeatureDisable","true",
660  "Dummy feature to disable assembler instructions"
661>;
662
663class GCNSubtargetFeatureGeneration <string Value,
664                                     string FeatureName,
665                                     list<SubtargetFeature> Implies> :
666        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
667
668def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
669    "southern-islands",
670  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
671  FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,
672  FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
673  FeatureTrigReducedRange, FeatureDoesNotSupportSRAMECC,
674  FeatureDoesNotSupportXNACK]
675>;
676
677def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
678    "sea-islands",
679  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
680  FeatureWavefrontSize64, FeatureFlatAddressSpace,
681  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
682  FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
683  FeatureDsSrc2Insts, FeatureDoesNotSupportSRAMECC,
684  FeatureUnalignedBufferAccess]
685>;
686
687def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
688  "volcanic-islands",
689  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
690   FeatureWavefrontSize64, FeatureFlatAddressSpace,
691   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
692   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
693   FeatureScalarStores, FeatureInv2PiInlineImm,
694   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
695   FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
696   FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
697   FeatureDsSrc2Insts, FeatureDoesNotSupportSRAMECC, FeatureFastDenormalF32,
698   FeatureUnalignedBufferAccess
699  ]
700>;
701
702def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
703  "gfx9",
704  [FeatureFP64, FeatureLocalMemorySize65536,
705   FeatureWavefrontSize64, FeatureFlatAddressSpace,
706   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
707   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
708   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
709   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
710   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
711   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
712   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
713   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
714   FeatureSMemTimeInst, FeatureMadMacF32Insts, FeatureDsSrc2Insts,
715   FeatureFastDenormalF32, FeatureUnalignedBufferAccess,
716   FeatureUnalignedDSAccess
717  ]
718>;
719
720def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
721  "gfx10",
722  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
723   FeatureFlatAddressSpace,
724   FeatureCIInsts, Feature16BitInsts,
725   FeatureSMemRealTime, FeatureInv2PiInlineImm,
726   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
727   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
728   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
729   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
730   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
731   FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
732   FeatureVOP3Literal, FeatureDPP8,
733   FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureDoesNotSupportSRAMECC,
734   FeatureGFX10A16, FeatureFastDenormalF32, FeatureG16,
735   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess
736  ]
737>;
738
739class FeatureSet<list<SubtargetFeature> Features_> {
740  list<SubtargetFeature> Features = Features_;
741}
742
743def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
744   FeatureFastFMAF32,
745   HalfRate64Ops,
746   FeatureLDSBankCount32,
747   FeatureDoesNotSupportXNACK,
748   FeatureCodeObjectV3]>;
749
750def FeatureISAVersion6_0_1 : FeatureSet<
751  [FeatureSouthernIslands,
752   FeatureLDSBankCount32,
753   FeatureDoesNotSupportXNACK,
754   FeatureCodeObjectV3]>;
755
756def FeatureISAVersion7_0_0 : FeatureSet<
757  [FeatureSeaIslands,
758   FeatureLDSBankCount32,
759   FeatureDoesNotSupportXNACK,
760   FeatureCodeObjectV3]>;
761
762def FeatureISAVersion7_0_1 : FeatureSet<
763  [FeatureSeaIslands,
764   HalfRate64Ops,
765   FeatureLDSBankCount32,
766   FeatureFastFMAF32,
767   FeatureDoesNotSupportXNACK,
768   FeatureCodeObjectV3]>;
769
770def FeatureISAVersion7_0_2 : FeatureSet<
771  [FeatureSeaIslands,
772   FeatureLDSBankCount16,
773   FeatureFastFMAF32,
774   FeatureDoesNotSupportXNACK,
775   FeatureCodeObjectV3]>;
776
777def FeatureISAVersion7_0_3 : FeatureSet<
778  [FeatureSeaIslands,
779   FeatureLDSBankCount16,
780   FeatureDoesNotSupportXNACK,
781   FeatureCodeObjectV3]>;
782
783def FeatureISAVersion7_0_4 : FeatureSet<
784  [FeatureSeaIslands,
785   FeatureLDSBankCount32,
786   FeatureDoesNotSupportXNACK,
787   FeatureCodeObjectV3]>;
788
789def FeatureISAVersion8_0_1 : FeatureSet<
790  [FeatureVolcanicIslands,
791   FeatureFastFMAF32,
792   HalfRate64Ops,
793   FeatureLDSBankCount32,
794   FeatureXNACK,
795   FeatureUnpackedD16VMem,
796   FeatureCodeObjectV3]>;
797
798def FeatureISAVersion8_0_2 : FeatureSet<
799  [FeatureVolcanicIslands,
800   FeatureLDSBankCount32,
801   FeatureSGPRInitBug,
802   FeatureUnpackedD16VMem,
803   FeatureDoesNotSupportXNACK,
804   FeatureCodeObjectV3]>;
805
806def FeatureISAVersion8_0_3 : FeatureSet<
807  [FeatureVolcanicIslands,
808   FeatureLDSBankCount32,
809   FeatureUnpackedD16VMem,
810   FeatureDoesNotSupportXNACK,
811   FeatureCodeObjectV3]>;
812
813def FeatureISAVersion8_1_0 : FeatureSet<
814  [FeatureVolcanicIslands,
815   FeatureLDSBankCount16,
816   FeatureXNACK,
817   FeatureCodeObjectV3]>;
818
819def FeatureISAVersion9_0_0 : FeatureSet<
820  [FeatureGFX9,
821   FeatureMadMixInsts,
822   FeatureLDSBankCount32,
823   FeatureCodeObjectV3,
824   FeatureDoesNotSupportXNACK,
825   FeatureDoesNotSupportSRAMECC]>;
826
827def FeatureISAVersion9_0_2 : FeatureSet<
828  [FeatureGFX9,
829   FeatureMadMixInsts,
830   FeatureLDSBankCount32,
831   FeatureXNACK,
832   FeatureDoesNotSupportSRAMECC,
833   FeatureCodeObjectV3]>;
834
835def FeatureISAVersion9_0_4 : FeatureSet<
836  [FeatureGFX9,
837   FeatureLDSBankCount32,
838   FeatureFmaMixInsts,
839   FeatureDoesNotSupportXNACK,
840   FeatureDoesNotSupportSRAMECC,
841   FeatureCodeObjectV3]>;
842
843def FeatureISAVersion9_0_6 : FeatureSet<
844  [FeatureGFX9,
845   HalfRate64Ops,
846   FeatureFmaMixInsts,
847   FeatureLDSBankCount32,
848   FeatureDLInsts,
849   FeatureDot1Insts,
850   FeatureDot2Insts,
851   FeatureDoesNotSupportXNACK,
852   FeatureCodeObjectV3]>;
853
854def FeatureISAVersion9_0_8 : FeatureSet<
855  [FeatureGFX9,
856   HalfRate64Ops,
857   FeatureFmaMixInsts,
858   FeatureLDSBankCount32,
859   FeatureDLInsts,
860   FeatureDot1Insts,
861   FeatureDot2Insts,
862   FeatureDot3Insts,
863   FeatureDot4Insts,
864   FeatureDot5Insts,
865   FeatureDot6Insts,
866   FeatureMAIInsts,
867   FeaturePkFmacF16Inst,
868   FeatureAtomicFaddInsts,
869   FeatureSRAMECC,
870   FeatureMFMAInlineLiteralBug,
871   FeatureCodeObjectV3]>;
872
873def FeatureISAVersion9_0_9 : FeatureSet<
874  [FeatureGFX9,
875   FeatureMadMixInsts,
876   FeatureLDSBankCount32,
877   FeatureXNACK,
878   FeatureCodeObjectV3]>;
879
880// TODO: Organize more features into groups.
881def FeatureGroup {
882  // Bugs present on gfx10.1.
883  list<SubtargetFeature> GFX10_1_Bugs = [
884    FeatureVcmpxPermlaneHazard,
885    FeatureVMEMtoScalarWriteHazard,
886    FeatureSMEMtoVectorWriteHazard,
887    FeatureInstFwdPrefetchBug,
888    FeatureVcmpxExecWARHazard,
889    FeatureLdsBranchVmemWARHazard,
890    FeatureNSAtoVMEMBug,
891    FeatureOffset3fBug,
892    FeatureFlatSegmentOffsetBug
893   ];
894}
895
896def FeatureISAVersion10_1_0 : FeatureSet<
897  !listconcat(FeatureGroup.GFX10_1_Bugs,
898    [FeatureGFX10,
899     FeatureLDSBankCount32,
900     FeatureDLInsts,
901     FeatureNSAEncoding,
902     FeatureWavefrontSize32,
903     FeatureScalarStores,
904     FeatureScalarAtomics,
905     FeatureScalarFlatScratchInsts,
906     FeatureGetWaveIdInst,
907     FeatureSMemTimeInst,
908     FeatureMadMacF32Insts,
909     FeatureDsSrc2Insts,
910     FeatureLdsMisalignedBug,
911     FeatureDoesNotSupportXNACK,
912     FeatureCodeObjectV3])>;
913
914def FeatureISAVersion10_1_1 : FeatureSet<
915  !listconcat(FeatureGroup.GFX10_1_Bugs,
916    [FeatureGFX10,
917     FeatureLDSBankCount32,
918     FeatureDLInsts,
919     FeatureDot1Insts,
920     FeatureDot2Insts,
921     FeatureDot5Insts,
922     FeatureDot6Insts,
923     FeatureNSAEncoding,
924     FeatureWavefrontSize32,
925     FeatureScalarStores,
926     FeatureScalarAtomics,
927     FeatureScalarFlatScratchInsts,
928     FeatureGetWaveIdInst,
929     FeatureSMemTimeInst,
930     FeatureMadMacF32Insts,
931     FeatureDsSrc2Insts,
932     FeatureDoesNotSupportXNACK,
933     FeatureCodeObjectV3])>;
934
935def FeatureISAVersion10_1_2 : FeatureSet<
936  !listconcat(FeatureGroup.GFX10_1_Bugs,
937    [FeatureGFX10,
938     FeatureLDSBankCount32,
939     FeatureDLInsts,
940     FeatureDot1Insts,
941     FeatureDot2Insts,
942     FeatureDot5Insts,
943     FeatureDot6Insts,
944     FeatureNSAEncoding,
945     FeatureWavefrontSize32,
946     FeatureScalarStores,
947     FeatureScalarAtomics,
948     FeatureScalarFlatScratchInsts,
949     FeatureGetWaveIdInst,
950     FeatureSMemTimeInst,
951     FeatureMadMacF32Insts,
952     FeatureDsSrc2Insts,
953     FeatureLdsMisalignedBug,
954     FeatureDoesNotSupportXNACK,
955     FeatureCodeObjectV3])>;
956
957def FeatureISAVersion10_3_0 : FeatureSet<
958  [FeatureGFX10,
959   FeatureGFX10_BEncoding,
960   FeatureGFX10_3Insts,
961   FeatureLDSBankCount32,
962   FeatureDLInsts,
963   FeatureDot1Insts,
964   FeatureDot2Insts,
965   FeatureDot5Insts,
966   FeatureDot6Insts,
967   FeatureNSAEncoding,
968   FeatureWavefrontSize32,
969   FeatureDoesNotSupportXNACK,
970   FeatureCodeObjectV3]>;
971
972//===----------------------------------------------------------------------===//
973
974def AMDGPUInstrInfo : InstrInfo {
975  let guessInstructionProperties = 1;
976  let noNamedPositionallyEncodedOperands = 1;
977}
978
979def AMDGPUAsmParser : AsmParser {
980  // Some of the R600 registers have the same name, so this crashes.
981  // For example T0_XYZW and T0_XY both have the asm name T0.
982  let ShouldEmitMatchRegisterName = 0;
983}
984
985def AMDGPUAsmWriter : AsmWriter {
986  int PassSubtarget = 1;
987}
988
989def AMDGPUAsmVariants {
990  string Default = "Default";
991  int Default_ID = 0;
992  string VOP3 = "VOP3";
993  int VOP3_ID = 1;
994  string SDWA = "SDWA";
995  int SDWA_ID = 2;
996  string SDWA9 = "SDWA9";
997  int SDWA9_ID = 3;
998  string DPP = "DPP";
999  int DPP_ID = 4;
1000  string Disable = "Disable";
1001  int Disable_ID = 5;
1002}
1003
1004def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
1005  let Variant = AMDGPUAsmVariants.Default_ID;
1006  let Name = AMDGPUAsmVariants.Default;
1007}
1008
1009def VOP3AsmParserVariant : AsmParserVariant {
1010  let Variant = AMDGPUAsmVariants.VOP3_ID;
1011  let Name = AMDGPUAsmVariants.VOP3;
1012}
1013
1014def SDWAAsmParserVariant : AsmParserVariant {
1015  let Variant = AMDGPUAsmVariants.SDWA_ID;
1016  let Name = AMDGPUAsmVariants.SDWA;
1017}
1018
1019def SDWA9AsmParserVariant : AsmParserVariant {
1020  let Variant = AMDGPUAsmVariants.SDWA9_ID;
1021  let Name = AMDGPUAsmVariants.SDWA9;
1022}
1023
1024
1025def DPPAsmParserVariant : AsmParserVariant {
1026  let Variant = AMDGPUAsmVariants.DPP_ID;
1027  let Name = AMDGPUAsmVariants.DPP;
1028}
1029
1030def AMDGPU : Target {
1031  // Pull in Instruction Info:
1032  let InstructionSet = AMDGPUInstrInfo;
1033  let AssemblyParsers = [AMDGPUAsmParser];
1034  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
1035                                VOP3AsmParserVariant,
1036                                SDWAAsmParserVariant,
1037                                SDWA9AsmParserVariant,
1038                                DPPAsmParserVariant];
1039  let AssemblyWriters = [AMDGPUAsmWriter];
1040  let AllowRegisterRenaming = 1;
1041}
1042
1043// Dummy Instruction itineraries for pseudo instructions
1044def ALU_NULL : FuncUnit;
1045def NullALU : InstrItinClass;
1046
1047//===----------------------------------------------------------------------===//
1048// Predicate helper class
1049//===----------------------------------------------------------------------===//
1050
1051def isGFX6 :
1052  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1053  AssemblerPredicate<(all_of FeatureSouthernIslands)>;
1054
1055def isGFX6GFX7 :
1056  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1057            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1058  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
1059
1060def isGFX6GFX7GFX10 :
1061  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1062            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1063            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1064  AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
1065
1066def isGFX7Only :
1067  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1068  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
1069
1070def isGFX7GFX10 :
1071  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1072            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1073  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
1074
1075def isGFX7GFX8 :
1076  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1077            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1078  AssemblerPredicate<(all_of FeatureSouthernIslands, FeatureCIInsts)>;
1079
1080def isGFX7GFX8GFX9 :
1081  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1082            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1083            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1084  AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
1085
1086def isGFX6GFX7GFX8GFX9 :
1087  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1088            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1089            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1090            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1091  AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
1092
1093def isGFX7Plus :
1094  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1095  AssemblerPredicate<(all_of FeatureCIInsts)>;
1096
1097def isGFX8Plus :
1098  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1099  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1100
1101def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1102                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1103  AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1104
1105def isGFX9Plus :
1106  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1107  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1108
1109def isGFX9Only : Predicate <
1110  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1111  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1112
1113def isGFX8GFX9 :
1114  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1115            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1116  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1117
1118def isGFX10Plus :
1119  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1120  AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1121
1122def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1123  AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1124
1125def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1126  AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1127def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1128  AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1129def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1130  AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1131def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1132  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1133
1134def HasGFX10_BEncoding : Predicate<"Subtarget->hasGFX10_BEncoding()">,
1135  AssemblerPredicate<(all_of FeatureGFX10_BEncoding)>;
1136
1137def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1138  AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1139def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1140  AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1141
1142def D16PreservesUnusedBits :
1143  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1144  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1145
1146def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1147def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1148
1149def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1150  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1151
1152def HasLDSFPAtomics : Predicate<"Subtarget->hasLDSFPAtomics()">,
1153  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1154
1155def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1156  AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1157
1158def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1159
1160def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1161  AssemblerPredicate<(all_of Feature16BitInsts)>;
1162def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1163  AssemblerPredicate<(all_of FeatureVOP3P)>;
1164
1165def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
1166def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
1167
1168def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1169  AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1170
1171def HasSDWA9 :
1172  Predicate<"Subtarget->hasSDWA()">,
1173  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1174
1175def HasSDWA10 :
1176  Predicate<"Subtarget->hasSDWA()">,
1177  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1178
1179def HasDPP : Predicate<"Subtarget->hasDPP()">,
1180  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1181
1182def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1183  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1184
1185def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1186  AssemblerPredicate<(all_of FeatureR128A16)>;
1187
1188def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1189  AssemblerPredicate<(all_of FeatureGFX10A16)>;
1190
1191def HasG16 : Predicate<"Subtarget->hasG16()">,
1192  AssemblerPredicate<(all_of FeatureG16)>;
1193
1194def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1195  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1196
1197def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1198  AssemblerPredicate<(all_of FeatureIntClamp)>;
1199
1200def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1201  AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1202
1203def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1204  AssemblerPredicate<(all_of FeatureScalarStores)>;
1205
1206def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1207  AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1208
1209def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1210  AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1211
1212def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1213  AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1214
1215def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1216def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1217def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1218                      AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1219def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1220                AssemblerPredicate<(all_of FeatureMovrel)>;
1221
1222def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1223  AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1224
1225def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1226  AssemblerPredicate<(all_of FeatureDLInsts)>;
1227
1228def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1229  AssemblerPredicate<(all_of FeatureDot1Insts)>;
1230
1231def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1232  AssemblerPredicate<(all_of FeatureDot2Insts)>;
1233
1234def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1235  AssemblerPredicate<(all_of FeatureDot3Insts)>;
1236
1237def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1238  AssemblerPredicate<(all_of FeatureDot4Insts)>;
1239
1240def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1241  AssemblerPredicate<(all_of FeatureDot5Insts)>;
1242
1243def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1244  AssemblerPredicate<(all_of FeatureDot6Insts)>;
1245
1246def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">,
1247  AssemblerPredicate<(all_of FeatureGetWaveIdInst)>;
1248
1249def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1250  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1251
1252def HasSMemTimeInst : Predicate<"Subtarget->hasSMemTimeInst()">,
1253  AssemblerPredicate<(all_of FeatureSMemTimeInst)>;
1254
1255def HasNoSMemTimeInst : Predicate<"!Subtarget->hasSMemTimeInst()">;
1256
1257def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1258  AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1259
1260def HasMadMacF32Insts : Predicate<"Subtarget->hasMadMacF32Insts()">,
1261  AssemblerPredicate<(all_of FeatureMadMacF32Insts)>;
1262
1263def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1264  AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>;
1265
1266def HasNoMadMacF32Insts : Predicate<"!Subtarget->hasMadMacF32Insts()">,
1267  AssemblerPredicate<(all_of (not FeatureMadMacF32Insts))>;
1268
1269def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
1270  AssemblerPredicate<(all_of FeatureDsSrc2Insts)>;
1271
1272def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">,
1273  AssemblerPredicate<(all_of FeatureOffset3fBug)>;
1274
1275def EnableLateCFGStructurize : Predicate<
1276  "EnableLateStructurizeCFG">;
1277
1278// Include AMDGPU TD files
1279include "SISchedule.td"
1280include "GCNProcessors.td"
1281include "AMDGPUInstrInfo.td"
1282include "SIRegisterInfo.td"
1283include "AMDGPURegisterBanks.td"
1284include "AMDGPUInstructions.td"
1285include "SIInstrInfo.td"
1286include "AMDGPUCallingConv.td"
1287include "AMDGPUSearchableTables.td"
1288