1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21
22class BoolToList<bit Value> {
23  list<int> ret = !if(Value, [1]<int>, []<int>);
24}
25
26//===------------------------------------------------------------===//
27// Subtarget Features (device properties)
28//===------------------------------------------------------------===//
29
30def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
31  "FastFMAF32",
32  "true",
33  "Assuming f32 fma is at least as fast as mul + add"
34>;
35
36def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
37  "FastDenormalF32",
38  "true",
39  "Enabling denormals does not cause f32 instructions to run at f64 rates"
40>;
41
42def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
43  "MIMG_R128",
44  "true",
45  "Support 128-bit texture resources"
46>;
47
48def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
49  "HalfRate64Ops",
50  "true",
51  "Most fp64 instructions are half rate instead of quarter"
52>;
53
54def FullRate64Ops : SubtargetFeature<"full-rate-64-ops",
55  "FullRate64Ops",
56  "true",
57  "Most fp64 instructions are full rate"
58>;
59
60def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
61  "FlatAddressSpace",
62  "true",
63  "Support flat address space"
64>;
65
66def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
67  "FlatInstOffsets",
68  "true",
69  "Flat instructions have immediate offset addressing mode"
70>;
71
72def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
73  "FlatGlobalInsts",
74  "true",
75  "Have global_* flat memory instructions"
76>;
77
78def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
79  "FlatScratchInsts",
80  "true",
81  "Have scratch_* flat memory instructions"
82>;
83
84def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
85  "ScalarFlatScratchInsts",
86  "true",
87  "Have s_scratch_* flat memory instructions"
88>;
89
90def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
91  "AddNoCarryInsts",
92  "true",
93  "Have VALU add/sub instructions without carry out"
94>;
95
96def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
97  "UnalignedBufferAccess",
98  "true",
99  "Hardware supports unaligned global loads and stores"
100>;
101
102def FeatureTrapHandler: SubtargetFeature<"trap-handler",
103  "TrapHandler",
104  "true",
105  "Trap handler support"
106>;
107
108def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
109  "UnalignedScratchAccess",
110  "true",
111  "Support unaligned scratch loads and stores"
112>;
113
114def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access",
115  "UnalignedDSAccess",
116  "true",
117  "Hardware supports unaligned local and region loads and stores"
118>;
119
120def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
121  "HasApertureRegs",
122  "true",
123  "Has Memory Aperture Base and Size Registers"
124>;
125
126def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
127  "HasMadMixInsts",
128  "true",
129  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
130>;
131
132def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
133  "HasFmaMixInsts",
134  "true",
135  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
136>;
137
138def FeatureSupportsXNACK : SubtargetFeature<"xnack-support",
139  "SupportsXNACK",
140  "true",
141  "Hardware supports XNACK"
142>;
143
144// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
145// XNACK. The current default kernel driver setting is:
146// - graphics ring: XNACK disabled
147// - compute ring: XNACK enabled
148//
149// If XNACK is enabled, the VMEM latency can be worse.
150// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
151def FeatureXNACK : SubtargetFeature<"xnack",
152  "EnableXNACK",
153  "true",
154  "Enable XNACK support"
155>;
156
157def FeatureTgSplit : SubtargetFeature<"tgsplit",
158  "EnableTgSplit",
159  "true",
160  "Enable threadgroup split execution"
161>;
162
163def FeatureCuMode : SubtargetFeature<"cumode",
164  "EnableCuMode",
165  "true",
166  "Enable CU wavefront execution mode"
167>;
168
169def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
170  "SGPRInitBug",
171  "true",
172  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
173>;
174
175def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
176  "LDSMisalignedBug",
177  "true",
178  "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode"
179>;
180
181def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
182  "HasMFMAInlineLiteralBug",
183  "true",
184  "MFMA cannot use inline literal as SrcC"
185>;
186
187def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
188  "HasVcmpxPermlaneHazard",
189  "true",
190  "TODO: describe me"
191>;
192
193def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
194  "HasVMEMtoScalarWriteHazard",
195  "true",
196  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
197>;
198
199def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
200  "HasSMEMtoVectorWriteHazard",
201  "true",
202  "s_load_dword followed by v_cmp page faults"
203>;
204
205def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
206  "HasInstFwdPrefetchBug",
207  "true",
208  "S_INST_PREFETCH instruction causes shader to hang"
209>;
210
211def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
212  "HasVcmpxExecWARHazard",
213  "true",
214  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
215>;
216
217def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
218  "HasLdsBranchVmemWARHazard",
219  "true",
220  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
221>;
222
223def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
224  "HasNSAtoVMEMBug",
225  "true",
226  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
227>;
228
229def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
230  "HasFlatSegmentOffsetBug",
231  "true",
232  "GFX10 bug, inst_offset ignored in flat segment"
233>;
234
235def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
236  "HasOffset3fBug",
237  "true",
238  "Branch offset of 3f hardware bug"
239>;
240
241def FeatureImageStoreD16Bug : SubtargetFeature<"image-store-d16-bug",
242  "HasImageStoreD16Bug",
243  "true",
244  "Image Store D16 hardware bug"
245>;
246
247def FeatureImageGather4D16Bug : SubtargetFeature<"image-gather4-d16-bug",
248  "HasImageGather4D16Bug",
249  "true",
250  "Image Gather4 D16 hardware bug"
251>;
252
253class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
254  "ldsbankcount"#Value,
255  "LDSBankCount",
256  !cast<string>(Value),
257  "The number of LDS banks per compute unit."
258>;
259
260def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
261def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
262
263def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
264  "GCN3Encoding",
265  "true",
266  "Encoding format for VI"
267>;
268
269def FeatureCIInsts : SubtargetFeature<"ci-insts",
270  "CIInsts",
271  "true",
272  "Additional instructions for CI+"
273>;
274
275def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
276  "GFX8Insts",
277  "true",
278  "Additional instructions for GFX8+"
279>;
280
281def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
282  "GFX9Insts",
283  "true",
284  "Additional instructions for GFX9+"
285>;
286
287def FeatureGFX90AInsts : SubtargetFeature<"gfx90a-insts",
288  "GFX90AInsts",
289  "true",
290  "Additional instructions for GFX90A+"
291>;
292
293def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
294  "GFX10Insts",
295  "true",
296  "Additional instructions for GFX10+"
297>;
298
299def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts",
300  "GFX10_3Insts",
301  "true",
302  "Additional instructions for GFX10.3"
303>;
304
305def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
306  "GFX7GFX8GFX9Insts",
307  "true",
308  "Instructions shared in GFX7, GFX8, GFX9"
309>;
310
311def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
312  "HasSMemRealTime",
313  "true",
314  "Has s_memrealtime instruction"
315>;
316
317def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
318  "HasInv2PiInlineImm",
319  "true",
320  "Has 1 / (2 * pi) as inline immediate"
321>;
322
323def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
324  "Has16BitInsts",
325  "true",
326  "Has i16/f16 instructions"
327>;
328
329def FeatureVOP3P : SubtargetFeature<"vop3p",
330  "HasVOP3PInsts",
331  "true",
332  "Has VOP3P packed instructions"
333>;
334
335def FeatureMovrel : SubtargetFeature<"movrel",
336  "HasMovrel",
337  "true",
338  "Has v_movrel*_b32 instructions"
339>;
340
341def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
342  "HasVGPRIndexMode",
343  "true",
344  "Has VGPR mode register indexing"
345>;
346
347def FeatureScalarStores : SubtargetFeature<"scalar-stores",
348  "HasScalarStores",
349  "true",
350  "Has store scalar memory instructions"
351>;
352
353def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
354  "HasScalarAtomics",
355  "true",
356  "Has atomic scalar memory instructions"
357>;
358
359def FeatureSDWA : SubtargetFeature<"sdwa",
360  "HasSDWA",
361  "true",
362  "Support SDWA (Sub-DWORD Addressing) extension"
363>;
364
365def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
366  "HasSDWAOmod",
367  "true",
368  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
369>;
370
371def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
372  "HasSDWAScalar",
373  "true",
374  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
375>;
376
377def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
378  "HasSDWASdst",
379  "true",
380  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
381>;
382
383def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
384  "HasSDWAMac",
385  "true",
386  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
387>;
388
389def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
390  "HasSDWAOutModsVOPC",
391  "true",
392  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
393>;
394
395def FeatureDPP : SubtargetFeature<"dpp",
396  "HasDPP",
397  "true",
398  "Support DPP (Data Parallel Primitives) extension"
399>;
400
401// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
402def FeatureDPP8 : SubtargetFeature<"dpp8",
403  "HasDPP8",
404  "true",
405  "Support DPP8 (Data Parallel Primitives) extension"
406>;
407
408def Feature64BitDPP : SubtargetFeature<"dpp-64bit",
409  "Has64BitDPP",
410  "true",
411  "Support DPP (Data Parallel Primitives) extension"
412>;
413
414def FeaturePackedFP32Ops : SubtargetFeature<"packed-fp32-ops",
415  "HasPackedFP32Ops",
416  "true",
417  "Support packed fp32 instructions"
418>;
419
420def FeatureR128A16 : SubtargetFeature<"r128-a16",
421  "HasR128A16",
422  "true",
423  "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
424>;
425
426def FeatureGFX10A16 : SubtargetFeature<"a16",
427  "HasGFX10A16",
428  "true",
429  "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
430>;
431
432def FeatureG16 : SubtargetFeature<"g16",
433  "HasG16",
434  "true",
435  "Support G16 for 16-bit gradient image operands"
436>;
437
438def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
439  "HasNSAEncoding",
440  "true",
441  "Support NSA encoding for image instructions"
442>;
443
444def FeatureExtendedImageInsts : SubtargetFeature<"extended-image-insts",
445  "HasExtendedImageInsts",
446  "true",
447  "Support mips != 0, lod != 0, gather4, and get_lod"
448>;
449
450def FeatureGFX10_BEncoding : SubtargetFeature<"gfx10_b-encoding",
451  "GFX10_BEncoding",
452  "true",
453  "Encoding format GFX10_B"
454>;
455
456def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
457  "HasIntClamp",
458  "true",
459  "Support clamp for integer destination"
460>;
461
462def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
463  "HasUnpackedD16VMem",
464  "true",
465  "Has unpacked d16 vmem instructions"
466>;
467
468def FeatureDLInsts : SubtargetFeature<"dl-insts",
469  "HasDLInsts",
470  "true",
471  "Has v_fmac_f32 and v_xnor_b32 instructions"
472>;
473
474def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
475  "HasDot1Insts",
476  "true",
477  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
478>;
479
480def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
481  "HasDot2Insts",
482  "true",
483  "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
484>;
485
486def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
487  "HasDot3Insts",
488  "true",
489  "Has v_dot8c_i32_i4 instruction"
490>;
491
492def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
493  "HasDot4Insts",
494  "true",
495  "Has v_dot2c_i32_i16 instruction"
496>;
497
498def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
499  "HasDot5Insts",
500  "true",
501  "Has v_dot2c_f32_f16 instruction"
502>;
503
504def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
505  "HasDot6Insts",
506  "true",
507  "Has v_dot4c_i32_i8 instruction"
508>;
509
510def FeatureMAIInsts : SubtargetFeature<"mai-insts",
511  "HasMAIInsts",
512  "true",
513  "Has mAI instructions"
514>;
515
516def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
517  "HasPkFmacF16Inst",
518  "true",
519  "Has v_pk_fmac_f16 instruction"
520>;
521
522def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
523  "HasAtomicFaddInsts",
524  "true",
525  "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
526  "global_atomic_pk_add_f16 instructions",
527  [FeatureFlatGlobalInsts]
528>;
529
530def FeatureSupportsSRAMECC : SubtargetFeature<"sramecc-support",
531  "SupportsSRAMECC",
532  "true",
533  "Hardware supports SRAMECC"
534>;
535
536def FeatureSRAMECC : SubtargetFeature<"sramecc",
537  "EnableSRAMECC",
538  "true",
539  "Enable SRAMECC"
540>;
541
542def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
543  "HasNoSdstCMPX",
544  "true",
545  "V_CMPX does not write VCC/SGPR in addition to EXEC"
546>;
547
548def FeatureVscnt : SubtargetFeature<"vscnt",
549  "HasVscnt",
550  "true",
551  "Has separate store vscnt counter"
552>;
553
554def FeatureGetWaveIdInst : SubtargetFeature<"get-wave-id-inst",
555  "HasGetWaveIdInst",
556  "true",
557  "Has s_get_waveid_in_workgroup instruction"
558>;
559
560def FeatureSMemTimeInst : SubtargetFeature<"s-memtime-inst",
561  "HasSMemTimeInst",
562  "true",
563  "Has s_memtime instruction"
564>;
565
566def FeatureShaderCyclesRegister : SubtargetFeature<"shader-cycles-register",
567  "HasShaderCyclesRegister",
568  "true",
569  "Has SHADER_CYCLES hardware register"
570>;
571
572def FeatureMadMacF32Insts : SubtargetFeature<"mad-mac-f32-insts",
573  "HasMadMacF32Insts",
574  "true",
575  "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions"
576>;
577
578def FeatureDsSrc2Insts : SubtargetFeature<"ds-src2-insts",
579  "HasDsSrc2Insts",
580  "true",
581  "Has ds_*_src2 instructions"
582>;
583
584def FeatureRegisterBanking : SubtargetFeature<"register-banking",
585  "HasRegisterBanking",
586  "true",
587  "Has register banking"
588>;
589
590def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
591  "HasVOP3Literal",
592  "true",
593  "Can use one literal in VOP3"
594>;
595
596def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
597  "HasNoDataDepHazard",
598  "true",
599  "Does not need SW waitstates"
600>;
601
602//===------------------------------------------------------------===//
603// Subtarget Features (options and debugging)
604//===------------------------------------------------------------===//
605
606class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
607  "max-private-element-size-"#size,
608  "MaxPrivateElementSize",
609  !cast<string>(size),
610  "Maximum private access size may be "#size
611>;
612
613def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
614def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
615def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
616
617def FeatureDumpCode : SubtargetFeature <"DumpCode",
618  "DumpCode",
619  "true",
620  "Dump MachineInstrs in the CodeEmitter"
621>;
622
623def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
624  "DumpCode",
625  "true",
626  "Dump MachineInstrs in the CodeEmitter"
627>;
628
629// XXX - This should probably be removed once enabled by default
630def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
631  "EnableLoadStoreOpt",
632  "true",
633  "Enable SI load/store optimizer pass"
634>;
635
636// Performance debugging feature. Allow using DS instruction immediate
637// offsets even if the base pointer can't be proven to be base. On SI,
638// base pointer values that won't give the same result as a 16-bit add
639// are not safe to fold, but this will override the conservative test
640// for the base pointer.
641def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
642  "unsafe-ds-offset-folding",
643  "EnableUnsafeDSOffsetFolding",
644  "true",
645  "Force using DS instruction immediate offsets on SI"
646>;
647
648def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
649  "EnableSIScheduler",
650  "true",
651  "Enable SI Machine Scheduler"
652>;
653
654def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
655  "EnableDS128",
656  "true",
657  "Use ds_{read|write}_b128"
658>;
659
660// Sparse texture support requires that all result registers are zeroed when
661// PRTStrictNull is set to true. This feature is turned on for all architectures
662// but is enabled as a feature in case there are situations where PRTStrictNull
663// is disabled by the driver.
664def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
665  "EnablePRTStrictNull",
666  "true",
667  "Enable zeroing of result registers for sparse texture fetches"
668>;
669
670// Unless +-flat-for-global is specified, turn on FlatForGlobal for
671// all OS-es on VI and newer hardware to avoid assertion failures due
672// to missing ADDR64 variants of MUBUF instructions.
673// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
674// instructions.
675
676def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
677  "FlatForGlobal",
678  "true",
679  "Force to generate flat instruction for global"
680>;
681
682def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
683  "auto-waitcnt-before-barrier",
684  "AutoWaitcntBeforeBarrier",
685  "true",
686  "Hardware automatically inserts waitcnt before barrier"
687>;
688
689def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
690  "HasTrigReducedRange",
691  "true",
692  "Requires use of fract on arguments to trig instructions"
693>;
694
695// Alignment enforcement is controlled by a configuration register:
696// SH_MEM_CONFIG.alignment_mode
697def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode",
698  "UnalignedAccessMode",
699  "true",
700  "Enable unaligned global, local and region loads and stores if the hardware"
701  " supports it"
702>;
703
704def FeaturePackedTID : SubtargetFeature<"packed-tid",
705  "HasPackedTID",
706  "true",
707  "Workitem IDs are packed into v0 at kernel launch"
708>;
709
710// Dummy feature used to disable assembler instructions.
711def FeatureDisable : SubtargetFeature<"",
712  "FeatureDisable","true",
713  "Dummy feature to disable assembler instructions"
714>;
715
716class GCNSubtargetFeatureGeneration <string Value,
717                                     string FeatureName,
718                                     list<SubtargetFeature> Implies> :
719        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
720
721def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
722    "southern-islands",
723  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
724  FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,
725  FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
726  FeatureTrigReducedRange, FeatureExtendedImageInsts
727  ]
728>;
729
730def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
731    "sea-islands",
732  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
733  FeatureWavefrontSize64, FeatureFlatAddressSpace,
734  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
735  FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
736  FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureUnalignedBufferAccess
737  ]
738>;
739
740def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
741  "volcanic-islands",
742  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
743   FeatureWavefrontSize64, FeatureFlatAddressSpace,
744   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
745   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
746   FeatureScalarStores, FeatureInv2PiInlineImm,
747   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
748   FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
749   FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
750   FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureFastDenormalF32,
751   FeatureUnalignedBufferAccess
752  ]
753>;
754
755def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
756  "gfx9",
757  [FeatureFP64, FeatureLocalMemorySize65536,
758   FeatureWavefrontSize64, FeatureFlatAddressSpace,
759   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
760   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
761   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
762   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
763   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
764   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
765   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
766   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
767   FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureSupportsXNACK,
768   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess
769  ]
770>;
771
772def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
773  "gfx10",
774  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
775   FeatureFlatAddressSpace,
776   FeatureCIInsts, Feature16BitInsts,
777   FeatureSMemRealTime, FeatureInv2PiInlineImm,
778   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
779   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
780   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
781   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
782   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
783   FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
784   FeatureVOP3Literal, FeatureDPP8, FeatureExtendedImageInsts,
785   FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
786   FeatureGFX10A16, FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureG16,
787   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess
788  ]
789>;
790
791class FeatureSet<list<SubtargetFeature> Features_> {
792  list<SubtargetFeature> Features = Features_;
793}
794
795def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
796   FeatureFastFMAF32,
797   HalfRate64Ops,
798   FeatureLDSBankCount32]>;
799
800def FeatureISAVersion6_0_1 : FeatureSet<
801  [FeatureSouthernIslands,
802   FeatureLDSBankCount32]>;
803
804def FeatureISAVersion6_0_2 : FeatureSet<
805  [FeatureSouthernIslands,
806   FeatureLDSBankCount32]>;
807
808def FeatureISAVersion7_0_0 : FeatureSet<
809  [FeatureSeaIslands,
810   FeatureLDSBankCount32]>;
811
812def FeatureISAVersion7_0_1 : FeatureSet<
813  [FeatureSeaIslands,
814   HalfRate64Ops,
815   FeatureLDSBankCount32,
816   FeatureFastFMAF32]>;
817
818def FeatureISAVersion7_0_2 : FeatureSet<
819  [FeatureSeaIslands,
820   FeatureLDSBankCount16,
821   FeatureFastFMAF32]>;
822
823def FeatureISAVersion7_0_3 : FeatureSet<
824  [FeatureSeaIslands,
825   FeatureLDSBankCount16]>;
826
827def FeatureISAVersion7_0_4 : FeatureSet<
828  [FeatureSeaIslands,
829   FeatureLDSBankCount32]>;
830
831def FeatureISAVersion7_0_5 : FeatureSet<
832  [FeatureSeaIslands,
833   FeatureLDSBankCount16]>;
834
835def FeatureISAVersion8_0_1 : FeatureSet<
836  [FeatureVolcanicIslands,
837   FeatureFastFMAF32,
838   HalfRate64Ops,
839   FeatureLDSBankCount32,
840   FeatureSupportsXNACK,
841   FeatureUnpackedD16VMem]>;
842
843def FeatureISAVersion8_0_2 : FeatureSet<
844  [FeatureVolcanicIslands,
845   FeatureLDSBankCount32,
846   FeatureSGPRInitBug,
847   FeatureUnpackedD16VMem]>;
848
849def FeatureISAVersion8_0_3 : FeatureSet<
850  [FeatureVolcanicIslands,
851   FeatureLDSBankCount32,
852   FeatureUnpackedD16VMem]>;
853
854def FeatureISAVersion8_0_5 : FeatureSet<
855  [FeatureVolcanicIslands,
856   FeatureLDSBankCount32,
857   FeatureSGPRInitBug,
858   FeatureUnpackedD16VMem]>;
859
860def FeatureISAVersion8_1_0 : FeatureSet<
861  [FeatureVolcanicIslands,
862   FeatureLDSBankCount16,
863   FeatureSupportsXNACK,
864   FeatureImageStoreD16Bug,
865   FeatureImageGather4D16Bug]>;
866
867def FeatureISAVersion9_0_0 : FeatureSet<
868  [FeatureGFX9,
869   FeatureMadMixInsts,
870   FeatureLDSBankCount32,
871   FeatureDsSrc2Insts,
872   FeatureExtendedImageInsts,
873   FeatureMadMacF32Insts,
874   FeatureImageGather4D16Bug]>;
875
876def FeatureISAVersion9_0_2 : FeatureSet<
877  [FeatureGFX9,
878   FeatureMadMixInsts,
879   FeatureLDSBankCount32,
880   FeatureDsSrc2Insts,
881   FeatureExtendedImageInsts,
882   FeatureMadMacF32Insts,
883   FeatureImageGather4D16Bug]>;
884
885def FeatureISAVersion9_0_4 : FeatureSet<
886  [FeatureGFX9,
887   FeatureLDSBankCount32,
888   FeatureDsSrc2Insts,
889   FeatureExtendedImageInsts,
890   FeatureMadMacF32Insts,
891   FeatureFmaMixInsts,
892   FeatureImageGather4D16Bug]>;
893
894def FeatureISAVersion9_0_6 : FeatureSet<
895  [FeatureGFX9,
896   HalfRate64Ops,
897   FeatureFmaMixInsts,
898   FeatureLDSBankCount32,
899   FeatureDsSrc2Insts,
900   FeatureExtendedImageInsts,
901   FeatureMadMacF32Insts,
902   FeatureDLInsts,
903   FeatureDot1Insts,
904   FeatureDot2Insts,
905   FeatureSupportsSRAMECC,
906   FeatureImageGather4D16Bug]>;
907
908def FeatureISAVersion9_0_8 : FeatureSet<
909  [FeatureGFX9,
910   HalfRate64Ops,
911   FeatureFmaMixInsts,
912   FeatureLDSBankCount32,
913   FeatureDsSrc2Insts,
914   FeatureExtendedImageInsts,
915   FeatureMadMacF32Insts,
916   FeatureDLInsts,
917   FeatureDot1Insts,
918   FeatureDot2Insts,
919   FeatureDot3Insts,
920   FeatureDot4Insts,
921   FeatureDot5Insts,
922   FeatureDot6Insts,
923   FeatureMAIInsts,
924   FeaturePkFmacF16Inst,
925   FeatureAtomicFaddInsts,
926   FeatureSupportsSRAMECC,
927   FeatureMFMAInlineLiteralBug,
928   FeatureImageGather4D16Bug]>;
929
930def FeatureISAVersion9_0_9 : FeatureSet<
931  [FeatureGFX9,
932   FeatureMadMixInsts,
933   FeatureLDSBankCount32,
934   FeatureDsSrc2Insts,
935   FeatureExtendedImageInsts,
936   FeatureMadMacF32Insts,
937   FeatureImageGather4D16Bug]>;
938
939def FeatureISAVersion9_0_A : FeatureSet<
940  [FeatureGFX9,
941   FeatureGFX90AInsts,
942   FeatureFmaMixInsts,
943   FeatureLDSBankCount32,
944   FeatureDLInsts,
945   FeatureDot1Insts,
946   FeatureDot2Insts,
947   FeatureDot3Insts,
948   FeatureDot4Insts,
949   FeatureDot5Insts,
950   FeatureDot6Insts,
951   Feature64BitDPP,
952   FeaturePackedFP32Ops,
953   FeatureMAIInsts,
954   FeaturePkFmacF16Inst,
955   FeatureAtomicFaddInsts,
956   FeatureMadMacF32Insts,
957   FeatureSupportsSRAMECC,
958   FeaturePackedTID,
959   FullRate64Ops]>;
960
961def FeatureISAVersion9_0_C : FeatureSet<
962  [FeatureGFX9,
963   FeatureMadMixInsts,
964   FeatureLDSBankCount32,
965   FeatureDsSrc2Insts,
966   FeatureExtendedImageInsts,
967   FeatureMadMacF32Insts,
968   FeatureImageGather4D16Bug]>;
969
970// TODO: Organize more features into groups.
971def FeatureGroup {
972  // Bugs present on gfx10.1.
973  list<SubtargetFeature> GFX10_1_Bugs = [
974    FeatureVcmpxPermlaneHazard,
975    FeatureVMEMtoScalarWriteHazard,
976    FeatureSMEMtoVectorWriteHazard,
977    FeatureInstFwdPrefetchBug,
978    FeatureVcmpxExecWARHazard,
979    FeatureLdsBranchVmemWARHazard,
980    FeatureNSAtoVMEMBug,
981    FeatureOffset3fBug,
982    FeatureFlatSegmentOffsetBug
983   ];
984}
985
986def FeatureISAVersion10_1_0 : FeatureSet<
987  !listconcat(FeatureGroup.GFX10_1_Bugs,
988    [FeatureGFX10,
989     FeatureLDSBankCount32,
990     FeatureDLInsts,
991     FeatureNSAEncoding,
992     FeatureWavefrontSize32,
993     FeatureScalarStores,
994     FeatureScalarAtomics,
995     FeatureScalarFlatScratchInsts,
996     FeatureGetWaveIdInst,
997     FeatureMadMacF32Insts,
998     FeatureDsSrc2Insts,
999     FeatureLdsMisalignedBug,
1000     FeatureSupportsXNACK])>;
1001
1002def FeatureISAVersion10_1_1 : FeatureSet<
1003  !listconcat(FeatureGroup.GFX10_1_Bugs,
1004    [FeatureGFX10,
1005     FeatureLDSBankCount32,
1006     FeatureDLInsts,
1007     FeatureDot1Insts,
1008     FeatureDot2Insts,
1009     FeatureDot5Insts,
1010     FeatureDot6Insts,
1011     FeatureNSAEncoding,
1012     FeatureWavefrontSize32,
1013     FeatureScalarStores,
1014     FeatureScalarAtomics,
1015     FeatureScalarFlatScratchInsts,
1016     FeatureGetWaveIdInst,
1017     FeatureMadMacF32Insts,
1018     FeatureDsSrc2Insts,
1019     FeatureLdsMisalignedBug,
1020     FeatureSupportsXNACK])>;
1021
1022def FeatureISAVersion10_1_2 : FeatureSet<
1023  !listconcat(FeatureGroup.GFX10_1_Bugs,
1024    [FeatureGFX10,
1025     FeatureLDSBankCount32,
1026     FeatureDLInsts,
1027     FeatureDot1Insts,
1028     FeatureDot2Insts,
1029     FeatureDot5Insts,
1030     FeatureDot6Insts,
1031     FeatureNSAEncoding,
1032     FeatureWavefrontSize32,
1033     FeatureScalarStores,
1034     FeatureScalarAtomics,
1035     FeatureScalarFlatScratchInsts,
1036     FeatureGetWaveIdInst,
1037     FeatureMadMacF32Insts,
1038     FeatureDsSrc2Insts,
1039     FeatureLdsMisalignedBug,
1040     FeatureSupportsXNACK])>;
1041
1042def FeatureISAVersion10_3_0 : FeatureSet<
1043  [FeatureGFX10,
1044   FeatureGFX10_BEncoding,
1045   FeatureGFX10_3Insts,
1046   FeatureLDSBankCount32,
1047   FeatureDLInsts,
1048   FeatureDot1Insts,
1049   FeatureDot2Insts,
1050   FeatureDot5Insts,
1051   FeatureDot6Insts,
1052   FeatureNSAEncoding,
1053   FeatureWavefrontSize32,
1054   FeatureShaderCyclesRegister]>;
1055
1056//===----------------------------------------------------------------------===//
1057
1058def AMDGPUInstrInfo : InstrInfo {
1059  let guessInstructionProperties = 1;
1060  let noNamedPositionallyEncodedOperands = 1;
1061}
1062
1063def AMDGPUAsmParser : AsmParser {
1064  // Some of the R600 registers have the same name, so this crashes.
1065  // For example T0_XYZW and T0_XY both have the asm name T0.
1066  let ShouldEmitMatchRegisterName = 0;
1067}
1068
1069def AMDGPUAsmWriter : AsmWriter {
1070  int PassSubtarget = 1;
1071}
1072
1073def AMDGPUAsmVariants {
1074  string Default = "Default";
1075  int Default_ID = 0;
1076  string VOP3 = "VOP3";
1077  int VOP3_ID = 1;
1078  string SDWA = "SDWA";
1079  int SDWA_ID = 2;
1080  string SDWA9 = "SDWA9";
1081  int SDWA9_ID = 3;
1082  string DPP = "DPP";
1083  int DPP_ID = 4;
1084  string Disable = "Disable";
1085  int Disable_ID = 5;
1086}
1087
1088def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
1089  let Variant = AMDGPUAsmVariants.Default_ID;
1090  let Name = AMDGPUAsmVariants.Default;
1091}
1092
1093def VOP3AsmParserVariant : AsmParserVariant {
1094  let Variant = AMDGPUAsmVariants.VOP3_ID;
1095  let Name = AMDGPUAsmVariants.VOP3;
1096}
1097
1098def SDWAAsmParserVariant : AsmParserVariant {
1099  let Variant = AMDGPUAsmVariants.SDWA_ID;
1100  let Name = AMDGPUAsmVariants.SDWA;
1101}
1102
1103def SDWA9AsmParserVariant : AsmParserVariant {
1104  let Variant = AMDGPUAsmVariants.SDWA9_ID;
1105  let Name = AMDGPUAsmVariants.SDWA9;
1106}
1107
1108
1109def DPPAsmParserVariant : AsmParserVariant {
1110  let Variant = AMDGPUAsmVariants.DPP_ID;
1111  let Name = AMDGPUAsmVariants.DPP;
1112}
1113
1114def AMDGPU : Target {
1115  // Pull in Instruction Info:
1116  let InstructionSet = AMDGPUInstrInfo;
1117  let AssemblyParsers = [AMDGPUAsmParser];
1118  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
1119                                VOP3AsmParserVariant,
1120                                SDWAAsmParserVariant,
1121                                SDWA9AsmParserVariant,
1122                                DPPAsmParserVariant];
1123  let AssemblyWriters = [AMDGPUAsmWriter];
1124  let AllowRegisterRenaming = 1;
1125}
1126
1127// Dummy Instruction itineraries for pseudo instructions
1128def ALU_NULL : FuncUnit;
1129def NullALU : InstrItinClass;
1130
1131//===----------------------------------------------------------------------===//
1132// Predicate helper class
1133//===----------------------------------------------------------------------===//
1134
1135def isGFX6 :
1136  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1137  AssemblerPredicate<(all_of FeatureSouthernIslands)>;
1138
1139def isGFX6GFX7 :
1140  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1141            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1142  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
1143
1144def isGFX6GFX7GFX10 :
1145  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1146            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1147            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1148  AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
1149
1150def isGFX7Only :
1151  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1152  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
1153
1154def isGFX7GFX10 :
1155  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1156            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1157  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
1158
1159def isGFX7GFX8GFX9 :
1160  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1161            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1162            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1163  AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
1164
1165def isGFX6GFX7GFX8GFX9 :
1166  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1167            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1168            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1169            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1170  AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
1171
1172def isGFX6GFX7GFX8GFX9NotGFX90A :
1173  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1174            "(Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1175            " Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1176            " Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1177            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1178  AssemblerPredicate<(all_of (not FeatureGFX10Insts), (not FeatureGFX90AInsts))>;
1179
1180def isGFX7Plus :
1181  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1182  AssemblerPredicate<(all_of FeatureCIInsts)>;
1183
1184def isGFX8Plus :
1185  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1186  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1187
1188def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1189                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1190  AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1191
1192def isGFX9Plus :
1193  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1194  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1195
1196def isGFX9Only : Predicate <
1197  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1198  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1199
1200def isGCN3ExcludingGFX90A :
1201  Predicate<"Subtarget->isGCN3Encoding() && !Subtarget->hasGFX90AInsts()">,
1202  AssemblerPredicate<(all_of FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1203
1204def isGFX90APlus :
1205  Predicate<"Subtarget->hasGFX90AInsts()">,
1206  AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1207
1208def isNotGFX90APlus :
1209  Predicate<"!Subtarget->hasGFX90AInsts()">,
1210  AssemblerPredicate<(all_of (not FeatureGFX90AInsts))>;
1211
1212def isGFX8GFX9NotGFX90A :
1213  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1214            "(Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1215            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1216  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1217
1218def isGFX90AOnly :
1219  Predicate<"Subtarget->hasGFX90AInsts()">,
1220  AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1221
1222def isGFX8GFX9 :
1223  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1224            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1225  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1226
1227def isGFX10Plus :
1228  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1229  AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1230
1231def isGFX10Before1030 :
1232  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 &&"
1233            "!Subtarget->hasGFX10_3Insts()">,
1234  AssemblerPredicate<(all_of FeatureGFX10Insts,(not FeatureGFX10_3Insts))>;
1235
1236def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1237  AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1238
1239def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1240  AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1241def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1242  AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1243def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1244  AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1245def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1246  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1247
1248def HasFlatScratchSTMode : Predicate<"Subtarget->hasFlatScratchSTMode()">,
1249  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1250
1251def HasGFX10_BEncoding : Predicate<"Subtarget->hasGFX10_BEncoding()">,
1252  AssemblerPredicate<(all_of FeatureGFX10_BEncoding)>;
1253
1254def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1255  AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1256def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1257  AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1258
1259def D16PreservesUnusedBits :
1260  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1261  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1262
1263def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1264def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1265
1266def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1267  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1268
1269def HasLDSFPAtomics : Predicate<"Subtarget->hasLDSFPAtomics()">,
1270  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1271
1272def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1273  AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1274
1275def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1276
1277def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1278  AssemblerPredicate<(all_of Feature16BitInsts)>;
1279def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1280  AssemblerPredicate<(all_of FeatureVOP3P)>;
1281
1282def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
1283def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
1284
1285def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1286  AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1287
1288def HasSDWA9 :
1289  Predicate<"Subtarget->hasSDWA()">,
1290  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1291
1292def HasSDWA10 :
1293  Predicate<"Subtarget->hasSDWA()">,
1294  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1295
1296def HasDPP : Predicate<"Subtarget->hasDPP()">,
1297  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1298
1299def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1300  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1301
1302def Has64BitDPP : Predicate<"Subtarget->has64BitDPP()">,
1303  AssemblerPredicate<(all_of Feature64BitDPP)>;
1304
1305def HasPackedFP32Ops : Predicate<"Subtarget->hasPackedFP32Ops()">,
1306  AssemblerPredicate<(all_of FeaturePackedFP32Ops)>;
1307
1308def HasExtendedImageInsts : Predicate<"Subtarget->hasExtendedImageInsts()">,
1309  AssemblerPredicate<(all_of FeatureExtendedImageInsts)>;
1310
1311def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1312  AssemblerPredicate<(all_of FeatureR128A16)>;
1313
1314def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1315  AssemblerPredicate<(all_of FeatureGFX10A16)>;
1316
1317def HasG16 : Predicate<"Subtarget->hasG16()">,
1318  AssemblerPredicate<(all_of FeatureG16)>;
1319
1320def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1321  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1322
1323def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1324  AssemblerPredicate<(all_of FeatureIntClamp)>;
1325
1326def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1327  AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1328
1329def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1330  AssemblerPredicate<(all_of FeatureScalarStores)>;
1331
1332def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1333  AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1334
1335def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1336  AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1337
1338def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1339  AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1340
1341def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1342def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1343def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1344                      AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1345def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1346                AssemblerPredicate<(all_of FeatureMovrel)>;
1347
1348def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1349  AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1350
1351def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1352  AssemblerPredicate<(all_of FeatureDLInsts)>;
1353
1354def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1355  AssemblerPredicate<(all_of FeatureDot1Insts)>;
1356
1357def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1358  AssemblerPredicate<(all_of FeatureDot2Insts)>;
1359
1360def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1361  AssemblerPredicate<(all_of FeatureDot3Insts)>;
1362
1363def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1364  AssemblerPredicate<(all_of FeatureDot4Insts)>;
1365
1366def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1367  AssemblerPredicate<(all_of FeatureDot5Insts)>;
1368
1369def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1370  AssemblerPredicate<(all_of FeatureDot6Insts)>;
1371
1372def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">,
1373  AssemblerPredicate<(all_of FeatureGetWaveIdInst)>;
1374
1375def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1376  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1377
1378def HasSMemRealTime : Predicate<"Subtarget->hasSMemRealTime()">,
1379  AssemblerPredicate<(all_of FeatureSMemRealTime)>;
1380
1381def HasSMemTimeInst : Predicate<"Subtarget->hasSMemTimeInst()">,
1382  AssemblerPredicate<(all_of FeatureSMemTimeInst)>;
1383
1384def HasShaderCyclesRegister : Predicate<"Subtarget->hasShaderCyclesRegister()">,
1385  AssemblerPredicate<(all_of FeatureShaderCyclesRegister)>;
1386
1387def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1388  AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1389
1390def HasMadMacF32Insts : Predicate<"Subtarget->hasMadMacF32Insts()">,
1391  AssemblerPredicate<(all_of FeatureMadMacF32Insts)>;
1392
1393def HasFmaLegacy32 : Predicate<"Subtarget->hasGFX10_3Insts()">,
1394  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1395
1396def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1397  AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>;
1398
1399def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
1400  AssemblerPredicate<(all_of FeatureDsSrc2Insts)>;
1401
1402def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">,
1403  AssemblerPredicate<(all_of FeatureOffset3fBug)>;
1404
1405def EnableLateCFGStructurize : Predicate<
1406  "EnableLateStructurizeCFG">;
1407
1408def EnableFlatScratch : Predicate<"Subtarget->enableFlatScratch()">;
1409
1410def DisableFlatScratch : Predicate<"!Subtarget->enableFlatScratch()">;
1411
1412def HasUnalignedAccessMode : Predicate<"Subtarget->hasUnalignedAccessMode()">,
1413  AssemblerPredicate<(all_of FeatureUnalignedAccessMode)>;
1414
1415// Include AMDGPU TD files
1416include "SISchedule.td"
1417include "GCNProcessors.td"
1418include "AMDGPUInstrInfo.td"
1419include "SIRegisterInfo.td"
1420include "AMDGPURegisterBanks.td"
1421include "AMDGPUInstructions.td"
1422include "SIInstrInfo.td"
1423include "AMDGPUCallingConv.td"
1424include "AMDGPUSearchableTables.td"
1425