1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21
22class BoolToList<bit Value> {
23  list<int> ret = !if(Value, [1]<int>, []<int>);
24}
25
26//===------------------------------------------------------------===//
27// Subtarget Features (device properties)
28//===------------------------------------------------------------===//
29
30def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
31  "FastFMAF32",
32  "true",
33  "Assuming f32 fma is at least as fast as mul + add"
34>;
35
36def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
37  "FastDenormalF32",
38  "true",
39  "Enabling denormals does not cause f32 instructions to run at f64 rates"
40>;
41
42def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
43  "MIMG_R128",
44  "true",
45  "Support 128-bit texture resources"
46>;
47
48def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
49  "HalfRate64Ops",
50  "true",
51  "Most fp64 instructions are half rate instead of quarter"
52>;
53
54def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
55  "FlatAddressSpace",
56  "true",
57  "Support flat address space"
58>;
59
60def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
61  "FlatInstOffsets",
62  "true",
63  "Flat instructions have immediate offset addressing mode"
64>;
65
66def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
67  "FlatGlobalInsts",
68  "true",
69  "Have global_* flat memory instructions"
70>;
71
72def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
73  "FlatScratchInsts",
74  "true",
75  "Have scratch_* flat memory instructions"
76>;
77
78def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
79  "ScalarFlatScratchInsts",
80  "true",
81  "Have s_scratch_* flat memory instructions"
82>;
83
84def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
85  "AddNoCarryInsts",
86  "true",
87  "Have VALU add/sub instructions without carry out"
88>;
89
90def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
91  "UnalignedBufferAccess",
92  "true",
93  "Support unaligned global loads and stores"
94>;
95
96def FeatureTrapHandler: SubtargetFeature<"trap-handler",
97  "TrapHandler",
98  "true",
99  "Trap handler support"
100>;
101
102def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
103  "UnalignedScratchAccess",
104  "true",
105  "Support unaligned scratch loads and stores"
106>;
107
108// LDS alignment enforcement is controlled by a configuration register:
109// SH_MEM_CONFIG.alignment_mode
110def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode",
111  "UnalignedAccessMode",
112  "true",
113  "Support unaligned local and region loads and stores"
114>;
115
116def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access",
117  "UnalignedDSAccess",
118  "true",
119  "Does not requires 16 byte alignment for certain local and region loads and stores"
120>;
121
122def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
123  "HasApertureRegs",
124  "true",
125  "Has Memory Aperture Base and Size Registers"
126>;
127
128def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
129  "HasMadMixInsts",
130  "true",
131  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
132>;
133
134def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
135  "HasFmaMixInsts",
136  "true",
137  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
138>;
139
140def FeatureDoesNotSupportXNACK : SubtargetFeature<"no-xnack-support",
141  "DoesNotSupportXNACK",
142  "true",
143  "Hardware does not support XNACK"
144>;
145
146// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
147// XNACK. The current default kernel driver setting is:
148// - graphics ring: XNACK disabled
149// - compute ring: XNACK enabled
150//
151// If XNACK is enabled, the VMEM latency can be worse.
152// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
153def FeatureXNACK : SubtargetFeature<"xnack",
154  "EnableXNACK",
155  "true",
156  "Enable XNACK support"
157>;
158
159def FeatureCuMode : SubtargetFeature<"cumode",
160  "EnableCuMode",
161  "true",
162  "Enable CU wavefront execution mode"
163>;
164
165def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
166  "SGPRInitBug",
167  "true",
168  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
169>;
170
171def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
172  "LDSMisalignedBug",
173  "true",
174  "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode"
175>;
176
177def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
178  "HasMFMAInlineLiteralBug",
179  "true",
180  "MFMA cannot use inline literal as SrcC"
181>;
182
183def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
184  "HasVcmpxPermlaneHazard",
185  "true",
186  "TODO: describe me"
187>;
188
189def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
190  "HasVMEMtoScalarWriteHazard",
191  "true",
192  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
193>;
194
195def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
196  "HasSMEMtoVectorWriteHazard",
197  "true",
198  "s_load_dword followed by v_cmp page faults"
199>;
200
201def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
202  "HasInstFwdPrefetchBug",
203  "true",
204  "S_INST_PREFETCH instruction causes shader to hang"
205>;
206
207def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
208  "HasVcmpxExecWARHazard",
209  "true",
210  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
211>;
212
213def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
214  "HasLdsBranchVmemWARHazard",
215  "true",
216  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
217>;
218
219def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
220  "HasNSAtoVMEMBug",
221  "true",
222  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
223>;
224
225def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
226  "HasFlatSegmentOffsetBug",
227  "true",
228  "GFX10 bug, inst_offset ignored in flat segment"
229>;
230
231def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
232  "HasOffset3fBug",
233  "true",
234  "Branch offset of 3f hardware bug"
235>;
236
237def FeatureImageStoreD16Bug : SubtargetFeature<"image-store-d16-bug",
238  "HasImageStoreD16Bug",
239  "true",
240  "Image Store D16 hardware bug"
241>;
242
243def FeatureImageGather4D16Bug : SubtargetFeature<"image-gather4-d16-bug",
244  "HasImageGather4D16Bug",
245  "true",
246  "Image Gather4 D16 hardware bug"
247>;
248
249class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
250  "ldsbankcount"#Value,
251  "LDSBankCount",
252  !cast<string>(Value),
253  "The number of LDS banks per compute unit."
254>;
255
256def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
257def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
258
259def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
260  "GCN3Encoding",
261  "true",
262  "Encoding format for VI"
263>;
264
265def FeatureCIInsts : SubtargetFeature<"ci-insts",
266  "CIInsts",
267  "true",
268  "Additional instructions for CI+"
269>;
270
271def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
272  "GFX8Insts",
273  "true",
274  "Additional instructions for GFX8+"
275>;
276
277def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
278  "GFX9Insts",
279  "true",
280  "Additional instructions for GFX9+"
281>;
282
283def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
284  "GFX10Insts",
285  "true",
286  "Additional instructions for GFX10+"
287>;
288
289def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts",
290  "GFX10_3Insts",
291  "true",
292  "Additional instructions for GFX10.3"
293>;
294
295def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
296  "GFX7GFX8GFX9Insts",
297  "true",
298  "Instructions shared in GFX7, GFX8, GFX9"
299>;
300
301def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
302  "HasSMemRealTime",
303  "true",
304  "Has s_memrealtime instruction"
305>;
306
307def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
308  "HasInv2PiInlineImm",
309  "true",
310  "Has 1 / (2 * pi) as inline immediate"
311>;
312
313def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
314  "Has16BitInsts",
315  "true",
316  "Has i16/f16 instructions"
317>;
318
319def FeatureVOP3P : SubtargetFeature<"vop3p",
320  "HasVOP3PInsts",
321  "true",
322  "Has VOP3P packed instructions"
323>;
324
325def FeatureMovrel : SubtargetFeature<"movrel",
326  "HasMovrel",
327  "true",
328  "Has v_movrel*_b32 instructions"
329>;
330
331def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
332  "HasVGPRIndexMode",
333  "true",
334  "Has VGPR mode register indexing"
335>;
336
337def FeatureScalarStores : SubtargetFeature<"scalar-stores",
338  "HasScalarStores",
339  "true",
340  "Has store scalar memory instructions"
341>;
342
343def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
344  "HasScalarAtomics",
345  "true",
346  "Has atomic scalar memory instructions"
347>;
348
349def FeatureSDWA : SubtargetFeature<"sdwa",
350  "HasSDWA",
351  "true",
352  "Support SDWA (Sub-DWORD Addressing) extension"
353>;
354
355def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
356  "HasSDWAOmod",
357  "true",
358  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
359>;
360
361def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
362  "HasSDWAScalar",
363  "true",
364  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
365>;
366
367def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
368  "HasSDWASdst",
369  "true",
370  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
371>;
372
373def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
374  "HasSDWAMac",
375  "true",
376  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
377>;
378
379def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
380  "HasSDWAOutModsVOPC",
381  "true",
382  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
383>;
384
385def FeatureDPP : SubtargetFeature<"dpp",
386  "HasDPP",
387  "true",
388  "Support DPP (Data Parallel Primitives) extension"
389>;
390
391// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
392def FeatureDPP8 : SubtargetFeature<"dpp8",
393  "HasDPP8",
394  "true",
395  "Support DPP8 (Data Parallel Primitives) extension"
396>;
397
398def FeatureR128A16 : SubtargetFeature<"r128-a16",
399  "HasR128A16",
400  "true",
401  "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
402>;
403
404def FeatureGFX10A16 : SubtargetFeature<"a16",
405  "HasGFX10A16",
406  "true",
407  "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
408>;
409
410def FeatureG16 : SubtargetFeature<"g16",
411  "HasG16",
412  "true",
413  "Support G16 for 16-bit gradient image operands"
414>;
415
416def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
417  "HasNSAEncoding",
418  "true",
419  "Support NSA encoding for image instructions"
420>;
421
422def FeatureGFX10_BEncoding : SubtargetFeature<"gfx10_b-encoding",
423  "GFX10_BEncoding",
424  "true",
425  "Encoding format GFX10_B"
426>;
427
428def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
429  "HasIntClamp",
430  "true",
431  "Support clamp for integer destination"
432>;
433
434def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
435  "HasUnpackedD16VMem",
436  "true",
437  "Has unpacked d16 vmem instructions"
438>;
439
440def FeatureDLInsts : SubtargetFeature<"dl-insts",
441  "HasDLInsts",
442  "true",
443  "Has v_fmac_f32 and v_xnor_b32 instructions"
444>;
445
446def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
447  "HasDot1Insts",
448  "true",
449  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
450>;
451
452def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
453  "HasDot2Insts",
454  "true",
455  "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
456>;
457
458def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
459  "HasDot3Insts",
460  "true",
461  "Has v_dot8c_i32_i4 instruction"
462>;
463
464def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
465  "HasDot4Insts",
466  "true",
467  "Has v_dot2c_i32_i16 instruction"
468>;
469
470def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
471  "HasDot5Insts",
472  "true",
473  "Has v_dot2c_f32_f16 instruction"
474>;
475
476def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
477  "HasDot6Insts",
478  "true",
479  "Has v_dot4c_i32_i8 instruction"
480>;
481
482def FeatureMAIInsts : SubtargetFeature<"mai-insts",
483  "HasMAIInsts",
484  "true",
485  "Has mAI instructions"
486>;
487
488def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
489  "HasPkFmacF16Inst",
490  "true",
491  "Has v_pk_fmac_f16 instruction"
492>;
493
494def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
495  "HasAtomicFaddInsts",
496  "true",
497  "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
498  "global_atomic_pk_add_f16 instructions",
499  [FeatureFlatGlobalInsts]
500>;
501
502def FeatureDoesNotSupportSRAMECC : SubtargetFeature<"no-sram-ecc-support",
503  "DoesNotSupportSRAMECC",
504  "true",
505  "Hardware does not support SRAM ECC"
506>;
507
508def FeatureSRAMECC : SubtargetFeature<"sram-ecc",
509  "EnableSRAMECC",
510  "true",
511  "Enable SRAM ECC"
512>;
513
514def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
515  "HasNoSdstCMPX",
516  "true",
517  "V_CMPX does not write VCC/SGPR in addition to EXEC"
518>;
519
520def FeatureVscnt : SubtargetFeature<"vscnt",
521  "HasVscnt",
522  "true",
523  "Has separate store vscnt counter"
524>;
525
526def FeatureGetWaveIdInst : SubtargetFeature<"get-wave-id-inst",
527  "HasGetWaveIdInst",
528  "true",
529  "Has s_get_waveid_in_workgroup instruction"
530>;
531
532def FeatureSMemTimeInst : SubtargetFeature<"s-memtime-inst",
533  "HasSMemTimeInst",
534  "true",
535  "Has s_memtime instruction"
536>;
537
538def FeatureMadMacF32Insts : SubtargetFeature<"mad-mac-f32-insts",
539  "HasMadMacF32Insts",
540  "true",
541  "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions"
542>;
543
544def FeatureDsSrc2Insts : SubtargetFeature<"ds-src2-insts",
545  "HasDsSrc2Insts",
546  "true",
547  "Has ds_*_src2 instructions"
548>;
549
550def FeatureRegisterBanking : SubtargetFeature<"register-banking",
551  "HasRegisterBanking",
552  "true",
553  "Has register banking"
554>;
555
556def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
557  "HasVOP3Literal",
558  "true",
559  "Can use one literal in VOP3"
560>;
561
562def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
563  "HasNoDataDepHazard",
564  "true",
565  "Does not need SW waitstates"
566>;
567
568//===------------------------------------------------------------===//
569// Subtarget Features (options and debugging)
570//===------------------------------------------------------------===//
571
572class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
573  "max-private-element-size-"#size,
574  "MaxPrivateElementSize",
575  !cast<string>(size),
576  "Maximum private access size may be "#size
577>;
578
579def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
580def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
581def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
582
583def FeatureDumpCode : SubtargetFeature <"DumpCode",
584  "DumpCode",
585  "true",
586  "Dump MachineInstrs in the CodeEmitter"
587>;
588
589def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
590  "DumpCode",
591  "true",
592  "Dump MachineInstrs in the CodeEmitter"
593>;
594
595// XXX - This should probably be removed once enabled by default
596def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
597  "EnableLoadStoreOpt",
598  "true",
599  "Enable SI load/store optimizer pass"
600>;
601
602// Performance debugging feature. Allow using DS instruction immediate
603// offsets even if the base pointer can't be proven to be base. On SI,
604// base pointer values that won't give the same result as a 16-bit add
605// are not safe to fold, but this will override the conservative test
606// for the base pointer.
607def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
608  "unsafe-ds-offset-folding",
609  "EnableUnsafeDSOffsetFolding",
610  "true",
611  "Force using DS instruction immediate offsets on SI"
612>;
613
614def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
615  "EnableSIScheduler",
616  "true",
617  "Enable SI Machine Scheduler"
618>;
619
620def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
621  "EnableDS128",
622  "true",
623  "Use ds_{read|write}_b128"
624>;
625
626// Sparse texture support requires that all result registers are zeroed when
627// PRTStrictNull is set to true. This feature is turned on for all architectures
628// but is enabled as a feature in case there are situations where PRTStrictNull
629// is disabled by the driver.
630def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
631  "EnablePRTStrictNull",
632  "true",
633  "Enable zeroing of result registers for sparse texture fetches"
634>;
635
636// Unless +-flat-for-global is specified, turn on FlatForGlobal for
637// all OS-es on VI and newer hardware to avoid assertion failures due
638// to missing ADDR64 variants of MUBUF instructions.
639// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
640// instructions.
641
642def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
643  "FlatForGlobal",
644  "true",
645  "Force to generate flat instruction for global"
646>;
647
648def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
649  "auto-waitcnt-before-barrier",
650  "AutoWaitcntBeforeBarrier",
651  "true",
652  "Hardware automatically inserts waitcnt before barrier"
653>;
654
655def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
656  "HasTrigReducedRange",
657  "true",
658  "Requires use of fract on arguments to trig instructions"
659>;
660
661// Dummy feature used to disable assembler instructions.
662def FeatureDisable : SubtargetFeature<"",
663  "FeatureDisable","true",
664  "Dummy feature to disable assembler instructions"
665>;
666
667class GCNSubtargetFeatureGeneration <string Value,
668                                     string FeatureName,
669                                     list<SubtargetFeature> Implies> :
670        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
671
672def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
673    "southern-islands",
674  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
675  FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,
676  FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
677  FeatureTrigReducedRange, FeatureDoesNotSupportSRAMECC,
678  FeatureDoesNotSupportXNACK]
679>;
680
681def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
682    "sea-islands",
683  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
684  FeatureWavefrontSize64, FeatureFlatAddressSpace,
685  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
686  FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
687  FeatureDsSrc2Insts, FeatureDoesNotSupportSRAMECC]
688>;
689
690def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
691  "volcanic-islands",
692  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
693   FeatureWavefrontSize64, FeatureFlatAddressSpace,
694   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
695   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
696   FeatureScalarStores, FeatureInv2PiInlineImm,
697   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
698   FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
699   FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
700   FeatureDsSrc2Insts, FeatureDoesNotSupportSRAMECC, FeatureFastDenormalF32
701  ]
702>;
703
704def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
705  "gfx9",
706  [FeatureFP64, FeatureLocalMemorySize65536,
707   FeatureWavefrontSize64, FeatureFlatAddressSpace,
708   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
709   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
710   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
711   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
712   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
713   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
714   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
715   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
716   FeatureSMemTimeInst, FeatureMadMacF32Insts, FeatureDsSrc2Insts,
717   FeatureFastDenormalF32, FeatureUnalignedDSAccess
718  ]
719>;
720
721def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
722  "gfx10",
723  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
724   FeatureFlatAddressSpace,
725   FeatureCIInsts, Feature16BitInsts,
726   FeatureSMemRealTime, FeatureInv2PiInlineImm,
727   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
728   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
729   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
730   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
731   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
732   FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
733   FeatureVOP3Literal, FeatureDPP8,
734   FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureDoesNotSupportSRAMECC,
735   FeatureGFX10A16, FeatureFastDenormalF32, FeatureG16,
736   FeatureUnalignedDSAccess
737  ]
738>;
739
740class FeatureSet<list<SubtargetFeature> Features_> {
741  list<SubtargetFeature> Features = Features_;
742}
743
744def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
745   FeatureFastFMAF32,
746   HalfRate64Ops,
747   FeatureLDSBankCount32,
748   FeatureDoesNotSupportXNACK]>;
749
750def FeatureISAVersion6_0_1 : FeatureSet<
751  [FeatureSouthernIslands,
752   FeatureLDSBankCount32,
753   FeatureDoesNotSupportXNACK]>;
754
755def FeatureISAVersion6_0_2 : FeatureSet<
756  [FeatureSouthernIslands,
757   FeatureLDSBankCount32,
758   FeatureDoesNotSupportXNACK]>;
759
760def FeatureISAVersion7_0_0 : FeatureSet<
761  [FeatureSeaIslands,
762   FeatureLDSBankCount32,
763   FeatureDoesNotSupportXNACK]>;
764
765def FeatureISAVersion7_0_1 : FeatureSet<
766  [FeatureSeaIslands,
767   HalfRate64Ops,
768   FeatureLDSBankCount32,
769   FeatureFastFMAF32,
770   FeatureDoesNotSupportXNACK]>;
771
772def FeatureISAVersion7_0_2 : FeatureSet<
773  [FeatureSeaIslands,
774   FeatureLDSBankCount16,
775   FeatureFastFMAF32,
776   FeatureDoesNotSupportXNACK]>;
777
778def FeatureISAVersion7_0_3 : FeatureSet<
779  [FeatureSeaIslands,
780   FeatureLDSBankCount16,
781   FeatureDoesNotSupportXNACK]>;
782
783def FeatureISAVersion7_0_4 : FeatureSet<
784  [FeatureSeaIslands,
785   FeatureLDSBankCount32,
786   FeatureDoesNotSupportXNACK]>;
787
788def FeatureISAVersion7_0_5 : FeatureSet<
789  [FeatureSeaIslands,
790   FeatureLDSBankCount16,
791   FeatureDoesNotSupportXNACK]>;
792
793def FeatureISAVersion8_0_1 : FeatureSet<
794  [FeatureVolcanicIslands,
795   FeatureFastFMAF32,
796   HalfRate64Ops,
797   FeatureLDSBankCount32,
798   FeatureXNACK,
799   FeatureUnpackedD16VMem]>;
800
801def FeatureISAVersion8_0_2 : FeatureSet<
802  [FeatureVolcanicIslands,
803   FeatureLDSBankCount32,
804   FeatureSGPRInitBug,
805   FeatureUnpackedD16VMem,
806   FeatureDoesNotSupportXNACK]>;
807
808def FeatureISAVersion8_0_3 : FeatureSet<
809  [FeatureVolcanicIslands,
810   FeatureLDSBankCount32,
811   FeatureUnpackedD16VMem,
812   FeatureDoesNotSupportXNACK]>;
813
814def FeatureISAVersion8_0_5 : FeatureSet<
815  [FeatureVolcanicIslands,
816   FeatureLDSBankCount32,
817   FeatureSGPRInitBug,
818   FeatureUnpackedD16VMem,
819   FeatureDoesNotSupportXNACK]>;
820
821def FeatureISAVersion8_1_0 : FeatureSet<
822  [FeatureVolcanicIslands,
823   FeatureLDSBankCount16,
824   FeatureXNACK,
825   FeatureImageStoreD16Bug,
826   FeatureImageGather4D16Bug]>;
827
828def FeatureISAVersion9_0_0 : FeatureSet<
829  [FeatureGFX9,
830   FeatureMadMixInsts,
831   FeatureLDSBankCount32,
832   FeatureDoesNotSupportXNACK,
833   FeatureDoesNotSupportSRAMECC,
834   FeatureImageGather4D16Bug]>;
835
836def FeatureISAVersion9_0_2 : FeatureSet<
837  [FeatureGFX9,
838   FeatureMadMixInsts,
839   FeatureLDSBankCount32,
840   FeatureXNACK,
841   FeatureDoesNotSupportSRAMECC,
842   FeatureImageGather4D16Bug]>;
843
844def FeatureISAVersion9_0_4 : FeatureSet<
845  [FeatureGFX9,
846   FeatureLDSBankCount32,
847   FeatureFmaMixInsts,
848   FeatureDoesNotSupportXNACK,
849   FeatureDoesNotSupportSRAMECC,
850   FeatureImageGather4D16Bug]>;
851
852def FeatureISAVersion9_0_6 : FeatureSet<
853  [FeatureGFX9,
854   HalfRate64Ops,
855   FeatureFmaMixInsts,
856   FeatureLDSBankCount32,
857   FeatureDLInsts,
858   FeatureDot1Insts,
859   FeatureDot2Insts,
860   FeatureDoesNotSupportXNACK,
861   FeatureImageGather4D16Bug]>;
862
863def FeatureISAVersion9_0_8 : FeatureSet<
864  [FeatureGFX9,
865   HalfRate64Ops,
866   FeatureFmaMixInsts,
867   FeatureLDSBankCount32,
868   FeatureDLInsts,
869   FeatureDot1Insts,
870   FeatureDot2Insts,
871   FeatureDot3Insts,
872   FeatureDot4Insts,
873   FeatureDot5Insts,
874   FeatureDot6Insts,
875   FeatureMAIInsts,
876   FeaturePkFmacF16Inst,
877   FeatureAtomicFaddInsts,
878   FeatureSRAMECC,
879   FeatureMFMAInlineLiteralBug,
880   FeatureImageGather4D16Bug]>;
881
882def FeatureISAVersion9_0_9 : FeatureSet<
883  [FeatureGFX9,
884   FeatureMadMixInsts,
885   FeatureLDSBankCount32,
886   FeatureXNACK,
887   FeatureImageGather4D16Bug]>;
888
889// TODO: Organize more features into groups.
890def FeatureGroup {
891  // Bugs present on gfx10.1.
892  list<SubtargetFeature> GFX10_1_Bugs = [
893    FeatureVcmpxPermlaneHazard,
894    FeatureVMEMtoScalarWriteHazard,
895    FeatureSMEMtoVectorWriteHazard,
896    FeatureInstFwdPrefetchBug,
897    FeatureVcmpxExecWARHazard,
898    FeatureLdsBranchVmemWARHazard,
899    FeatureNSAtoVMEMBug,
900    FeatureOffset3fBug,
901    FeatureFlatSegmentOffsetBug
902   ];
903}
904
905def FeatureISAVersion10_1_0 : FeatureSet<
906  !listconcat(FeatureGroup.GFX10_1_Bugs,
907    [FeatureGFX10,
908     FeatureLDSBankCount32,
909     FeatureDLInsts,
910     FeatureNSAEncoding,
911     FeatureWavefrontSize32,
912     FeatureScalarStores,
913     FeatureScalarAtomics,
914     FeatureScalarFlatScratchInsts,
915     FeatureGetWaveIdInst,
916     FeatureSMemTimeInst,
917     FeatureMadMacF32Insts,
918     FeatureDsSrc2Insts,
919     FeatureLdsMisalignedBug,
920     FeatureDoesNotSupportXNACK])>;
921
922def FeatureISAVersion10_1_1 : FeatureSet<
923  !listconcat(FeatureGroup.GFX10_1_Bugs,
924    [FeatureGFX10,
925     FeatureLDSBankCount32,
926     FeatureDLInsts,
927     FeatureDot1Insts,
928     FeatureDot2Insts,
929     FeatureDot5Insts,
930     FeatureDot6Insts,
931     FeatureNSAEncoding,
932     FeatureWavefrontSize32,
933     FeatureScalarStores,
934     FeatureScalarAtomics,
935     FeatureScalarFlatScratchInsts,
936     FeatureGetWaveIdInst,
937     FeatureSMemTimeInst,
938     FeatureMadMacF32Insts,
939     FeatureDsSrc2Insts,
940     FeatureLdsMisalignedBug,
941     FeatureDoesNotSupportXNACK])>;
942
943def FeatureISAVersion10_1_2 : FeatureSet<
944  !listconcat(FeatureGroup.GFX10_1_Bugs,
945    [FeatureGFX10,
946     FeatureLDSBankCount32,
947     FeatureDLInsts,
948     FeatureDot1Insts,
949     FeatureDot2Insts,
950     FeatureDot5Insts,
951     FeatureDot6Insts,
952     FeatureNSAEncoding,
953     FeatureWavefrontSize32,
954     FeatureScalarStores,
955     FeatureScalarAtomics,
956     FeatureScalarFlatScratchInsts,
957     FeatureGetWaveIdInst,
958     FeatureSMemTimeInst,
959     FeatureMadMacF32Insts,
960     FeatureDsSrc2Insts,
961     FeatureLdsMisalignedBug,
962     FeatureDoesNotSupportXNACK])>;
963
964def FeatureISAVersion10_3_0 : FeatureSet<
965  [FeatureGFX10,
966   FeatureGFX10_BEncoding,
967   FeatureGFX10_3Insts,
968   FeatureLDSBankCount32,
969   FeatureDLInsts,
970   FeatureDot1Insts,
971   FeatureDot2Insts,
972   FeatureDot5Insts,
973   FeatureDot6Insts,
974   FeatureNSAEncoding,
975   FeatureWavefrontSize32,
976   FeatureDoesNotSupportXNACK]>;
977
978//===----------------------------------------------------------------------===//
979
980def AMDGPUInstrInfo : InstrInfo {
981  let guessInstructionProperties = 1;
982  let noNamedPositionallyEncodedOperands = 1;
983}
984
985def AMDGPUAsmParser : AsmParser {
986  // Some of the R600 registers have the same name, so this crashes.
987  // For example T0_XYZW and T0_XY both have the asm name T0.
988  let ShouldEmitMatchRegisterName = 0;
989}
990
991def AMDGPUAsmWriter : AsmWriter {
992  int PassSubtarget = 1;
993}
994
995def AMDGPUAsmVariants {
996  string Default = "Default";
997  int Default_ID = 0;
998  string VOP3 = "VOP3";
999  int VOP3_ID = 1;
1000  string SDWA = "SDWA";
1001  int SDWA_ID = 2;
1002  string SDWA9 = "SDWA9";
1003  int SDWA9_ID = 3;
1004  string DPP = "DPP";
1005  int DPP_ID = 4;
1006  string Disable = "Disable";
1007  int Disable_ID = 5;
1008}
1009
1010def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
1011  let Variant = AMDGPUAsmVariants.Default_ID;
1012  let Name = AMDGPUAsmVariants.Default;
1013}
1014
1015def VOP3AsmParserVariant : AsmParserVariant {
1016  let Variant = AMDGPUAsmVariants.VOP3_ID;
1017  let Name = AMDGPUAsmVariants.VOP3;
1018}
1019
1020def SDWAAsmParserVariant : AsmParserVariant {
1021  let Variant = AMDGPUAsmVariants.SDWA_ID;
1022  let Name = AMDGPUAsmVariants.SDWA;
1023}
1024
1025def SDWA9AsmParserVariant : AsmParserVariant {
1026  let Variant = AMDGPUAsmVariants.SDWA9_ID;
1027  let Name = AMDGPUAsmVariants.SDWA9;
1028}
1029
1030
1031def DPPAsmParserVariant : AsmParserVariant {
1032  let Variant = AMDGPUAsmVariants.DPP_ID;
1033  let Name = AMDGPUAsmVariants.DPP;
1034}
1035
1036def AMDGPU : Target {
1037  // Pull in Instruction Info:
1038  let InstructionSet = AMDGPUInstrInfo;
1039  let AssemblyParsers = [AMDGPUAsmParser];
1040  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
1041                                VOP3AsmParserVariant,
1042                                SDWAAsmParserVariant,
1043                                SDWA9AsmParserVariant,
1044                                DPPAsmParserVariant];
1045  let AssemblyWriters = [AMDGPUAsmWriter];
1046  let AllowRegisterRenaming = 1;
1047}
1048
1049// Dummy Instruction itineraries for pseudo instructions
1050def ALU_NULL : FuncUnit;
1051def NullALU : InstrItinClass;
1052
1053//===----------------------------------------------------------------------===//
1054// Predicate helper class
1055//===----------------------------------------------------------------------===//
1056
1057def isGFX6 :
1058  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1059  AssemblerPredicate<(all_of FeatureSouthernIslands)>;
1060
1061def isGFX6GFX7 :
1062  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1063            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1064  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
1065
1066def isGFX6GFX7GFX10 :
1067  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1068            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1069            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1070  AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
1071
1072def isGFX7Only :
1073  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1074  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
1075
1076def isGFX7GFX10 :
1077  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1078            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1079  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
1080
1081def isGFX7GFX8 :
1082  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1083            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1084  AssemblerPredicate<(all_of FeatureSouthernIslands, FeatureCIInsts)>;
1085
1086def isGFX7GFX8GFX9 :
1087  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1088            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1089            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1090  AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
1091
1092def isGFX6GFX7GFX8GFX9 :
1093  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1094            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1095            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1096            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1097  AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
1098
1099def isGFX7Plus :
1100  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1101  AssemblerPredicate<(all_of FeatureCIInsts)>;
1102
1103def isGFX8Plus :
1104  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1105  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1106
1107def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1108                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1109  AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1110
1111def isGFX9Plus :
1112  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1113  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1114
1115def isGFX9Only : Predicate <
1116  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1117  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1118
1119def isGFX8GFX9 :
1120  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1121            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1122  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1123
1124def isGFX10Plus :
1125  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1126  AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1127
1128def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1129  AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1130
1131def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1132  AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1133def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1134  AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1135def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1136  AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1137def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1138  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1139
1140def HasFlatScratchSTMode : Predicate<"Subtarget->hasFlatScratchSTMode()">,
1141  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1142
1143def HasGFX10_BEncoding : Predicate<"Subtarget->hasGFX10_BEncoding()">,
1144  AssemblerPredicate<(all_of FeatureGFX10_BEncoding)>;
1145
1146def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1147  AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1148def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1149  AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1150
1151def D16PreservesUnusedBits :
1152  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1153  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1154
1155def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1156def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1157
1158def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1159  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1160
1161def HasLDSFPAtomics : Predicate<"Subtarget->hasLDSFPAtomics()">,
1162  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1163
1164def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1165  AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1166
1167def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1168
1169def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1170  AssemblerPredicate<(all_of Feature16BitInsts)>;
1171def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1172  AssemblerPredicate<(all_of FeatureVOP3P)>;
1173
1174def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
1175def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
1176
1177def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1178  AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1179
1180def HasSDWA9 :
1181  Predicate<"Subtarget->hasSDWA()">,
1182  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1183
1184def HasSDWA10 :
1185  Predicate<"Subtarget->hasSDWA()">,
1186  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1187
1188def HasDPP : Predicate<"Subtarget->hasDPP()">,
1189  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1190
1191def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1192  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1193
1194def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1195  AssemblerPredicate<(all_of FeatureR128A16)>;
1196
1197def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1198  AssemblerPredicate<(all_of FeatureGFX10A16)>;
1199
1200def HasG16 : Predicate<"Subtarget->hasG16()">,
1201  AssemblerPredicate<(all_of FeatureG16)>;
1202
1203def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1204  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1205
1206def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1207  AssemblerPredicate<(all_of FeatureIntClamp)>;
1208
1209def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1210  AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1211
1212def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1213  AssemblerPredicate<(all_of FeatureScalarStores)>;
1214
1215def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1216  AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1217
1218def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1219  AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1220
1221def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1222  AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1223
1224def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1225def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1226def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1227                      AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1228def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1229                AssemblerPredicate<(all_of FeatureMovrel)>;
1230
1231def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1232  AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1233
1234def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1235  AssemblerPredicate<(all_of FeatureDLInsts)>;
1236
1237def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1238  AssemblerPredicate<(all_of FeatureDot1Insts)>;
1239
1240def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1241  AssemblerPredicate<(all_of FeatureDot2Insts)>;
1242
1243def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1244  AssemblerPredicate<(all_of FeatureDot3Insts)>;
1245
1246def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1247  AssemblerPredicate<(all_of FeatureDot4Insts)>;
1248
1249def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1250  AssemblerPredicate<(all_of FeatureDot5Insts)>;
1251
1252def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1253  AssemblerPredicate<(all_of FeatureDot6Insts)>;
1254
1255def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">,
1256  AssemblerPredicate<(all_of FeatureGetWaveIdInst)>;
1257
1258def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1259  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1260
1261def HasSMemTimeInst : Predicate<"Subtarget->hasSMemTimeInst()">,
1262  AssemblerPredicate<(all_of FeatureSMemTimeInst)>;
1263
1264def HasNoSMemTimeInst : Predicate<"!Subtarget->hasSMemTimeInst()">;
1265
1266def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1267  AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1268
1269def HasMadMacF32Insts : Predicate<"Subtarget->hasMadMacF32Insts()">,
1270  AssemblerPredicate<(all_of FeatureMadMacF32Insts)>;
1271
1272def HasFmaLegacy32 : Predicate<"Subtarget->hasGFX10_3Insts()">,
1273  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1274
1275def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1276  AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>;
1277
1278def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
1279  AssemblerPredicate<(all_of FeatureDsSrc2Insts)>;
1280
1281def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">,
1282  AssemblerPredicate<(all_of FeatureOffset3fBug)>;
1283
1284def EnableLateCFGStructurize : Predicate<
1285  "EnableLateStructurizeCFG">;
1286
1287def EnableFlatScratch : Predicate<"Subtarget->enableFlatScratch()">;
1288
1289def DisableFlatScratch : Predicate<"!Subtarget->enableFlatScratch()">;
1290
1291// Include AMDGPU TD files
1292include "SISchedule.td"
1293include "GCNProcessors.td"
1294include "AMDGPUInstrInfo.td"
1295include "SIRegisterInfo.td"
1296include "AMDGPURegisterBanks.td"
1297include "AMDGPUInstructions.td"
1298include "SIInstrInfo.td"
1299include "AMDGPUCallingConv.td"
1300include "AMDGPUSearchableTables.td"
1301