1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===------------------------------------------------------------===//
9
10include "llvm/Target/Target.td"
11
12//===------------------------------------------------------------===//
13// Subtarget Features (device properties)
14//===------------------------------------------------------------===//
15
16def FeatureFP64 : SubtargetFeature<"fp64",
17  "FP64",
18  "true",
19  "Enable double precision operations"
20>;
21
22def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
23  "FastFMAF32",
24  "true",
25  "Assuming f32 fma is at least as fast as mul + add"
26>;
27
28def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
29  "HalfRate64Ops",
30  "true",
31  "Most fp64 instructions are half rate instead of quarter"
32>;
33
34def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
35  "R600ALUInst",
36  "false",
37  "Older version of ALU instructions encoding"
38>;
39
40def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
41  "HasVertexCache",
42  "true",
43  "Specify use of dedicated vertex cache"
44>;
45
46def FeatureCaymanISA : SubtargetFeature<"caymanISA",
47  "CaymanISA",
48  "true",
49  "Use Cayman ISA"
50>;
51
52def FeatureCFALUBug : SubtargetFeature<"cfalubug",
53  "CFALUBug",
54  "true",
55  "GPU has CF_ALU bug"
56>;
57
58def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
59  "FlatAddressSpace",
60  "true",
61  "Support flat address space"
62>;
63
64def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
65  "FlatInstOffsets",
66  "true",
67  "Flat instructions have immediate offset addressing mode"
68>;
69
70def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
71  "FlatGlobalInsts",
72  "true",
73  "Have global_* flat memory instructions"
74>;
75
76def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
77  "FlatScratchInsts",
78  "true",
79  "Have scratch_* flat memory instructions"
80>;
81
82def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
83  "UnalignedBufferAccess",
84  "true",
85  "Support unaligned global loads and stores"
86>;
87
88def FeatureTrapHandler: SubtargetFeature<"trap-handler",
89  "TrapHandler",
90  "true",
91  "Trap handler support"
92>;
93
94def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
95  "UnalignedScratchAccess",
96  "true",
97  "Support unaligned scratch loads and stores"
98>;
99
100def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
101  "HasApertureRegs",
102  "true",
103  "Has Memory Aperture Base and Size Registers"
104>;
105
106// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
107// XNACK. The current default kernel driver setting is:
108// - graphics ring: XNACK disabled
109// - compute ring: XNACK enabled
110//
111// If XNACK is enabled, the VMEM latency can be worse.
112// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
113def FeatureXNACK : SubtargetFeature<"xnack",
114  "EnableXNACK",
115  "true",
116  "Enable XNACK support"
117>;
118
119def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
120  "SGPRInitBug",
121  "true",
122  "VI SGPR initilization bug requiring a fixed SGPR allocation size"
123>;
124
125class SubtargetFeatureFetchLimit <string Value> :
126                          SubtargetFeature <"fetch"#Value,
127  "TexVTXClauseSize",
128  Value,
129  "Limit the maximum number of fetches in a clause to "#Value
130>;
131
132def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
133def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
134
135class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
136  "wavefrontsize"#Value,
137  "WavefrontSize",
138  !cast<string>(Value),
139  "The number of threads per wavefront"
140>;
141
142def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
143def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
144def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
145
146class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
147  "ldsbankcount"#Value,
148  "LDSBankCount",
149  !cast<string>(Value),
150  "The number of LDS banks per compute unit."
151>;
152
153def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
154def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
155
156class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
157  "localmemorysize"#Value,
158  "LocalMemorySize",
159  !cast<string>(Value),
160  "The size of local memory in bytes"
161>;
162
163def FeatureGCN : SubtargetFeature<"gcn",
164  "IsGCN",
165  "true",
166  "GCN or newer GPU"
167>;
168
169def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",
170  "GCN1Encoding",
171  "true",
172  "Encoding format for SI and CI"
173>;
174
175def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
176  "GCN3Encoding",
177  "true",
178  "Encoding format for VI"
179>;
180
181def FeatureCIInsts : SubtargetFeature<"ci-insts",
182  "CIInsts",
183  "true",
184  "Additional intstructions for CI+"
185>;
186
187def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
188  "GFX9Insts",
189  "true",
190  "Additional intstructions for GFX9+"
191>;
192
193def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
194  "HasSMemRealTime",
195  "true",
196  "Has s_memrealtime instruction"
197>;
198
199def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
200  "HasInv2PiInlineImm",
201  "true",
202  "Has 1 / (2 * pi) as inline immediate"
203>;
204
205def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
206  "Has16BitInsts",
207  "true",
208  "Has i16/f16 instructions"
209>;
210
211def FeatureVOP3P : SubtargetFeature<"vop3p",
212  "HasVOP3PInsts",
213  "true",
214  "Has VOP3P packed instructions"
215>;
216
217def FeatureMovrel : SubtargetFeature<"movrel",
218  "HasMovrel",
219  "true",
220  "Has v_movrel*_b32 instructions"
221>;
222
223def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
224  "HasVGPRIndexMode",
225  "true",
226  "Has VGPR mode register indexing"
227>;
228
229def FeatureScalarStores : SubtargetFeature<"scalar-stores",
230  "HasScalarStores",
231  "true",
232  "Has store scalar memory instructions"
233>;
234
235def FeatureSDWA : SubtargetFeature<"sdwa",
236  "HasSDWA",
237  "true",
238  "Support SDWA (Sub-DWORD Addressing) extension"
239>;
240
241def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
242  "HasSDWAOmod",
243  "true",
244  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
245>;
246
247def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
248  "HasSDWAScalar",
249  "true",
250  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
251>;
252
253def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
254  "HasSDWASdst",
255  "true",
256  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
257>;
258
259def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
260  "HasSDWAMac",
261  "true",
262  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
263>;
264
265def FeatureSDWAClampVOPC : SubtargetFeature<"sdwa-clamp-vopc",
266  "HasSDWAClampVOPC",
267  "true",
268  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
269>;
270
271def FeatureDPP : SubtargetFeature<"dpp",
272  "HasDPP",
273  "true",
274  "Support DPP (Data Parallel Primitives) extension"
275>;
276
277//===------------------------------------------------------------===//
278// Subtarget Features (options and debugging)
279//===------------------------------------------------------------===//
280
281// Some instructions do not support denormals despite this flag. Using
282// fp32 denormals also causes instructions to run at the double
283// precision rate for the device.
284def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
285  "FP32Denormals",
286  "true",
287  "Enable single precision denormal handling"
288>;
289
290// Denormal handling for fp64 and fp16 is controlled by the same
291// config register when fp16 supported.
292// TODO: Do we need a separate f16 setting when not legal?
293def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
294  "FP64FP16Denormals",
295  "true",
296  "Enable double and half precision denormal handling",
297  [FeatureFP64]
298>;
299
300def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
301  "FP64FP16Denormals",
302  "true",
303  "Enable double and half precision denormal handling",
304  [FeatureFP64, FeatureFP64FP16Denormals]
305>;
306
307def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
308  "FP64FP16Denormals",
309  "true",
310  "Enable half precision denormal handling",
311  [FeatureFP64FP16Denormals]
312>;
313
314def FeatureDX10Clamp : SubtargetFeature<"dx10-clamp",
315  "DX10Clamp",
316  "true",
317  "clamp modifier clamps NaNs to 0.0"
318>;
319
320def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
321  "FPExceptions",
322  "true",
323  "Enable floating point exceptions"
324>;
325
326class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
327  "max-private-element-size-"#size,
328  "MaxPrivateElementSize",
329  !cast<string>(size),
330  "Maximum private access size may be "#size
331>;
332
333def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
334def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
335def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
336
337def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
338  "EnableVGPRSpilling",
339  "true",
340  "Enable spilling of VGPRs to scratch memory"
341>;
342
343def FeatureDumpCode : SubtargetFeature <"DumpCode",
344  "DumpCode",
345  "true",
346  "Dump MachineInstrs in the CodeEmitter"
347>;
348
349def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
350  "DumpCode",
351  "true",
352  "Dump MachineInstrs in the CodeEmitter"
353>;
354
355def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
356  "EnablePromoteAlloca",
357  "true",
358  "Enable promote alloca pass"
359>;
360
361// XXX - This should probably be removed once enabled by default
362def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
363  "EnableLoadStoreOpt",
364  "true",
365  "Enable SI load/store optimizer pass"
366>;
367
368// Performance debugging feature. Allow using DS instruction immediate
369// offsets even if the base pointer can't be proven to be base. On SI,
370// base pointer values that won't give the same result as a 16-bit add
371// are not safe to fold, but this will override the conservative test
372// for the base pointer.
373def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
374  "unsafe-ds-offset-folding",
375  "EnableUnsafeDSOffsetFolding",
376  "true",
377  "Force using DS instruction immediate offsets on SI"
378>;
379
380def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
381  "EnableSIScheduler",
382  "true",
383  "Enable SI Machine Scheduler"
384>;
385
386// Unless +-flat-for-global is specified, turn on FlatForGlobal for
387// all OS-es on VI and newer hardware to avoid assertion failures due
388// to missing ADDR64 variants of MUBUF instructions.
389// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
390// instructions.
391
392def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
393  "FlatForGlobal",
394  "true",
395  "Force to generate flat instruction for global"
396>;
397
398def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
399  "auto-waitcnt-before-barrier",
400  "AutoWaitcntBeforeBarrier",
401  "true",
402  "Hardware automatically inserts waitcnt before barrier"
403>;
404
405// Dummy feature used to disable assembler instructions.
406def FeatureDisable : SubtargetFeature<"",
407  "FeatureDisable","true",
408  "Dummy feature to disable assembler instructions"
409>;
410
411class SubtargetFeatureGeneration <string Value,
412                                  list<SubtargetFeature> Implies> :
413        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
414                          Value#" GPU generation", Implies>;
415
416def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
417def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
418def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
419
420def FeatureR600 : SubtargetFeatureGeneration<"R600",
421  [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]
422>;
423
424def FeatureR700 : SubtargetFeatureGeneration<"R700",
425  [FeatureFetchLimit16, FeatureLocalMemorySize0]
426>;
427
428def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
429  [FeatureFetchLimit16, FeatureLocalMemorySize32768]
430>;
431
432def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
433  [FeatureFetchLimit16, FeatureWavefrontSize64,
434   FeatureLocalMemorySize32768]
435>;
436
437def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
438  [FeatureFP64, FeatureLocalMemorySize32768,
439  FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
440  FeatureLDSBankCount32, FeatureMovrel]
441>;
442
443def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
444  [FeatureFP64, FeatureLocalMemorySize65536,
445  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
446  FeatureGCN1Encoding, FeatureCIInsts, FeatureMovrel]
447>;
448
449def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
450  [FeatureFP64, FeatureLocalMemorySize65536,
451   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
452   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
453   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
454   FeatureScalarStores, FeatureInv2PiInlineImm,
455   FeatureSDWA, FeatureSDWAClampVOPC, FeatureSDWAMac, FeatureDPP
456  ]
457>;
458
459def FeatureGFX9 : SubtargetFeatureGeneration<"GFX9",
460  [FeatureFP64, FeatureLocalMemorySize65536,
461   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
462   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
463   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
464   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
465   FeatureFastFMAF32, FeatureDPP,
466   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
467   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts
468  ]
469>;
470
471class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
472                                  list<SubtargetFeature> Implies>
473                                 : SubtargetFeature <
474  "isaver"#Major#"."#Minor#"."#Stepping,
475  "IsaVersion",
476  "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
477  "Instruction set version number",
478  Implies
479>;
480
481def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
482  [FeatureSouthernIslands,
483   FeatureFastFMAF32,
484   HalfRate64Ops,
485   FeatureLDSBankCount32]>;
486
487def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
488  [FeatureSouthernIslands,
489   FeatureLDSBankCount32]>;
490
491def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
492  [FeatureSeaIslands,
493   FeatureLDSBankCount32]>;
494
495def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
496  [FeatureSeaIslands,
497   HalfRate64Ops,
498   FeatureLDSBankCount32,
499   FeatureFastFMAF32]>;
500
501def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
502  [FeatureSeaIslands,
503   FeatureLDSBankCount16]>;
504
505def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
506  [FeatureSeaIslands,
507   FeatureLDSBankCount16]>;
508
509def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0,
510  [FeatureVolcanicIslands,
511   FeatureLDSBankCount32,
512   FeatureSGPRInitBug]>;
513
514def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
515  [FeatureVolcanicIslands,
516   FeatureLDSBankCount32,
517   FeatureXNACK]>;
518
519def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
520  [FeatureVolcanicIslands,
521   FeatureLDSBankCount32,
522   FeatureSGPRInitBug]>;
523
524def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
525  [FeatureVolcanicIslands,
526   FeatureLDSBankCount32]>;
527
528def FeatureISAVersion8_0_4 : SubtargetFeatureISAVersion <8,0,4,
529  [FeatureVolcanicIslands,
530   FeatureLDSBankCount32]>;
531
532def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
533  [FeatureVolcanicIslands,
534   FeatureLDSBankCount16,
535   FeatureXNACK]>;
536
537def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
538  [FeatureGFX9,
539   FeatureLDSBankCount32]>;
540
541def FeatureISAVersion9_0_1 : SubtargetFeatureISAVersion <9,0,1,
542  [FeatureGFX9,
543   FeatureLDSBankCount32,
544   FeatureXNACK]>;
545
546def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
547  [FeatureGFX9,
548   FeatureLDSBankCount32]>;
549
550def FeatureISAVersion9_0_3 : SubtargetFeatureISAVersion <9,0,3,
551  [FeatureGFX9,
552   FeatureLDSBankCount32,
553   FeatureXNACK]>;
554
555//===----------------------------------------------------------------------===//
556// Debugger related subtarget features.
557//===----------------------------------------------------------------------===//
558
559def FeatureDebuggerInsertNops : SubtargetFeature<
560  "amdgpu-debugger-insert-nops",
561  "DebuggerInsertNops",
562  "true",
563  "Insert one nop instruction for each high level source statement"
564>;
565
566def FeatureDebuggerReserveRegs : SubtargetFeature<
567  "amdgpu-debugger-reserve-regs",
568  "DebuggerReserveRegs",
569  "true",
570  "Reserve registers for debugger usage"
571>;
572
573def FeatureDebuggerEmitPrologue : SubtargetFeature<
574  "amdgpu-debugger-emit-prologue",
575  "DebuggerEmitPrologue",
576  "true",
577  "Emit debugger prologue"
578>;
579
580//===----------------------------------------------------------------------===//
581
582def AMDGPUInstrInfo : InstrInfo {
583  let guessInstructionProperties = 1;
584  let noNamedPositionallyEncodedOperands = 1;
585}
586
587def AMDGPUAsmParser : AsmParser {
588  // Some of the R600 registers have the same name, so this crashes.
589  // For example T0_XYZW and T0_XY both have the asm name T0.
590  let ShouldEmitMatchRegisterName = 0;
591}
592
593def AMDGPUAsmWriter : AsmWriter {
594  int PassSubtarget = 1;
595}
596
597def AMDGPUAsmVariants {
598  string Default = "Default";
599  int Default_ID = 0;
600  string VOP3 = "VOP3";
601  int VOP3_ID = 1;
602  string SDWA = "SDWA";
603  int SDWA_ID = 2;
604  string SDWA9 = "SDWA9";
605  int SDWA9_ID = 3;
606  string DPP = "DPP";
607  int DPP_ID = 4;
608  string Disable = "Disable";
609  int Disable_ID = 5;
610}
611
612def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
613  let Variant = AMDGPUAsmVariants.Default_ID;
614  let Name = AMDGPUAsmVariants.Default;
615}
616
617def VOP3AsmParserVariant : AsmParserVariant {
618  let Variant = AMDGPUAsmVariants.VOP3_ID;
619  let Name = AMDGPUAsmVariants.VOP3;
620}
621
622def SDWAAsmParserVariant : AsmParserVariant {
623  let Variant = AMDGPUAsmVariants.SDWA_ID;
624  let Name = AMDGPUAsmVariants.SDWA;
625}
626
627def SDWA9AsmParserVariant : AsmParserVariant {
628  let Variant = AMDGPUAsmVariants.SDWA9_ID;
629  let Name = AMDGPUAsmVariants.SDWA9;
630}
631
632
633def DPPAsmParserVariant : AsmParserVariant {
634  let Variant = AMDGPUAsmVariants.DPP_ID;
635  let Name = AMDGPUAsmVariants.DPP;
636}
637
638def AMDGPU : Target {
639  // Pull in Instruction Info:
640  let InstructionSet = AMDGPUInstrInfo;
641  let AssemblyParsers = [AMDGPUAsmParser];
642  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
643                                VOP3AsmParserVariant,
644                                SDWAAsmParserVariant,
645                                SDWA9AsmParserVariant,
646                                DPPAsmParserVariant];
647  let AssemblyWriters = [AMDGPUAsmWriter];
648}
649
650// Dummy Instruction itineraries for pseudo instructions
651def ALU_NULL : FuncUnit;
652def NullALU : InstrItinClass;
653
654//===----------------------------------------------------------------------===//
655// Predicate helper class
656//===----------------------------------------------------------------------===//
657
658def TruePredicate : Predicate<"true">;
659
660def isSICI : Predicate<
661  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
662  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
663>, AssemblerPredicate<"FeatureGCN1Encoding">;
664
665def isVI : Predicate <
666  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
667  AssemblerPredicate<"FeatureGCN3Encoding">;
668
669def isGFX9 : Predicate <
670  "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
671  AssemblerPredicate<"FeatureGFX9Insts">;
672
673// TODO: Either the name to be changed or we simply use IsCI!
674def isCIVI : Predicate <
675  "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
676  AssemblerPredicate<"FeatureCIInsts">;
677
678def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
679  AssemblerPredicate<"FeatureFlatAddressSpace">;
680
681def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
682  AssemblerPredicate<"FeatureFlatGlobalInsts">;
683
684def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
685  AssemblerPredicate<"Feature16BitInsts">;
686def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
687  AssemblerPredicate<"FeatureVOP3P">;
688
689def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
690  AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
691
692def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
693  AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
694
695def HasDPP : Predicate<"Subtarget->hasDPP()">,
696  AssemblerPredicate<"FeatureDPP">;
697
698class PredicateControl {
699  Predicate SubtargetPredicate;
700  Predicate SIAssemblerPredicate = isSICI;
701  Predicate VIAssemblerPredicate = isVI;
702  list<Predicate> AssemblerPredicates = [];
703  Predicate AssemblerPredicate = TruePredicate;
704  list<Predicate> OtherPredicates = [];
705  list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
706                                            AssemblerPredicates,
707                                            OtherPredicates);
708}
709
710// Include AMDGPU TD files
711include "R600Schedule.td"
712include "SISchedule.td"
713include "Processors.td"
714include "AMDGPUInstrInfo.td"
715include "AMDGPUIntrinsics.td"
716include "AMDGPURegisterInfo.td"
717include "AMDGPURegisterBanks.td"
718include "AMDGPUInstructions.td"
719include "AMDGPUCallingConv.td"
720