1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===------------------------------------------------------------===//
9
10include "llvm/Target/Target.td"
11
12//===------------------------------------------------------------===//
13// Subtarget Features (device properties)
14//===------------------------------------------------------------===//
15
16def FeatureFP64 : SubtargetFeature<"fp64",
17  "FP64",
18  "true",
19  "Enable double precision operations"
20>;
21
22def FeatureFMA : SubtargetFeature<"fmaf",
23  "FMA",
24  "true",
25  "Enable single precision FMA (not as fast as mul+add, but fused)"
26>;
27
28def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
29  "FastFMAF32",
30  "true",
31  "Assuming f32 fma is at least as fast as mul + add"
32>;
33
34def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
35  "MIMG_R128",
36  "true",
37  "Support 128-bit texture resources"
38>;
39
40def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
41  "HalfRate64Ops",
42  "true",
43  "Most fp64 instructions are half rate instead of quarter"
44>;
45
46def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
47  "R600ALUInst",
48  "false",
49  "Older version of ALU instructions encoding"
50>;
51
52def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
53  "HasVertexCache",
54  "true",
55  "Specify use of dedicated vertex cache"
56>;
57
58def FeatureCaymanISA : SubtargetFeature<"caymanISA",
59  "CaymanISA",
60  "true",
61  "Use Cayman ISA"
62>;
63
64def FeatureCFALUBug : SubtargetFeature<"cfalubug",
65  "CFALUBug",
66  "true",
67  "GPU has CF_ALU bug"
68>;
69
70def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
71  "FlatAddressSpace",
72  "true",
73  "Support flat address space"
74>;
75
76def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
77  "FlatInstOffsets",
78  "true",
79  "Flat instructions have immediate offset addressing mode"
80>;
81
82def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
83  "FlatGlobalInsts",
84  "true",
85  "Have global_* flat memory instructions"
86>;
87
88def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
89  "FlatScratchInsts",
90  "true",
91  "Have scratch_* flat memory instructions"
92>;
93
94def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
95  "AddNoCarryInsts",
96  "true",
97  "Have VALU add/sub instructions without carry out"
98>;
99
100def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
101  "UnalignedBufferAccess",
102  "true",
103  "Support unaligned global loads and stores"
104>;
105
106def FeatureTrapHandler: SubtargetFeature<"trap-handler",
107  "TrapHandler",
108  "true",
109  "Trap handler support"
110>;
111
112def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
113  "UnalignedScratchAccess",
114  "true",
115  "Support unaligned scratch loads and stores"
116>;
117
118def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
119  "HasApertureRegs",
120  "true",
121  "Has Memory Aperture Base and Size Registers"
122>;
123
124def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
125  "HasMadMixInsts",
126  "true",
127  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
128>;
129
130// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
131// XNACK. The current default kernel driver setting is:
132// - graphics ring: XNACK disabled
133// - compute ring: XNACK enabled
134//
135// If XNACK is enabled, the VMEM latency can be worse.
136// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
137def FeatureXNACK : SubtargetFeature<"xnack",
138  "EnableXNACK",
139  "true",
140  "Enable XNACK support"
141>;
142
143def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
144  "SGPRInitBug",
145  "true",
146  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
147>;
148
149class SubtargetFeatureFetchLimit <string Value> :
150                          SubtargetFeature <"fetch"#Value,
151  "TexVTXClauseSize",
152  Value,
153  "Limit the maximum number of fetches in a clause to "#Value
154>;
155
156def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
157def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
158
159class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
160  "wavefrontsize"#Value,
161  "WavefrontSize",
162  !cast<string>(Value),
163  "The number of threads per wavefront"
164>;
165
166def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
167def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
168def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
169
170class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
171  "ldsbankcount"#Value,
172  "LDSBankCount",
173  !cast<string>(Value),
174  "The number of LDS banks per compute unit."
175>;
176
177def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
178def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
179
180class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
181  "localmemorysize"#Value,
182  "LocalMemorySize",
183  !cast<string>(Value),
184  "The size of local memory in bytes"
185>;
186
187def FeatureGCN : SubtargetFeature<"gcn",
188  "IsGCN",
189  "true",
190  "GCN or newer GPU"
191>;
192
193def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
194  "GCN3Encoding",
195  "true",
196  "Encoding format for VI"
197>;
198
199def FeatureCIInsts : SubtargetFeature<"ci-insts",
200  "CIInsts",
201  "true",
202  "Additional instructions for CI+"
203>;
204
205def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
206  "GFX9Insts",
207  "true",
208  "Additional instructions for GFX9+"
209>;
210
211def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
212  "HasSMemRealTime",
213  "true",
214  "Has s_memrealtime instruction"
215>;
216
217def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
218  "HasInv2PiInlineImm",
219  "true",
220  "Has 1 / (2 * pi) as inline immediate"
221>;
222
223def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
224  "Has16BitInsts",
225  "true",
226  "Has i16/f16 instructions"
227>;
228
229def FeatureVOP3P : SubtargetFeature<"vop3p",
230  "HasVOP3PInsts",
231  "true",
232  "Has VOP3P packed instructions"
233>;
234
235def FeatureMovrel : SubtargetFeature<"movrel",
236  "HasMovrel",
237  "true",
238  "Has v_movrel*_b32 instructions"
239>;
240
241def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
242  "HasVGPRIndexMode",
243  "true",
244  "Has VGPR mode register indexing"
245>;
246
247def FeatureScalarStores : SubtargetFeature<"scalar-stores",
248  "HasScalarStores",
249  "true",
250  "Has store scalar memory instructions"
251>;
252
253def FeatureSDWA : SubtargetFeature<"sdwa",
254  "HasSDWA",
255  "true",
256  "Support SDWA (Sub-DWORD Addressing) extension"
257>;
258
259def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
260  "HasSDWAOmod",
261  "true",
262  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
263>;
264
265def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
266  "HasSDWAScalar",
267  "true",
268  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
269>;
270
271def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
272  "HasSDWASdst",
273  "true",
274  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
275>;
276
277def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
278  "HasSDWAMac",
279  "true",
280  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
281>;
282
283def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
284  "HasSDWAOutModsVOPC",
285  "true",
286  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
287>;
288
289def FeatureDPP : SubtargetFeature<"dpp",
290  "HasDPP",
291  "true",
292  "Support DPP (Data Parallel Primitives) extension"
293>;
294
295def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
296  "HasIntClamp",
297  "true",
298  "Support clamp for integer destination"
299>;
300
301def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
302  "HasUnpackedD16VMem",
303  "true",
304  "Has unpacked d16 vmem instructions"
305>;
306
307//===------------------------------------------------------------===//
308// Subtarget Features (options and debugging)
309//===------------------------------------------------------------===//
310
311// Some instructions do not support denormals despite this flag. Using
312// fp32 denormals also causes instructions to run at the double
313// precision rate for the device.
314def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
315  "FP32Denormals",
316  "true",
317  "Enable single precision denormal handling"
318>;
319
320// Denormal handling for fp64 and fp16 is controlled by the same
321// config register when fp16 supported.
322// TODO: Do we need a separate f16 setting when not legal?
323def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
324  "FP64FP16Denormals",
325  "true",
326  "Enable double and half precision denormal handling",
327  [FeatureFP64]
328>;
329
330def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
331  "FP64FP16Denormals",
332  "true",
333  "Enable double and half precision denormal handling",
334  [FeatureFP64, FeatureFP64FP16Denormals]
335>;
336
337def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
338  "FP64FP16Denormals",
339  "true",
340  "Enable half precision denormal handling",
341  [FeatureFP64FP16Denormals]
342>;
343
344def FeatureDX10Clamp : SubtargetFeature<"dx10-clamp",
345  "DX10Clamp",
346  "true",
347  "clamp modifier clamps NaNs to 0.0"
348>;
349
350def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
351  "FPExceptions",
352  "true",
353  "Enable floating point exceptions"
354>;
355
356class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
357  "max-private-element-size-"#size,
358  "MaxPrivateElementSize",
359  !cast<string>(size),
360  "Maximum private access size may be "#size
361>;
362
363def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
364def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
365def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
366
367def FeatureEnableHugePrivateBuffer : SubtargetFeature<
368  "huge-private-buffer",
369  "EnableHugePrivateBuffer",
370  "true",
371  "Enable private/scratch buffer sizes greater than 128 GB"
372>;
373
374def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
375  "EnableVGPRSpilling",
376  "true",
377  "Enable spilling of VGPRs to scratch memory"
378>;
379
380def FeatureDumpCode : SubtargetFeature <"DumpCode",
381  "DumpCode",
382  "true",
383  "Dump MachineInstrs in the CodeEmitter"
384>;
385
386def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
387  "DumpCode",
388  "true",
389  "Dump MachineInstrs in the CodeEmitter"
390>;
391
392def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
393  "EnablePromoteAlloca",
394  "true",
395  "Enable promote alloca pass"
396>;
397
398// XXX - This should probably be removed once enabled by default
399def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
400  "EnableLoadStoreOpt",
401  "true",
402  "Enable SI load/store optimizer pass"
403>;
404
405// Performance debugging feature. Allow using DS instruction immediate
406// offsets even if the base pointer can't be proven to be base. On SI,
407// base pointer values that won't give the same result as a 16-bit add
408// are not safe to fold, but this will override the conservative test
409// for the base pointer.
410def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
411  "unsafe-ds-offset-folding",
412  "EnableUnsafeDSOffsetFolding",
413  "true",
414  "Force using DS instruction immediate offsets on SI"
415>;
416
417def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
418  "EnableSIScheduler",
419  "true",
420  "Enable SI Machine Scheduler"
421>;
422
423// Unless +-flat-for-global is specified, turn on FlatForGlobal for
424// all OS-es on VI and newer hardware to avoid assertion failures due
425// to missing ADDR64 variants of MUBUF instructions.
426// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
427// instructions.
428
429def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
430  "FlatForGlobal",
431  "true",
432  "Force to generate flat instruction for global"
433>;
434
435def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
436  "auto-waitcnt-before-barrier",
437  "AutoWaitcntBeforeBarrier",
438  "true",
439  "Hardware automatically inserts waitcnt before barrier"
440>;
441
442def FeatureCodeObjectV3 : SubtargetFeature <
443  "code-object-v3",
444  "CodeObjectV3",
445  "true",
446  "Generate code object version 3"
447>;
448
449// Dummy feature used to disable assembler instructions.
450def FeatureDisable : SubtargetFeature<"",
451  "FeatureDisable","true",
452  "Dummy feature to disable assembler instructions"
453>;
454
455class SubtargetFeatureGeneration <string Value,
456                                  list<SubtargetFeature> Implies> :
457        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
458                          Value#" GPU generation", Implies>;
459
460def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
461def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
462def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
463
464def FeatureR600 : SubtargetFeatureGeneration<"R600",
465  [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]
466>;
467
468def FeatureR700 : SubtargetFeatureGeneration<"R700",
469  [FeatureFetchLimit16, FeatureLocalMemorySize0]
470>;
471
472def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
473  [FeatureFetchLimit16, FeatureLocalMemorySize32768]
474>;
475
476def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
477  [FeatureFetchLimit16, FeatureWavefrontSize64,
478   FeatureLocalMemorySize32768]
479>;
480
481def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
482  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
483  FeatureWavefrontSize64, FeatureGCN,
484  FeatureLDSBankCount32, FeatureMovrel]
485>;
486
487def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
488  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
489  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
490  FeatureCIInsts, FeatureMovrel]
491>;
492
493def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
494  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
495   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
496   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
497   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
498   FeatureScalarStores, FeatureInv2PiInlineImm,
499   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
500   FeatureIntClamp
501  ]
502>;
503
504def FeatureGFX9 : SubtargetFeatureGeneration<"GFX9",
505  [FeatureFP64, FeatureLocalMemorySize65536,
506   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
507   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
508   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
509   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
510   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
511   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
512   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
513   FeatureAddNoCarryInsts
514  ]
515>;
516
517class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
518                                  list<SubtargetFeature> Implies>
519                                 : SubtargetFeature <
520  "isaver"#Major#"."#Minor#"."#Stepping,
521  "IsaVersion",
522  "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
523  "Instruction set version number",
524  Implies
525>;
526
527def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
528  [FeatureSouthernIslands,
529   FeatureFastFMAF32,
530   HalfRate64Ops,
531   FeatureLDSBankCount32]>;
532
533def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
534  [FeatureSouthernIslands,
535   FeatureLDSBankCount32]>;
536
537def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
538  [FeatureSeaIslands,
539   FeatureLDSBankCount32]>;
540
541def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
542  [FeatureSeaIslands,
543   HalfRate64Ops,
544   FeatureLDSBankCount32,
545   FeatureFastFMAF32]>;
546
547def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
548  [FeatureSeaIslands,
549   FeatureLDSBankCount16]>;
550
551def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
552  [FeatureSeaIslands,
553   FeatureLDSBankCount16]>;
554
555def FeatureISAVersion7_0_4 : SubtargetFeatureISAVersion <7,0,4,
556  [FeatureSeaIslands,
557   FeatureLDSBankCount32]>;
558
559def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0,
560  [FeatureVolcanicIslands,
561   FeatureLDSBankCount32,
562   FeatureSGPRInitBug,
563   FeatureUnpackedD16VMem]>;
564
565def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
566  [FeatureVolcanicIslands,
567   FeatureFastFMAF32,
568   HalfRate64Ops,
569   FeatureLDSBankCount32,
570   FeatureXNACK,
571   FeatureUnpackedD16VMem]>;
572
573def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
574  [FeatureVolcanicIslands,
575   FeatureLDSBankCount32,
576   FeatureSGPRInitBug,
577   FeatureUnpackedD16VMem]>;
578
579def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
580  [FeatureVolcanicIslands,
581   FeatureLDSBankCount32,
582   FeatureUnpackedD16VMem]>;
583
584def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
585  [FeatureVolcanicIslands,
586   FeatureLDSBankCount16,
587   FeatureXNACK]>;
588
589def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
590  [FeatureGFX9,
591   FeatureMadMixInsts,
592   FeatureLDSBankCount32
593   ]>;
594
595def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
596  [FeatureGFX9,
597   FeatureMadMixInsts,
598   FeatureLDSBankCount32
599   ]>;
600
601//===----------------------------------------------------------------------===//
602// Debugger related subtarget features.
603//===----------------------------------------------------------------------===//
604
605def FeatureDebuggerInsertNops : SubtargetFeature<
606  "amdgpu-debugger-insert-nops",
607  "DebuggerInsertNops",
608  "true",
609  "Insert one nop instruction for each high level source statement"
610>;
611
612def FeatureDebuggerReserveRegs : SubtargetFeature<
613  "amdgpu-debugger-reserve-regs",
614  "DebuggerReserveRegs",
615  "true",
616  "Reserve registers for debugger usage"
617>;
618
619def FeatureDebuggerEmitPrologue : SubtargetFeature<
620  "amdgpu-debugger-emit-prologue",
621  "DebuggerEmitPrologue",
622  "true",
623  "Emit debugger prologue"
624>;
625
626//===----------------------------------------------------------------------===//
627
628def AMDGPUInstrInfo : InstrInfo {
629  let guessInstructionProperties = 1;
630  let noNamedPositionallyEncodedOperands = 1;
631}
632
633def AMDGPUAsmParser : AsmParser {
634  // Some of the R600 registers have the same name, so this crashes.
635  // For example T0_XYZW and T0_XY both have the asm name T0.
636  let ShouldEmitMatchRegisterName = 0;
637}
638
639def AMDGPUAsmWriter : AsmWriter {
640  int PassSubtarget = 1;
641}
642
643def AMDGPUAsmVariants {
644  string Default = "Default";
645  int Default_ID = 0;
646  string VOP3 = "VOP3";
647  int VOP3_ID = 1;
648  string SDWA = "SDWA";
649  int SDWA_ID = 2;
650  string SDWA9 = "SDWA9";
651  int SDWA9_ID = 3;
652  string DPP = "DPP";
653  int DPP_ID = 4;
654  string Disable = "Disable";
655  int Disable_ID = 5;
656}
657
658def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
659  let Variant = AMDGPUAsmVariants.Default_ID;
660  let Name = AMDGPUAsmVariants.Default;
661}
662
663def VOP3AsmParserVariant : AsmParserVariant {
664  let Variant = AMDGPUAsmVariants.VOP3_ID;
665  let Name = AMDGPUAsmVariants.VOP3;
666}
667
668def SDWAAsmParserVariant : AsmParserVariant {
669  let Variant = AMDGPUAsmVariants.SDWA_ID;
670  let Name = AMDGPUAsmVariants.SDWA;
671}
672
673def SDWA9AsmParserVariant : AsmParserVariant {
674  let Variant = AMDGPUAsmVariants.SDWA9_ID;
675  let Name = AMDGPUAsmVariants.SDWA9;
676}
677
678
679def DPPAsmParserVariant : AsmParserVariant {
680  let Variant = AMDGPUAsmVariants.DPP_ID;
681  let Name = AMDGPUAsmVariants.DPP;
682}
683
684def AMDGPU : Target {
685  // Pull in Instruction Info:
686  let InstructionSet = AMDGPUInstrInfo;
687  let AssemblyParsers = [AMDGPUAsmParser];
688  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
689                                VOP3AsmParserVariant,
690                                SDWAAsmParserVariant,
691                                SDWA9AsmParserVariant,
692                                DPPAsmParserVariant];
693  let AssemblyWriters = [AMDGPUAsmWriter];
694}
695
696// Dummy Instruction itineraries for pseudo instructions
697def ALU_NULL : FuncUnit;
698def NullALU : InstrItinClass;
699
700//===----------------------------------------------------------------------===//
701// Predicate helper class
702//===----------------------------------------------------------------------===//
703
704def TruePredicate : Predicate<"true">;
705
706def isSICI : Predicate<
707  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
708  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
709>, AssemblerPredicate<"!FeatureGCN3Encoding">;
710
711def isVI : Predicate <
712  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
713  AssemblerPredicate<"FeatureGCN3Encoding">;
714
715def isGFX9 : Predicate <
716  "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
717  AssemblerPredicate<"FeatureGFX9Insts">;
718
719// TODO: Either the name to be changed or we simply use IsCI!
720def isCIVI : Predicate <
721  "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
722  AssemblerPredicate<"FeatureCIInsts">;
723
724def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
725  AssemblerPredicate<"FeatureFlatAddressSpace">;
726
727def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
728  AssemblerPredicate<"FeatureFlatGlobalInsts">;
729def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
730  AssemblerPredicate<"FeatureFlatScratchInsts">;
731def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
732  AssemblerPredicate<"FeatureGFX9Insts">;
733
734def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
735  AssemblerPredicate<"FeatureUnpackedD16VMem">;
736def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
737  AssemblerPredicate<"!FeatureUnpackedD16VMem">;
738
739
740def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
741def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
742
743def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
744  AssemblerPredicate<"FeatureGFX9Insts">;
745
746def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarryInsts()">,
747  AssemblerPredicate<"FeatureAddNoCarryInsts">;
748
749def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarryInsts()">,
750  AssemblerPredicate<"!FeatureAddNoCarryInsts">;
751
752def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
753  AssemblerPredicate<"Feature16BitInsts">;
754def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
755  AssemblerPredicate<"FeatureVOP3P">;
756
757def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
758  AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
759
760def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
761  AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
762
763def HasDPP : Predicate<"Subtarget->hasDPP()">,
764  AssemblerPredicate<"FeatureDPP">;
765
766def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
767  AssemblerPredicate<"FeatureIntClamp">;
768
769def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
770  AssemblerPredicate<"FeatureMadMixInsts">;
771
772def EnableLateCFGStructurize : Predicate<
773  "EnableLateStructurizeCFG">;
774
775// Exists to help track down where SubtargetPredicate isn't set rather
776// than letting tablegen crash with an unhelpful error.
777def InvalidPred : Predicate<"predicate not set on instruction or pattern">;
778
779class PredicateControl {
780  Predicate SubtargetPredicate = InvalidPred;
781  Predicate SIAssemblerPredicate = isSICI;
782  Predicate VIAssemblerPredicate = isVI;
783  list<Predicate> AssemblerPredicates = [];
784  Predicate AssemblerPredicate = TruePredicate;
785  list<Predicate> OtherPredicates = [];
786  list<Predicate> Predicates = !listconcat([SubtargetPredicate,
787                                            AssemblerPredicate],
788                                            AssemblerPredicates,
789                                            OtherPredicates);
790}
791
792class AMDGPUPat<dag pattern, dag result> : Pat<pattern, result>,
793  PredicateControl;
794
795
796// Include AMDGPU TD files
797include "R600Schedule.td"
798include "R600Processors.td"
799include "SISchedule.td"
800include "GCNProcessors.td"
801include "AMDGPUInstrInfo.td"
802include "AMDGPUIntrinsics.td"
803include "AMDGPURegisterInfo.td"
804include "AMDGPURegisterBanks.td"
805include "AMDGPUInstructions.td"
806include "AMDGPUCallingConv.td"
807