1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21
22class BoolToList<bit Value> {
23  list<int> ret = !if(Value, [1]<int>, []<int>);
24}
25
26//===------------------------------------------------------------===//
27// Subtarget Features (device properties)
28//===------------------------------------------------------------===//
29
30def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
31  "FastFMAF32",
32  "true",
33  "Assuming f32 fma is at least as fast as mul + add"
34>;
35
36def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
37  "FastDenormalF32",
38  "true",
39  "Enabling denormals does not cause f32 instructions to run at f64 rates"
40>;
41
42def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
43  "MIMG_R128",
44  "true",
45  "Support 128-bit texture resources"
46>;
47
48def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
49  "HalfRate64Ops",
50  "true",
51  "Most fp64 instructions are half rate instead of quarter"
52>;
53
54def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
55  "FlatAddressSpace",
56  "true",
57  "Support flat address space"
58>;
59
60def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
61  "FlatInstOffsets",
62  "true",
63  "Flat instructions have immediate offset addressing mode"
64>;
65
66def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
67  "FlatGlobalInsts",
68  "true",
69  "Have global_* flat memory instructions"
70>;
71
72def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
73  "FlatScratchInsts",
74  "true",
75  "Have scratch_* flat memory instructions"
76>;
77
78def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
79  "ScalarFlatScratchInsts",
80  "true",
81  "Have s_scratch_* flat memory instructions"
82>;
83
84def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
85  "AddNoCarryInsts",
86  "true",
87  "Have VALU add/sub instructions without carry out"
88>;
89
90def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
91  "UnalignedBufferAccess",
92  "true",
93  "Support unaligned global loads and stores"
94>;
95
96def FeatureTrapHandler: SubtargetFeature<"trap-handler",
97  "TrapHandler",
98  "true",
99  "Trap handler support"
100>;
101
102def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
103  "UnalignedScratchAccess",
104  "true",
105  "Support unaligned scratch loads and stores"
106>;
107
108def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
109  "HasApertureRegs",
110  "true",
111  "Has Memory Aperture Base and Size Registers"
112>;
113
114def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
115  "HasMadMixInsts",
116  "true",
117  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
118>;
119
120def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
121  "HasFmaMixInsts",
122  "true",
123  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
124>;
125
126def FeatureDoesNotSupportXNACK : SubtargetFeature<"no-xnack-support",
127  "DoesNotSupportXNACK",
128  "true",
129  "Hardware does not support XNACK"
130>;
131
132// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
133// XNACK. The current default kernel driver setting is:
134// - graphics ring: XNACK disabled
135// - compute ring: XNACK enabled
136//
137// If XNACK is enabled, the VMEM latency can be worse.
138// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
139def FeatureXNACK : SubtargetFeature<"xnack",
140  "EnableXNACK",
141  "true",
142  "Enable XNACK support"
143>;
144
145def FeatureCuMode : SubtargetFeature<"cumode",
146  "EnableCuMode",
147  "true",
148  "Enable CU wavefront execution mode"
149>;
150
151def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
152  "SGPRInitBug",
153  "true",
154  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
155>;
156
157def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
158  "LDSMisalignedBug",
159  "true",
160  "Some GFX10 bug with misaligned multi-dword LDS access in WGP mode"
161>;
162
163def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
164  "HasMFMAInlineLiteralBug",
165  "true",
166  "MFMA cannot use inline literal as SrcC"
167>;
168
169def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
170  "HasVcmpxPermlaneHazard",
171  "true",
172  "TODO: describe me"
173>;
174
175def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
176  "HasVMEMtoScalarWriteHazard",
177  "true",
178  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
179>;
180
181def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
182  "HasSMEMtoVectorWriteHazard",
183  "true",
184  "s_load_dword followed by v_cmp page faults"
185>;
186
187def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
188  "HasInstFwdPrefetchBug",
189  "true",
190  "S_INST_PREFETCH instruction causes shader to hang"
191>;
192
193def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
194  "HasVcmpxExecWARHazard",
195  "true",
196  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
197>;
198
199def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
200  "HasLdsBranchVmemWARHazard",
201  "true",
202  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
203>;
204
205def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
206  "HasNSAtoVMEMBug",
207  "true",
208  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
209>;
210
211def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
212  "HasFlatSegmentOffsetBug",
213  "true",
214  "GFX10 bug, inst_offset ignored in flat segment"
215>;
216
217def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
218  "HasOffset3fBug",
219  "true",
220  "Branch offset of 3f hardware bug"
221>;
222
223class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
224  "ldsbankcount"#Value,
225  "LDSBankCount",
226  !cast<string>(Value),
227  "The number of LDS banks per compute unit."
228>;
229
230def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
231def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
232
233def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
234  "GCN3Encoding",
235  "true",
236  "Encoding format for VI"
237>;
238
239def FeatureCIInsts : SubtargetFeature<"ci-insts",
240  "CIInsts",
241  "true",
242  "Additional instructions for CI+"
243>;
244
245def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
246  "GFX8Insts",
247  "true",
248  "Additional instructions for GFX8+"
249>;
250
251def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
252  "GFX9Insts",
253  "true",
254  "Additional instructions for GFX9+"
255>;
256
257def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
258  "GFX10Insts",
259  "true",
260  "Additional instructions for GFX10+"
261>;
262
263def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
264  "GFX7GFX8GFX9Insts",
265  "true",
266  "Instructions shared in GFX7, GFX8, GFX9"
267>;
268
269def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
270  "HasSMemRealTime",
271  "true",
272  "Has s_memrealtime instruction"
273>;
274
275def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
276  "HasInv2PiInlineImm",
277  "true",
278  "Has 1 / (2 * pi) as inline immediate"
279>;
280
281def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
282  "Has16BitInsts",
283  "true",
284  "Has i16/f16 instructions"
285>;
286
287def FeatureVOP3P : SubtargetFeature<"vop3p",
288  "HasVOP3PInsts",
289  "true",
290  "Has VOP3P packed instructions"
291>;
292
293def FeatureMovrel : SubtargetFeature<"movrel",
294  "HasMovrel",
295  "true",
296  "Has v_movrel*_b32 instructions"
297>;
298
299def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
300  "HasVGPRIndexMode",
301  "true",
302  "Has VGPR mode register indexing"
303>;
304
305def FeatureScalarStores : SubtargetFeature<"scalar-stores",
306  "HasScalarStores",
307  "true",
308  "Has store scalar memory instructions"
309>;
310
311def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
312  "HasScalarAtomics",
313  "true",
314  "Has atomic scalar memory instructions"
315>;
316
317def FeatureSDWA : SubtargetFeature<"sdwa",
318  "HasSDWA",
319  "true",
320  "Support SDWA (Sub-DWORD Addressing) extension"
321>;
322
323def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
324  "HasSDWAOmod",
325  "true",
326  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
327>;
328
329def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
330  "HasSDWAScalar",
331  "true",
332  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
333>;
334
335def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
336  "HasSDWASdst",
337  "true",
338  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
339>;
340
341def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
342  "HasSDWAMac",
343  "true",
344  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
345>;
346
347def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
348  "HasSDWAOutModsVOPC",
349  "true",
350  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
351>;
352
353def FeatureDPP : SubtargetFeature<"dpp",
354  "HasDPP",
355  "true",
356  "Support DPP (Data Parallel Primitives) extension"
357>;
358
359// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
360def FeatureDPP8 : SubtargetFeature<"dpp8",
361  "HasDPP8",
362  "true",
363  "Support DPP8 (Data Parallel Primitives) extension"
364>;
365
366def FeatureR128A16 : SubtargetFeature<"r128-a16",
367  "HasR128A16",
368  "true",
369  "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
370>;
371
372def FeatureGFX10A16 : SubtargetFeature<"a16",
373  "HasGFX10A16",
374  "true",
375  "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
376>;
377
378def FeatureG16 : SubtargetFeature<"g16",
379  "HasG16",
380  "true",
381  "Support G16 for 16-bit gradient image operands"
382>;
383
384def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
385  "HasNSAEncoding",
386  "true",
387  "Support NSA encoding for image instructions"
388>;
389
390def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
391  "HasIntClamp",
392  "true",
393  "Support clamp for integer destination"
394>;
395
396def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
397  "HasUnpackedD16VMem",
398  "true",
399  "Has unpacked d16 vmem instructions"
400>;
401
402def FeatureDLInsts : SubtargetFeature<"dl-insts",
403  "HasDLInsts",
404  "true",
405  "Has v_fmac_f32 and v_xnor_b32 instructions"
406>;
407
408def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
409  "HasDot1Insts",
410  "true",
411  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
412>;
413
414def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
415  "HasDot2Insts",
416  "true",
417  "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
418>;
419
420def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
421  "HasDot3Insts",
422  "true",
423  "Has v_dot8c_i32_i4 instruction"
424>;
425
426def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
427  "HasDot4Insts",
428  "true",
429  "Has v_dot2c_i32_i16 instruction"
430>;
431
432def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
433  "HasDot5Insts",
434  "true",
435  "Has v_dot2c_f32_f16 instruction"
436>;
437
438def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
439  "HasDot6Insts",
440  "true",
441  "Has v_dot4c_i32_i8 instruction"
442>;
443
444def FeatureMAIInsts : SubtargetFeature<"mai-insts",
445  "HasMAIInsts",
446  "true",
447  "Has mAI instructions"
448>;
449
450def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
451  "HasPkFmacF16Inst",
452  "true",
453  "Has v_pk_fmac_f16 instruction"
454>;
455
456def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
457  "HasAtomicFaddInsts",
458  "true",
459  "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
460  "global_atomic_pk_add_f16 instructions",
461  [FeatureFlatGlobalInsts]
462>;
463
464def FeatureDoesNotSupportSRAMECC : SubtargetFeature<"no-sram-ecc-support",
465  "DoesNotSupportSRAMECC",
466  "true",
467  "Hardware does not support SRAM ECC"
468>;
469
470def FeatureSRAMECC : SubtargetFeature<"sram-ecc",
471  "EnableSRAMECC",
472  "true",
473  "Enable SRAM ECC"
474>;
475
476def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
477  "HasNoSdstCMPX",
478  "true",
479  "V_CMPX does not write VCC/SGPR in addition to EXEC"
480>;
481
482def FeatureVscnt : SubtargetFeature<"vscnt",
483  "HasVscnt",
484  "true",
485  "Has separate store vscnt counter"
486>;
487
488def FeatureRegisterBanking : SubtargetFeature<"register-banking",
489  "HasRegisterBanking",
490  "true",
491  "Has register banking"
492>;
493
494def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
495  "HasVOP3Literal",
496  "true",
497  "Can use one literal in VOP3"
498>;
499
500def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
501  "HasNoDataDepHazard",
502  "true",
503  "Does not need SW waitstates"
504>;
505
506//===------------------------------------------------------------===//
507// Subtarget Features (options and debugging)
508//===------------------------------------------------------------===//
509
510class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
511  "max-private-element-size-"#size,
512  "MaxPrivateElementSize",
513  !cast<string>(size),
514  "Maximum private access size may be "#size
515>;
516
517def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
518def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
519def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
520
521def FeatureDumpCode : SubtargetFeature <"DumpCode",
522  "DumpCode",
523  "true",
524  "Dump MachineInstrs in the CodeEmitter"
525>;
526
527def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
528  "DumpCode",
529  "true",
530  "Dump MachineInstrs in the CodeEmitter"
531>;
532
533// XXX - This should probably be removed once enabled by default
534def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
535  "EnableLoadStoreOpt",
536  "true",
537  "Enable SI load/store optimizer pass"
538>;
539
540// Performance debugging feature. Allow using DS instruction immediate
541// offsets even if the base pointer can't be proven to be base. On SI,
542// base pointer values that won't give the same result as a 16-bit add
543// are not safe to fold, but this will override the conservative test
544// for the base pointer.
545def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
546  "unsafe-ds-offset-folding",
547  "EnableUnsafeDSOffsetFolding",
548  "true",
549  "Force using DS instruction immediate offsets on SI"
550>;
551
552def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
553  "EnableSIScheduler",
554  "true",
555  "Enable SI Machine Scheduler"
556>;
557
558def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
559  "EnableDS128",
560  "true",
561  "Use ds_{read|write}_b128"
562>;
563
564// Sparse texture support requires that all result registers are zeroed when
565// PRTStrictNull is set to true. This feature is turned on for all architectures
566// but is enabled as a feature in case there are situations where PRTStrictNull
567// is disabled by the driver.
568def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
569  "EnablePRTStrictNull",
570  "true",
571  "Enable zeroing of result registers for sparse texture fetches"
572>;
573
574// Unless +-flat-for-global is specified, turn on FlatForGlobal for
575// all OS-es on VI and newer hardware to avoid assertion failures due
576// to missing ADDR64 variants of MUBUF instructions.
577// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
578// instructions.
579
580def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
581  "FlatForGlobal",
582  "true",
583  "Force to generate flat instruction for global"
584>;
585
586def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
587  "auto-waitcnt-before-barrier",
588  "AutoWaitcntBeforeBarrier",
589  "true",
590  "Hardware automatically inserts waitcnt before barrier"
591>;
592
593def FeatureCodeObjectV3 : SubtargetFeature <
594  "code-object-v3",
595  "CodeObjectV3",
596  "true",
597  "Generate code object version 3"
598>;
599
600def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
601  "HasTrigReducedRange",
602  "true",
603  "Requires use of fract on arguments to trig instructions"
604>;
605
606// Dummy feature used to disable assembler instructions.
607def FeatureDisable : SubtargetFeature<"",
608  "FeatureDisable","true",
609  "Dummy feature to disable assembler instructions"
610>;
611
612class GCNSubtargetFeatureGeneration <string Value,
613                                     string FeatureName,
614                                     list<SubtargetFeature> Implies> :
615        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
616
617def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
618    "southern-islands",
619  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
620  FeatureWavefrontSize64,
621  FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange,
622  FeatureDoesNotSupportSRAMECC, FeatureDoesNotSupportXNACK]
623>;
624
625def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
626    "sea-islands",
627  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
628  FeatureWavefrontSize64, FeatureFlatAddressSpace,
629  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
630  FeatureGFX7GFX8GFX9Insts, FeatureDoesNotSupportSRAMECC]
631>;
632
633def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
634  "volcanic-islands",
635  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
636   FeatureWavefrontSize64, FeatureFlatAddressSpace,
637   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
638   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
639   FeatureScalarStores, FeatureInv2PiInlineImm,
640   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
641   FeatureIntClamp, FeatureTrigReducedRange, FeatureDoesNotSupportSRAMECC,
642   FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts, FeatureFastDenormalF32
643  ]
644>;
645
646def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
647  "gfx9",
648  [FeatureFP64, FeatureLocalMemorySize65536,
649   FeatureWavefrontSize64, FeatureFlatAddressSpace,
650   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
651   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
652   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
653   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
654   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
655   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
656   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
657   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
658   FeatureFastDenormalF32]
659>;
660
661def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
662  "gfx10",
663  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
664   FeatureFlatAddressSpace,
665   FeatureCIInsts, Feature16BitInsts,
666   FeatureSMemRealTime, FeatureInv2PiInlineImm,
667   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
668   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
669   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
670   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
671   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
672   FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
673   FeatureVOP3Literal, FeatureDPP8,
674   FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureDoesNotSupportSRAMECC,
675   FeatureGFX10A16, FeatureFastDenormalF32, FeatureG16
676  ]
677>;
678
679class FeatureSet<list<SubtargetFeature> Features_> {
680  list<SubtargetFeature> Features = Features_;
681}
682
683def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
684   FeatureFastFMAF32,
685   HalfRate64Ops,
686   FeatureLDSBankCount32,
687   FeatureDoesNotSupportXNACK,
688   FeatureCodeObjectV3]>;
689
690def FeatureISAVersion6_0_1 : FeatureSet<
691  [FeatureSouthernIslands,
692   FeatureLDSBankCount32,
693   FeatureDoesNotSupportXNACK,
694   FeatureCodeObjectV3]>;
695
696def FeatureISAVersion7_0_0 : FeatureSet<
697  [FeatureSeaIslands,
698   FeatureLDSBankCount32,
699   FeatureDoesNotSupportXNACK,
700   FeatureCodeObjectV3]>;
701
702def FeatureISAVersion7_0_1 : FeatureSet<
703  [FeatureSeaIslands,
704   HalfRate64Ops,
705   FeatureLDSBankCount32,
706   FeatureFastFMAF32,
707   FeatureDoesNotSupportXNACK,
708   FeatureCodeObjectV3]>;
709
710def FeatureISAVersion7_0_2 : FeatureSet<
711  [FeatureSeaIslands,
712   FeatureLDSBankCount16,
713   FeatureFastFMAF32,
714   FeatureDoesNotSupportXNACK,
715   FeatureCodeObjectV3]>;
716
717def FeatureISAVersion7_0_3 : FeatureSet<
718  [FeatureSeaIslands,
719   FeatureLDSBankCount16,
720   FeatureDoesNotSupportXNACK,
721   FeatureCodeObjectV3]>;
722
723def FeatureISAVersion7_0_4 : FeatureSet<
724  [FeatureSeaIslands,
725   FeatureLDSBankCount32,
726   FeatureDoesNotSupportXNACK,
727   FeatureCodeObjectV3]>;
728
729def FeatureISAVersion8_0_1 : FeatureSet<
730  [FeatureVolcanicIslands,
731   FeatureFastFMAF32,
732   HalfRate64Ops,
733   FeatureLDSBankCount32,
734   FeatureXNACK,
735   FeatureUnpackedD16VMem,
736   FeatureCodeObjectV3]>;
737
738def FeatureISAVersion8_0_2 : FeatureSet<
739  [FeatureVolcanicIslands,
740   FeatureLDSBankCount32,
741   FeatureSGPRInitBug,
742   FeatureUnpackedD16VMem,
743   FeatureDoesNotSupportXNACK,
744   FeatureCodeObjectV3]>;
745
746def FeatureISAVersion8_0_3 : FeatureSet<
747  [FeatureVolcanicIslands,
748   FeatureLDSBankCount32,
749   FeatureUnpackedD16VMem,
750   FeatureDoesNotSupportXNACK,
751   FeatureCodeObjectV3]>;
752
753def FeatureISAVersion8_1_0 : FeatureSet<
754  [FeatureVolcanicIslands,
755   FeatureLDSBankCount16,
756   FeatureXNACK,
757   FeatureCodeObjectV3]>;
758
759def FeatureISAVersion9_0_0 : FeatureSet<
760  [FeatureGFX9,
761   FeatureMadMixInsts,
762   FeatureLDSBankCount32,
763   FeatureCodeObjectV3,
764   FeatureDoesNotSupportXNACK,
765   FeatureDoesNotSupportSRAMECC]>;
766
767def FeatureISAVersion9_0_2 : FeatureSet<
768  [FeatureGFX9,
769   FeatureMadMixInsts,
770   FeatureLDSBankCount32,
771   FeatureXNACK,
772   FeatureDoesNotSupportSRAMECC,
773   FeatureCodeObjectV3]>;
774
775def FeatureISAVersion9_0_4 : FeatureSet<
776  [FeatureGFX9,
777   FeatureLDSBankCount32,
778   FeatureFmaMixInsts,
779   FeatureDoesNotSupportXNACK,
780   FeatureDoesNotSupportSRAMECC,
781   FeatureCodeObjectV3]>;
782
783def FeatureISAVersion9_0_6 : FeatureSet<
784  [FeatureGFX9,
785   HalfRate64Ops,
786   FeatureFmaMixInsts,
787   FeatureLDSBankCount32,
788   FeatureDLInsts,
789   FeatureDot1Insts,
790   FeatureDot2Insts,
791   FeatureDoesNotSupportXNACK,
792   FeatureCodeObjectV3]>;
793
794def FeatureISAVersion9_0_8 : FeatureSet<
795  [FeatureGFX9,
796   HalfRate64Ops,
797   FeatureFmaMixInsts,
798   FeatureLDSBankCount32,
799   FeatureDLInsts,
800   FeatureDot1Insts,
801   FeatureDot2Insts,
802   FeatureDot3Insts,
803   FeatureDot4Insts,
804   FeatureDot5Insts,
805   FeatureDot6Insts,
806   FeatureMAIInsts,
807   FeaturePkFmacF16Inst,
808   FeatureAtomicFaddInsts,
809   FeatureSRAMECC,
810   FeatureMFMAInlineLiteralBug,
811   FeatureCodeObjectV3]>;
812
813def FeatureISAVersion9_0_9 : FeatureSet<
814  [FeatureGFX9,
815   FeatureMadMixInsts,
816   FeatureLDSBankCount32,
817   FeatureXNACK,
818   FeatureCodeObjectV3]>;
819
820// TODO: Organize more features into groups.
821def FeatureGroup {
822  // Bugs present on gfx10.1.
823  list<SubtargetFeature> GFX10_1_Bugs = [
824    FeatureVcmpxPermlaneHazard,
825    FeatureVMEMtoScalarWriteHazard,
826    FeatureSMEMtoVectorWriteHazard,
827    FeatureInstFwdPrefetchBug,
828    FeatureVcmpxExecWARHazard,
829    FeatureLdsBranchVmemWARHazard,
830    FeatureNSAtoVMEMBug,
831    FeatureOffset3fBug,
832    FeatureFlatSegmentOffsetBug
833   ];
834}
835
836def FeatureISAVersion10_1_0 : FeatureSet<
837  !listconcat(FeatureGroup.GFX10_1_Bugs,
838    [FeatureGFX10,
839     FeatureLDSBankCount32,
840     FeatureDLInsts,
841     FeatureNSAEncoding,
842     FeatureWavefrontSize32,
843     FeatureScalarStores,
844     FeatureScalarAtomics,
845     FeatureScalarFlatScratchInsts,
846     FeatureLdsMisalignedBug,
847     FeatureDoesNotSupportXNACK,
848     FeatureCodeObjectV3])>;
849
850def FeatureISAVersion10_1_1 : FeatureSet<
851  !listconcat(FeatureGroup.GFX10_1_Bugs,
852    [FeatureGFX10,
853     FeatureLDSBankCount32,
854     FeatureDLInsts,
855     FeatureDot1Insts,
856     FeatureDot2Insts,
857     FeatureDot5Insts,
858     FeatureDot6Insts,
859     FeatureNSAEncoding,
860     FeatureWavefrontSize32,
861     FeatureScalarStores,
862     FeatureScalarAtomics,
863     FeatureScalarFlatScratchInsts,
864     FeatureDoesNotSupportXNACK,
865     FeatureCodeObjectV3])>;
866
867def FeatureISAVersion10_1_2 : FeatureSet<
868  !listconcat(FeatureGroup.GFX10_1_Bugs,
869    [FeatureGFX10,
870     FeatureLDSBankCount32,
871     FeatureDLInsts,
872     FeatureDot1Insts,
873     FeatureDot2Insts,
874     FeatureDot5Insts,
875     FeatureDot6Insts,
876     FeatureNSAEncoding,
877     FeatureWavefrontSize32,
878     FeatureScalarStores,
879     FeatureScalarAtomics,
880     FeatureScalarFlatScratchInsts,
881     FeatureLdsMisalignedBug,
882     FeatureDoesNotSupportXNACK,
883     FeatureCodeObjectV3])>;
884
885//===----------------------------------------------------------------------===//
886
887def AMDGPUInstrInfo : InstrInfo {
888  let guessInstructionProperties = 1;
889  let noNamedPositionallyEncodedOperands = 1;
890}
891
892def AMDGPUAsmParser : AsmParser {
893  // Some of the R600 registers have the same name, so this crashes.
894  // For example T0_XYZW and T0_XY both have the asm name T0.
895  let ShouldEmitMatchRegisterName = 0;
896}
897
898def AMDGPUAsmWriter : AsmWriter {
899  int PassSubtarget = 1;
900}
901
902def AMDGPUAsmVariants {
903  string Default = "Default";
904  int Default_ID = 0;
905  string VOP3 = "VOP3";
906  int VOP3_ID = 1;
907  string SDWA = "SDWA";
908  int SDWA_ID = 2;
909  string SDWA9 = "SDWA9";
910  int SDWA9_ID = 3;
911  string DPP = "DPP";
912  int DPP_ID = 4;
913  string Disable = "Disable";
914  int Disable_ID = 5;
915}
916
917def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
918  let Variant = AMDGPUAsmVariants.Default_ID;
919  let Name = AMDGPUAsmVariants.Default;
920}
921
922def VOP3AsmParserVariant : AsmParserVariant {
923  let Variant = AMDGPUAsmVariants.VOP3_ID;
924  let Name = AMDGPUAsmVariants.VOP3;
925}
926
927def SDWAAsmParserVariant : AsmParserVariant {
928  let Variant = AMDGPUAsmVariants.SDWA_ID;
929  let Name = AMDGPUAsmVariants.SDWA;
930}
931
932def SDWA9AsmParserVariant : AsmParserVariant {
933  let Variant = AMDGPUAsmVariants.SDWA9_ID;
934  let Name = AMDGPUAsmVariants.SDWA9;
935}
936
937
938def DPPAsmParserVariant : AsmParserVariant {
939  let Variant = AMDGPUAsmVariants.DPP_ID;
940  let Name = AMDGPUAsmVariants.DPP;
941}
942
943def AMDGPU : Target {
944  // Pull in Instruction Info:
945  let InstructionSet = AMDGPUInstrInfo;
946  let AssemblyParsers = [AMDGPUAsmParser];
947  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
948                                VOP3AsmParserVariant,
949                                SDWAAsmParserVariant,
950                                SDWA9AsmParserVariant,
951                                DPPAsmParserVariant];
952  let AssemblyWriters = [AMDGPUAsmWriter];
953  let AllowRegisterRenaming = 1;
954}
955
956// Dummy Instruction itineraries for pseudo instructions
957def ALU_NULL : FuncUnit;
958def NullALU : InstrItinClass;
959
960//===----------------------------------------------------------------------===//
961// Predicate helper class
962//===----------------------------------------------------------------------===//
963
964def isGFX6 :
965  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
966  AssemblerPredicate<(all_of FeatureSouthernIslands)>;
967
968def isGFX6GFX7 :
969  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
970            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
971  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
972
973def isGFX6GFX7GFX10 :
974  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
975            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
976            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
977  AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
978
979def isGFX7Only :
980  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
981  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
982
983def isGFX7GFX10 :
984  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
985            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
986  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
987
988def isGFX7GFX8GFX9 :
989  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
990            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
991            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
992  AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
993
994def isGFX6GFX7GFX8GFX9 :
995  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
996            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
997            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
998            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
999  AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
1000
1001def isGFX7Plus :
1002  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1003  AssemblerPredicate<(all_of FeatureCIInsts)>;
1004
1005def isGFX8Plus :
1006  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1007  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1008
1009def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1010                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1011  AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1012
1013def isGFX9Plus :
1014  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1015  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1016
1017def isGFX9Only : Predicate <
1018  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1019  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1020
1021def isGFX8GFX9 :
1022  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1023            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1024  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1025
1026def isGFX10Plus :
1027  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1028  AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1029
1030def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1031  AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1032
1033def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1034  AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1035def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1036  AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1037def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1038  AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1039def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1040  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1041
1042def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1043  AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1044def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1045  AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1046
1047def D16PreservesUnusedBits :
1048  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1049  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1050
1051def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1052def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1053
1054def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1055  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1056
1057def HasLDSFPAtomics : Predicate<"Subtarget->hasLDSFPAtomics()">,
1058  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1059
1060def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1061  AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1062
1063def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1064
1065def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1066  AssemblerPredicate<(all_of Feature16BitInsts)>;
1067def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1068  AssemblerPredicate<(all_of FeatureVOP3P)>;
1069
1070def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
1071def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
1072
1073def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1074  AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1075
1076def HasSDWA9 :
1077  Predicate<"Subtarget->hasSDWA()">,
1078  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1079
1080def HasSDWA10 :
1081  Predicate<"Subtarget->hasSDWA()">,
1082  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1083
1084def HasDPP : Predicate<"Subtarget->hasDPP()">,
1085  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1086
1087def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1088  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1089
1090def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1091  AssemblerPredicate<(all_of FeatureR128A16)>;
1092
1093def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1094  AssemblerPredicate<(all_of FeatureGFX10A16)>;
1095
1096def HasG16 : Predicate<"Subtarget->hasG16()">,
1097  AssemblerPredicate<(all_of FeatureG16)>;
1098
1099def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1100  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1101
1102def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1103  AssemblerPredicate<(all_of FeatureIntClamp)>;
1104
1105def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1106  AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1107
1108def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1109  AssemblerPredicate<(all_of FeatureScalarStores)>;
1110
1111def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1112  AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1113
1114def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1115  AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1116
1117def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1118  AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1119
1120def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1121def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1122def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1123                      AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1124def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1125                AssemblerPredicate<(all_of FeatureMovrel)>;
1126
1127def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1128  AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1129
1130def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1131  AssemblerPredicate<(all_of FeatureDLInsts)>;
1132
1133def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1134  AssemblerPredicate<(all_of FeatureDot1Insts)>;
1135
1136def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1137  AssemblerPredicate<(all_of FeatureDot2Insts)>;
1138
1139def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1140  AssemblerPredicate<(all_of FeatureDot3Insts)>;
1141
1142def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1143  AssemblerPredicate<(all_of FeatureDot4Insts)>;
1144
1145def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1146  AssemblerPredicate<(all_of FeatureDot5Insts)>;
1147
1148def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1149  AssemblerPredicate<(all_of FeatureDot6Insts)>;
1150
1151def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1152  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1153
1154def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1155  AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1156
1157def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1158  AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>;
1159
1160def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">,
1161  AssemblerPredicate<(all_of FeatureOffset3fBug)>;
1162
1163def EnableLateCFGStructurize : Predicate<
1164  "EnableLateStructurizeCFG">;
1165
1166// Include AMDGPU TD files
1167include "SISchedule.td"
1168include "GCNProcessors.td"
1169include "AMDGPUInstrInfo.td"
1170include "SIRegisterInfo.td"
1171include "AMDGPURegisterBanks.td"
1172include "AMDGPUInstructions.td"
1173include "SIInstrInfo.td"
1174include "AMDGPUCallingConv.td"
1175include "AMDGPUSearchableTables.td"
1176