1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===------------------------------------------------------------===//
9
10include "llvm/Target/Target.td"
11
12//===------------------------------------------------------------===//
13// Subtarget Features (device properties)
14//===------------------------------------------------------------===//
15
16def FeatureFP64 : SubtargetFeature<"fp64",
17  "FP64",
18  "true",
19  "Enable double precision operations"
20>;
21
22def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
23  "FastFMAF32",
24  "true",
25  "Assuming f32 fma is at least as fast as mul + add"
26>;
27
28def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
29  "HalfRate64Ops",
30  "true",
31  "Most fp64 instructions are half rate instead of quarter"
32>;
33
34def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
35  "R600ALUInst",
36  "false",
37  "Older version of ALU instructions encoding"
38>;
39
40def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
41  "HasVertexCache",
42  "true",
43  "Specify use of dedicated vertex cache"
44>;
45
46def FeatureCaymanISA : SubtargetFeature<"caymanISA",
47  "CaymanISA",
48  "true",
49  "Use Cayman ISA"
50>;
51
52def FeatureCFALUBug : SubtargetFeature<"cfalubug",
53  "CFALUBug",
54  "true",
55  "GPU has CF_ALU bug"
56>;
57
58def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
59  "FlatAddressSpace",
60  "true",
61  "Support flat address space"
62>;
63
64def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
65  "UnalignedBufferAccess",
66  "true",
67  "Support unaligned global loads and stores"
68>;
69
70def FeatureXNACK : SubtargetFeature<"xnack",
71  "EnableXNACK",
72  "true",
73  "Enable XNACK support"
74>;
75
76def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
77  "SGPRInitBug",
78  "true",
79  "VI SGPR initilization bug requiring a fixed SGPR allocation size"
80>;
81
82class SubtargetFeatureFetchLimit <string Value> :
83                          SubtargetFeature <"fetch"#Value,
84  "TexVTXClauseSize",
85  Value,
86  "Limit the maximum number of fetches in a clause to "#Value
87>;
88
89def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
90def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
91
92class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
93  "wavefrontsize"#Value,
94  "WavefrontSize",
95  !cast<string>(Value),
96  "The number of threads per wavefront"
97>;
98
99def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
100def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
101def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
102
103class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
104  "ldsbankcount"#Value,
105  "LDSBankCount",
106  !cast<string>(Value),
107  "The number of LDS banks per compute unit."
108>;
109
110def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
111def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
112
113class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping>
114                                 : SubtargetFeature <
115  "isaver"#Major#"."#Minor#"."#Stepping,
116  "IsaVersion",
117  "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
118  "Instruction set version number"
119>;
120
121def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0>;
122def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1>;
123def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0>;
124def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1>;
125def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2>;
126def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3>;
127
128class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
129  "localmemorysize"#Value,
130  "LocalMemorySize",
131  !cast<string>(Value),
132  "The size of local memory in bytes"
133>;
134
135def FeatureGCN : SubtargetFeature<"gcn",
136  "IsGCN",
137  "true",
138  "GCN or newer GPU"
139>;
140
141def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",
142  "GCN1Encoding",
143  "true",
144  "Encoding format for SI and CI"
145>;
146
147def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
148  "GCN3Encoding",
149  "true",
150  "Encoding format for VI"
151>;
152
153def FeatureCIInsts : SubtargetFeature<"ci-insts",
154  "CIInsts",
155  "true",
156  "Additional intstructions for CI+"
157>;
158
159def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
160  "HasSMemRealTime",
161  "true",
162  "Has s_memrealtime instruction"
163>;
164
165def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
166  "Has16BitInsts",
167  "true",
168  "Has i16/f16 instructions"
169>;
170
171def FeatureMovrel : SubtargetFeature<"movrel",
172  "HasMovrel",
173  "true",
174  "Has v_movrel*_b32 instructions"
175>;
176
177def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
178  "HasVGPRIndexMode",
179  "true",
180  "Has VGPR mode register indexing"
181>;
182
183//===------------------------------------------------------------===//
184// Subtarget Features (options and debugging)
185//===------------------------------------------------------------===//
186
187// Some instructions do not support denormals despite this flag. Using
188// fp32 denormals also causes instructions to run at the double
189// precision rate for the device.
190def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
191  "FP32Denormals",
192  "true",
193  "Enable single precision denormal handling"
194>;
195
196def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
197  "FP64Denormals",
198  "true",
199  "Enable double precision denormal handling",
200  [FeatureFP64]
201>;
202
203def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
204  "FPExceptions",
205  "true",
206  "Enable floating point exceptions"
207>;
208
209class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
210  "max-private-element-size-"#size,
211  "MaxPrivateElementSize",
212  !cast<string>(size),
213  "Maximum private access size may be "#size
214>;
215
216def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
217def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
218def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
219
220def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
221  "EnableVGPRSpilling",
222  "true",
223  "Enable spilling of VGPRs to scratch memory"
224>;
225
226def FeatureDumpCode : SubtargetFeature <"DumpCode",
227  "DumpCode",
228  "true",
229  "Dump MachineInstrs in the CodeEmitter"
230>;
231
232def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
233  "DumpCode",
234  "true",
235  "Dump MachineInstrs in the CodeEmitter"
236>;
237
238def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
239  "EnablePromoteAlloca",
240  "true",
241  "Enable promote alloca pass"
242>;
243
244// XXX - This should probably be removed once enabled by default
245def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
246  "EnableLoadStoreOpt",
247  "true",
248  "Enable SI load/store optimizer pass"
249>;
250
251// Performance debugging feature. Allow using DS instruction immediate
252// offsets even if the base pointer can't be proven to be base. On SI,
253// base pointer values that won't give the same result as a 16-bit add
254// are not safe to fold, but this will override the conservative test
255// for the base pointer.
256def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
257  "unsafe-ds-offset-folding",
258  "EnableUnsafeDSOffsetFolding",
259  "true",
260  "Force using DS instruction immediate offsets on SI"
261>;
262
263def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
264  "EnableSIScheduler",
265  "true",
266  "Enable SI Machine Scheduler"
267>;
268
269def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
270  "FlatForGlobal",
271  "true",
272  "Force to generate flat instruction for global"
273>;
274
275// Dummy feature used to disable assembler instructions.
276def FeatureDisable : SubtargetFeature<"",
277  "FeatureDisable","true",
278  "Dummy feature to disable assembler instructions"
279>;
280
281class SubtargetFeatureGeneration <string Value,
282                                  list<SubtargetFeature> Implies> :
283        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
284                          Value#" GPU generation", Implies>;
285
286def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
287def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
288def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
289
290def FeatureR600 : SubtargetFeatureGeneration<"R600",
291  [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]
292>;
293
294def FeatureR700 : SubtargetFeatureGeneration<"R700",
295  [FeatureFetchLimit16, FeatureLocalMemorySize0]
296>;
297
298def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
299  [FeatureFetchLimit16, FeatureLocalMemorySize32768]
300>;
301
302def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
303  [FeatureFetchLimit16, FeatureWavefrontSize64,
304   FeatureLocalMemorySize32768]
305>;
306
307def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
308  [FeatureFP64, FeatureLocalMemorySize32768,
309  FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
310  FeatureLDSBankCount32, FeatureMovrel]
311>;
312
313def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
314  [FeatureFP64, FeatureLocalMemorySize65536,
315  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
316  FeatureGCN1Encoding, FeatureCIInsts, FeatureMovrel]
317>;
318
319def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
320  [FeatureFP64, FeatureLocalMemorySize65536,
321   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
322   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
323   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel
324  ]
325>;
326
327//===----------------------------------------------------------------------===//
328// Debugger related subtarget features.
329//===----------------------------------------------------------------------===//
330
331def FeatureDebuggerInsertNops : SubtargetFeature<
332  "amdgpu-debugger-insert-nops",
333  "DebuggerInsertNops",
334  "true",
335  "Insert one nop instruction for each high level source statement"
336>;
337
338def FeatureDebuggerReserveRegs : SubtargetFeature<
339  "amdgpu-debugger-reserve-regs",
340  "DebuggerReserveRegs",
341  "true",
342  "Reserve registers for debugger usage"
343>;
344
345def FeatureDebuggerEmitPrologue : SubtargetFeature<
346  "amdgpu-debugger-emit-prologue",
347  "DebuggerEmitPrologue",
348  "true",
349  "Emit debugger prologue"
350>;
351
352//===----------------------------------------------------------------------===//
353
354def AMDGPUInstrInfo : InstrInfo {
355  let guessInstructionProperties = 1;
356  let noNamedPositionallyEncodedOperands = 1;
357}
358
359def AMDGPUAsmParser : AsmParser {
360  // Some of the R600 registers have the same name, so this crashes.
361  // For example T0_XYZW and T0_XY both have the asm name T0.
362  let ShouldEmitMatchRegisterName = 0;
363}
364
365def AMDGPUAsmWriter : AsmWriter {
366  int PassSubtarget = 1;
367}
368
369def AMDGPUAsmVariants {
370  string Default = "Default";
371  int Default_ID = 0;
372  string VOP3 = "VOP3";
373  int VOP3_ID = 1;
374  string SDWA = "SDWA";
375  int SDWA_ID = 2;
376  string DPP = "DPP";
377  int DPP_ID = 3;
378  string Disable = "Disable";
379  int Disable_ID = 4;
380}
381
382def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
383  let Variant = AMDGPUAsmVariants.Default_ID;
384  let Name = AMDGPUAsmVariants.Default;
385}
386
387def VOP3AsmParserVariant : AsmParserVariant {
388  let Variant = AMDGPUAsmVariants.VOP3_ID;
389  let Name = AMDGPUAsmVariants.VOP3;
390}
391
392def SDWAAsmParserVariant : AsmParserVariant {
393  let Variant = AMDGPUAsmVariants.SDWA_ID;
394  let Name = AMDGPUAsmVariants.SDWA;
395}
396
397def DPPAsmParserVariant : AsmParserVariant {
398  let Variant = AMDGPUAsmVariants.DPP_ID;
399  let Name = AMDGPUAsmVariants.DPP;
400}
401
402def AMDGPU : Target {
403  // Pull in Instruction Info:
404  let InstructionSet = AMDGPUInstrInfo;
405  let AssemblyParsers = [AMDGPUAsmParser];
406  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
407                                VOP3AsmParserVariant,
408                                SDWAAsmParserVariant,
409                                DPPAsmParserVariant];
410  let AssemblyWriters = [AMDGPUAsmWriter];
411}
412
413// Dummy Instruction itineraries for pseudo instructions
414def ALU_NULL : FuncUnit;
415def NullALU : InstrItinClass;
416
417//===----------------------------------------------------------------------===//
418// Predicate helper class
419//===----------------------------------------------------------------------===//
420
421def TruePredicate : Predicate<"true">;
422
423def isSICI : Predicate<
424  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
425  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
426>, AssemblerPredicate<"FeatureGCN1Encoding">;
427
428def isVI : Predicate <
429  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
430  AssemblerPredicate<"FeatureGCN3Encoding">;
431
432def isCIVI : Predicate <
433  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS || "
434  "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS"
435>, AssemblerPredicate<"FeatureCIInsts">;
436
437def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">;
438
439class PredicateControl {
440  Predicate SubtargetPredicate;
441  Predicate SIAssemblerPredicate = isSICI;
442  Predicate VIAssemblerPredicate = isVI;
443  list<Predicate> AssemblerPredicates = [];
444  Predicate AssemblerPredicate = TruePredicate;
445  list<Predicate> OtherPredicates = [];
446  list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
447                                            AssemblerPredicates,
448                                            OtherPredicates);
449}
450
451// Include AMDGPU TD files
452include "R600Schedule.td"
453include "SISchedule.td"
454include "Processors.td"
455include "AMDGPUInstrInfo.td"
456include "AMDGPUIntrinsics.td"
457include "AMDGPURegisterInfo.td"
458include "AMDGPUInstructions.td"
459include "AMDGPUCallingConv.td"
460