1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===------------------------------------------------------------===//
9
10include "llvm/TableGen/SearchableTable.td"
11include "llvm/Target/Target.td"
12include "AMDGPUFeatures.td"
13
14class BoolToList<bit Value> {
15  list<int> ret = !if(Value, [1]<int>, []<int>);
16}
17
18//===------------------------------------------------------------===//
19// Subtarget Features (device properties)
20//===------------------------------------------------------------===//
21
22def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
23  "FastFMAF32",
24  "true",
25  "Assuming f32 fma is at least as fast as mul + add"
26>;
27
28def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
29  "MIMG_R128",
30  "true",
31  "Support 128-bit texture resources"
32>;
33
34def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
35  "HalfRate64Ops",
36  "true",
37  "Most fp64 instructions are half rate instead of quarter"
38>;
39
40def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
41  "FlatAddressSpace",
42  "true",
43  "Support flat address space"
44>;
45
46def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
47  "FlatInstOffsets",
48  "true",
49  "Flat instructions have immediate offset addressing mode"
50>;
51
52def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
53  "FlatGlobalInsts",
54  "true",
55  "Have global_* flat memory instructions"
56>;
57
58def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
59  "FlatScratchInsts",
60  "true",
61  "Have scratch_* flat memory instructions"
62>;
63
64def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
65  "AddNoCarryInsts",
66  "true",
67  "Have VALU add/sub instructions without carry out"
68>;
69
70def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
71  "UnalignedBufferAccess",
72  "true",
73  "Support unaligned global loads and stores"
74>;
75
76def FeatureTrapHandler: SubtargetFeature<"trap-handler",
77  "TrapHandler",
78  "true",
79  "Trap handler support"
80>;
81
82def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
83  "UnalignedScratchAccess",
84  "true",
85  "Support unaligned scratch loads and stores"
86>;
87
88def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
89  "HasApertureRegs",
90  "true",
91  "Has Memory Aperture Base and Size Registers"
92>;
93
94def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
95  "HasMadMixInsts",
96  "true",
97  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
98>;
99
100def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
101  "HasFmaMixInsts",
102  "true",
103  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
104>;
105
106// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
107// XNACK. The current default kernel driver setting is:
108// - graphics ring: XNACK disabled
109// - compute ring: XNACK enabled
110//
111// If XNACK is enabled, the VMEM latency can be worse.
112// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
113def FeatureXNACK : SubtargetFeature<"xnack",
114  "EnableXNACK",
115  "true",
116  "Enable XNACK support"
117>;
118
119def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
120  "SGPRInitBug",
121  "true",
122  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
123>;
124
125class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
126  "ldsbankcount"#Value,
127  "LDSBankCount",
128  !cast<string>(Value),
129  "The number of LDS banks per compute unit."
130>;
131
132def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
133def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
134
135def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
136  "GCN3Encoding",
137  "true",
138  "Encoding format for VI"
139>;
140
141def FeatureCIInsts : SubtargetFeature<"ci-insts",
142  "CIInsts",
143  "true",
144  "Additional instructions for CI+"
145>;
146
147def FeatureVIInsts : SubtargetFeature<"vi-insts",
148  "VIInsts",
149  "true",
150  "Additional instructions for VI+"
151>;
152
153def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
154  "GFX9Insts",
155  "true",
156  "Additional instructions for GFX9+"
157>;
158
159def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
160  "HasSMemRealTime",
161  "true",
162  "Has s_memrealtime instruction"
163>;
164
165def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
166  "HasInv2PiInlineImm",
167  "true",
168  "Has 1 / (2 * pi) as inline immediate"
169>;
170
171def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
172  "Has16BitInsts",
173  "true",
174  "Has i16/f16 instructions"
175>;
176
177def FeatureVOP3P : SubtargetFeature<"vop3p",
178  "HasVOP3PInsts",
179  "true",
180  "Has VOP3P packed instructions"
181>;
182
183def FeatureMovrel : SubtargetFeature<"movrel",
184  "HasMovrel",
185  "true",
186  "Has v_movrel*_b32 instructions"
187>;
188
189def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
190  "HasVGPRIndexMode",
191  "true",
192  "Has VGPR mode register indexing"
193>;
194
195def FeatureScalarStores : SubtargetFeature<"scalar-stores",
196  "HasScalarStores",
197  "true",
198  "Has store scalar memory instructions"
199>;
200
201def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
202  "HasScalarAtomics",
203  "true",
204  "Has atomic scalar memory instructions"
205>;
206
207def FeatureSDWA : SubtargetFeature<"sdwa",
208  "HasSDWA",
209  "true",
210  "Support SDWA (Sub-DWORD Addressing) extension"
211>;
212
213def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
214  "HasSDWAOmod",
215  "true",
216  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
217>;
218
219def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
220  "HasSDWAScalar",
221  "true",
222  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
223>;
224
225def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
226  "HasSDWASdst",
227  "true",
228  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
229>;
230
231def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
232  "HasSDWAMac",
233  "true",
234  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
235>;
236
237def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
238  "HasSDWAOutModsVOPC",
239  "true",
240  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
241>;
242
243def FeatureDPP : SubtargetFeature<"dpp",
244  "HasDPP",
245  "true",
246  "Support DPP (Data Parallel Primitives) extension"
247>;
248
249def FeatureR128A16 : SubtargetFeature<"r128-a16",
250  "HasR128A16",
251  "true",
252  "Support 16 bit coordindates/gradients/lod/clamp/mip types on gfx9"
253>;
254
255def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
256  "HasIntClamp",
257  "true",
258  "Support clamp for integer destination"
259>;
260
261def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
262  "HasUnpackedD16VMem",
263  "true",
264  "Has unpacked d16 vmem instructions"
265>;
266
267def FeatureDLInsts : SubtargetFeature<"dl-insts",
268  "HasDLInsts",
269  "true",
270  "Has deep learning instructions"
271>;
272
273def FeatureSRAMECC : SubtargetFeature<"sram-ecc",
274  "EnableSRAMECC",
275  "true",
276  "Enable SRAM ECC"
277>;
278
279//===------------------------------------------------------------===//
280// Subtarget Features (options and debugging)
281//===------------------------------------------------------------===//
282
283// Denormal handling for fp64 and fp16 is controlled by the same
284// config register when fp16 supported.
285// TODO: Do we need a separate f16 setting when not legal?
286def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
287  "FP64FP16Denormals",
288  "true",
289  "Enable double and half precision denormal handling",
290  [FeatureFP64]
291>;
292
293def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
294  "FP64FP16Denormals",
295  "true",
296  "Enable double and half precision denormal handling",
297  [FeatureFP64, FeatureFP64FP16Denormals]
298>;
299
300def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
301  "FP64FP16Denormals",
302  "true",
303  "Enable half precision denormal handling",
304  [FeatureFP64FP16Denormals]
305>;
306
307def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
308  "FPExceptions",
309  "true",
310  "Enable floating point exceptions"
311>;
312
313class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
314  "max-private-element-size-"#size,
315  "MaxPrivateElementSize",
316  !cast<string>(size),
317  "Maximum private access size may be "#size
318>;
319
320def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
321def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
322def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
323
324def FeatureEnableHugePrivateBuffer : SubtargetFeature<
325  "huge-private-buffer",
326  "EnableHugePrivateBuffer",
327  "true",
328  "Enable private/scratch buffer sizes greater than 128 GB"
329>;
330
331def FeatureDumpCode : SubtargetFeature <"DumpCode",
332  "DumpCode",
333  "true",
334  "Dump MachineInstrs in the CodeEmitter"
335>;
336
337def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
338  "DumpCode",
339  "true",
340  "Dump MachineInstrs in the CodeEmitter"
341>;
342
343// XXX - This should probably be removed once enabled by default
344def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
345  "EnableLoadStoreOpt",
346  "true",
347  "Enable SI load/store optimizer pass"
348>;
349
350// Performance debugging feature. Allow using DS instruction immediate
351// offsets even if the base pointer can't be proven to be base. On SI,
352// base pointer values that won't give the same result as a 16-bit add
353// are not safe to fold, but this will override the conservative test
354// for the base pointer.
355def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
356  "unsafe-ds-offset-folding",
357  "EnableUnsafeDSOffsetFolding",
358  "true",
359  "Force using DS instruction immediate offsets on SI"
360>;
361
362def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
363  "EnableSIScheduler",
364  "true",
365  "Enable SI Machine Scheduler"
366>;
367
368def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
369  "EnableDS128",
370  "true",
371  "Use ds_{read|write}_b128"
372>;
373
374// Unless +-flat-for-global is specified, turn on FlatForGlobal for
375// all OS-es on VI and newer hardware to avoid assertion failures due
376// to missing ADDR64 variants of MUBUF instructions.
377// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
378// instructions.
379
380def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
381  "FlatForGlobal",
382  "true",
383  "Force to generate flat instruction for global"
384>;
385
386def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
387  "auto-waitcnt-before-barrier",
388  "AutoWaitcntBeforeBarrier",
389  "true",
390  "Hardware automatically inserts waitcnt before barrier"
391>;
392
393def FeatureCodeObjectV3 : SubtargetFeature <
394  "code-object-v3",
395  "CodeObjectV3",
396  "true",
397  "Generate code object version 3"
398>;
399
400def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
401  "HasTrigReducedRange",
402  "true",
403  "Requires use of fract on arguments to trig instructions"
404>;
405
406// Dummy feature used to disable assembler instructions.
407def FeatureDisable : SubtargetFeature<"",
408  "FeatureDisable","true",
409  "Dummy feature to disable assembler instructions"
410>;
411
412def FeatureGCN : SubtargetFeature<"gcn",
413  "IsGCN",
414  "true",
415  "GCN or newer GPU"
416>;
417
418class GCNSubtargetFeatureGeneration <string Value,
419                                  list<SubtargetFeature> Implies> :
420        SubtargetFeatureGeneration <Value, "GCNSubtarget", Implies>;
421
422def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
423  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
424  FeatureWavefrontSize64, FeatureGCN,
425  FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange]
426>;
427
428def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
429  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
430  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
431  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange]
432>;
433
434def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
435  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
436   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
437   FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts,
438   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
439   FeatureScalarStores, FeatureInv2PiInlineImm,
440   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
441   FeatureIntClamp, FeatureTrigReducedRange
442  ]
443>;
444
445def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
446  [FeatureFP64, FeatureLocalMemorySize65536,
447   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
448   FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts,
449   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
450   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
451   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
452   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
453   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
454   FeatureAddNoCarryInsts, FeatureScalarAtomics, FeatureR128A16
455  ]
456>;
457
458class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
459                                  list<SubtargetFeature> Implies>
460                                 : SubtargetFeature <
461  "isaver"#Major#"."#Minor#"."#Stepping,
462  "IsaVersion",
463  "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
464  "Instruction set version number",
465  Implies
466>;
467
468def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
469  [FeatureSouthernIslands,
470   FeatureFastFMAF32,
471   HalfRate64Ops,
472   FeatureLDSBankCount32,
473   FeatureCodeObjectV3]>;
474
475def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
476  [FeatureSouthernIslands,
477   FeatureLDSBankCount32,
478   FeatureCodeObjectV3]>;
479
480def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
481  [FeatureSeaIslands,
482   FeatureLDSBankCount32,
483   FeatureCodeObjectV3]>;
484
485def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
486  [FeatureSeaIslands,
487   HalfRate64Ops,
488   FeatureLDSBankCount32,
489   FeatureFastFMAF32,
490   FeatureCodeObjectV3]>;
491
492def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
493  [FeatureSeaIslands,
494   FeatureLDSBankCount16,
495   FeatureFastFMAF32,
496   FeatureCodeObjectV3]>;
497
498def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
499  [FeatureSeaIslands,
500   FeatureLDSBankCount16,
501   FeatureCodeObjectV3]>;
502
503def FeatureISAVersion7_0_4 : SubtargetFeatureISAVersion <7,0,4,
504  [FeatureSeaIslands,
505   FeatureLDSBankCount32,
506   FeatureCodeObjectV3]>;
507
508def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
509  [FeatureVolcanicIslands,
510   FeatureFastFMAF32,
511   HalfRate64Ops,
512   FeatureLDSBankCount32,
513   FeatureXNACK,
514   FeatureUnpackedD16VMem,
515   FeatureCodeObjectV3]>;
516
517def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
518  [FeatureVolcanicIslands,
519   FeatureLDSBankCount32,
520   FeatureSGPRInitBug,
521   FeatureUnpackedD16VMem,
522   FeatureCodeObjectV3]>;
523
524def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
525  [FeatureVolcanicIslands,
526   FeatureLDSBankCount32,
527   FeatureUnpackedD16VMem,
528   FeatureCodeObjectV3]>;
529
530def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
531  [FeatureVolcanicIslands,
532   FeatureLDSBankCount16,
533   FeatureXNACK,
534   FeatureCodeObjectV3]>;
535
536def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
537  [FeatureGFX9,
538   FeatureMadMixInsts,
539   FeatureLDSBankCount32,
540   FeatureCodeObjectV3]>;
541
542def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
543  [FeatureGFX9,
544   FeatureMadMixInsts,
545   FeatureLDSBankCount32,
546   FeatureXNACK,
547   FeatureCodeObjectV3]>;
548
549def FeatureISAVersion9_0_4 : SubtargetFeatureISAVersion <9,0,4,
550  [FeatureGFX9,
551   FeatureLDSBankCount32,
552   FeatureFmaMixInsts,
553   FeatureCodeObjectV3]>;
554
555def FeatureISAVersion9_0_6 : SubtargetFeatureISAVersion <9,0,6,
556  [FeatureGFX9,
557   HalfRate64Ops,
558   FeatureFmaMixInsts,
559   FeatureLDSBankCount32,
560   FeatureDLInsts,
561   FeatureSRAMECC,
562   FeatureCodeObjectV3]>;
563
564def FeatureISAVersion9_0_9 : SubtargetFeatureISAVersion <9,0,9,
565  [FeatureGFX9,
566   FeatureMadMixInsts,
567   FeatureLDSBankCount32,
568   FeatureXNACK,
569   FeatureCodeObjectV3]>;
570
571//===----------------------------------------------------------------------===//
572// Debugger related subtarget features.
573//===----------------------------------------------------------------------===//
574
575def FeatureDebuggerInsertNops : SubtargetFeature<
576  "amdgpu-debugger-insert-nops",
577  "DebuggerInsertNops",
578  "true",
579  "Insert one nop instruction for each high level source statement"
580>;
581
582def FeatureDebuggerEmitPrologue : SubtargetFeature<
583  "amdgpu-debugger-emit-prologue",
584  "DebuggerEmitPrologue",
585  "true",
586  "Emit debugger prologue"
587>;
588
589//===----------------------------------------------------------------------===//
590
591def AMDGPUInstrInfo : InstrInfo {
592  let guessInstructionProperties = 1;
593  let noNamedPositionallyEncodedOperands = 1;
594}
595
596def AMDGPUAsmParser : AsmParser {
597  // Some of the R600 registers have the same name, so this crashes.
598  // For example T0_XYZW and T0_XY both have the asm name T0.
599  let ShouldEmitMatchRegisterName = 0;
600}
601
602def AMDGPUAsmWriter : AsmWriter {
603  int PassSubtarget = 1;
604}
605
606def AMDGPUAsmVariants {
607  string Default = "Default";
608  int Default_ID = 0;
609  string VOP3 = "VOP3";
610  int VOP3_ID = 1;
611  string SDWA = "SDWA";
612  int SDWA_ID = 2;
613  string SDWA9 = "SDWA9";
614  int SDWA9_ID = 3;
615  string DPP = "DPP";
616  int DPP_ID = 4;
617  string Disable = "Disable";
618  int Disable_ID = 5;
619}
620
621def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
622  let Variant = AMDGPUAsmVariants.Default_ID;
623  let Name = AMDGPUAsmVariants.Default;
624}
625
626def VOP3AsmParserVariant : AsmParserVariant {
627  let Variant = AMDGPUAsmVariants.VOP3_ID;
628  let Name = AMDGPUAsmVariants.VOP3;
629}
630
631def SDWAAsmParserVariant : AsmParserVariant {
632  let Variant = AMDGPUAsmVariants.SDWA_ID;
633  let Name = AMDGPUAsmVariants.SDWA;
634}
635
636def SDWA9AsmParserVariant : AsmParserVariant {
637  let Variant = AMDGPUAsmVariants.SDWA9_ID;
638  let Name = AMDGPUAsmVariants.SDWA9;
639}
640
641
642def DPPAsmParserVariant : AsmParserVariant {
643  let Variant = AMDGPUAsmVariants.DPP_ID;
644  let Name = AMDGPUAsmVariants.DPP;
645}
646
647def AMDGPU : Target {
648  // Pull in Instruction Info:
649  let InstructionSet = AMDGPUInstrInfo;
650  let AssemblyParsers = [AMDGPUAsmParser];
651  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
652                                VOP3AsmParserVariant,
653                                SDWAAsmParserVariant,
654                                SDWA9AsmParserVariant,
655                                DPPAsmParserVariant];
656  let AssemblyWriters = [AMDGPUAsmWriter];
657  let AllowRegisterRenaming = 1;
658}
659
660// Dummy Instruction itineraries for pseudo instructions
661def ALU_NULL : FuncUnit;
662def NullALU : InstrItinClass;
663
664//===----------------------------------------------------------------------===//
665// Predicate helper class
666//===----------------------------------------------------------------------===//
667
668def isSICI : Predicate<
669  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
670  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
671>, AssemblerPredicate<"!FeatureGCN3Encoding">;
672
673def isVI : Predicate <
674  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
675  AssemblerPredicate<"FeatureGCN3Encoding">;
676
677def isGFX9 : Predicate <
678  "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
679  AssemblerPredicate<"FeatureGFX9Insts">;
680
681// TODO: Either the name to be changed or we simply use IsCI!
682def isCIVI : Predicate <
683  "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
684  AssemblerPredicate<"FeatureCIInsts">;
685
686def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
687  AssemblerPredicate<"FeatureFlatAddressSpace">;
688
689def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
690  AssemblerPredicate<"FeatureFlatGlobalInsts">;
691def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
692  AssemblerPredicate<"FeatureFlatScratchInsts">;
693def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
694  AssemblerPredicate<"FeatureGFX9Insts">;
695
696def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
697  AssemblerPredicate<"FeatureUnpackedD16VMem">;
698def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
699  AssemblerPredicate<"!FeatureUnpackedD16VMem">;
700
701def D16PreservesUnusedBits :
702  Predicate<"Subtarget->hasD16LoadStore() && !Subtarget->isSRAMECCEnabled()">,
703  AssemblerPredicate<"FeatureGFX9Insts,!FeatureSRAMECC">;
704
705def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
706def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
707
708def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
709  AssemblerPredicate<"FeatureGFX9Insts">;
710
711def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
712  AssemblerPredicate<"FeatureAddNoCarryInsts">;
713
714def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">,
715  AssemblerPredicate<"!FeatureAddNoCarryInsts">;
716
717def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
718  AssemblerPredicate<"Feature16BitInsts">;
719def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
720  AssemblerPredicate<"FeatureVOP3P">;
721
722def NotHasVOP3PInsts : Predicate<"!Subtarget->hasVOP3PInsts()">,
723  AssemblerPredicate<"!FeatureVOP3P">;
724
725def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
726  AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
727
728def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
729  AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
730
731def HasDPP : Predicate<"Subtarget->hasDPP()">,
732  AssemblerPredicate<"FeatureDPP">;
733
734def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
735  AssemblerPredicate<"FeatureR128A16">;
736
737def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
738  AssemblerPredicate<"FeatureIntClamp">;
739
740def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
741  AssemblerPredicate<"FeatureMadMixInsts">;
742
743def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
744  AssemblerPredicate<"FeatureScalarAtomics">;
745
746def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
747def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
748def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
749                      AssemblerPredicate<"FeatureVGPRIndexMode">;
750def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
751                AssemblerPredicate<"FeatureMovrel">;
752
753def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
754  AssemblerPredicate<"FeatureFmaMixInsts">;
755
756def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
757  AssemblerPredicate<"FeatureDLInsts">;
758
759
760def EnableLateCFGStructurize : Predicate<
761  "EnableLateStructurizeCFG">;
762
763// Include AMDGPU TD files
764include "SISchedule.td"
765include "GCNProcessors.td"
766include "AMDGPUInstrInfo.td"
767include "SIIntrinsics.td"
768include "AMDGPURegisterInfo.td"
769include "AMDGPURegisterBanks.td"
770include "AMDGPUInstructions.td"
771include "SIInstrInfo.td"
772include "AMDGPUCallingConv.td"
773include "AMDGPUSearchableTables.td"
774