1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21
22class BoolToList<bit Value> {
23  list<int> ret = !if(Value, [1]<int>, []<int>);
24}
25
26//===------------------------------------------------------------===//
27// Subtarget Features (device properties)
28//===------------------------------------------------------------===//
29
30def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
31  "FastFMAF32",
32  "true",
33  "Assuming f32 fma is at least as fast as mul + add"
34>;
35
36def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
37  "FastDenormalF32",
38  "true",
39  "Enabling denormals does not cause f32 instructions to run at f64 rates"
40>;
41
42def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
43  "MIMG_R128",
44  "true",
45  "Support 128-bit texture resources"
46>;
47
48def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
49  "HalfRate64Ops",
50  "true",
51  "Most fp64 instructions are half rate instead of quarter"
52>;
53
54def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
55  "FlatAddressSpace",
56  "true",
57  "Support flat address space"
58>;
59
60def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
61  "FlatInstOffsets",
62  "true",
63  "Flat instructions have immediate offset addressing mode"
64>;
65
66def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
67  "FlatGlobalInsts",
68  "true",
69  "Have global_* flat memory instructions"
70>;
71
72def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
73  "FlatScratchInsts",
74  "true",
75  "Have scratch_* flat memory instructions"
76>;
77
78def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
79  "ScalarFlatScratchInsts",
80  "true",
81  "Have s_scratch_* flat memory instructions"
82>;
83
84def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
85  "AddNoCarryInsts",
86  "true",
87  "Have VALU add/sub instructions without carry out"
88>;
89
90def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
91  "UnalignedBufferAccess",
92  "true",
93  "Support unaligned global loads and stores"
94>;
95
96def FeatureTrapHandler: SubtargetFeature<"trap-handler",
97  "TrapHandler",
98  "true",
99  "Trap handler support"
100>;
101
102def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
103  "UnalignedScratchAccess",
104  "true",
105  "Support unaligned scratch loads and stores"
106>;
107
108def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
109  "HasApertureRegs",
110  "true",
111  "Has Memory Aperture Base and Size Registers"
112>;
113
114def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
115  "HasMadMixInsts",
116  "true",
117  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
118>;
119
120def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
121  "HasFmaMixInsts",
122  "true",
123  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
124>;
125
126def FeatureDoesNotSupportXNACK : SubtargetFeature<"no-xnack-support",
127  "DoesNotSupportXNACK",
128  "true",
129  "Hardware does not support XNACK"
130>;
131
132// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
133// XNACK. The current default kernel driver setting is:
134// - graphics ring: XNACK disabled
135// - compute ring: XNACK enabled
136//
137// If XNACK is enabled, the VMEM latency can be worse.
138// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
139def FeatureXNACK : SubtargetFeature<"xnack",
140  "EnableXNACK",
141  "true",
142  "Enable XNACK support"
143>;
144
145def FeatureCuMode : SubtargetFeature<"cumode",
146  "EnableCuMode",
147  "true",
148  "Enable CU wavefront execution mode"
149>;
150
151def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
152  "SGPRInitBug",
153  "true",
154  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
155>;
156
157def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
158  "LDSMisalignedBug",
159  "true",
160  "Some GFX10 bug with misaligned multi-dword LDS access in WGP mode"
161>;
162
163def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
164  "HasMFMAInlineLiteralBug",
165  "true",
166  "MFMA cannot use inline literal as SrcC"
167>;
168
169def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
170  "HasVcmpxPermlaneHazard",
171  "true",
172  "TODO: describe me"
173>;
174
175def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
176  "HasVMEMtoScalarWriteHazard",
177  "true",
178  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
179>;
180
181def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
182  "HasSMEMtoVectorWriteHazard",
183  "true",
184  "s_load_dword followed by v_cmp page faults"
185>;
186
187def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
188  "HasInstFwdPrefetchBug",
189  "true",
190  "S_INST_PREFETCH instruction causes shader to hang"
191>;
192
193def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
194  "HasVcmpxExecWARHazard",
195  "true",
196  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
197>;
198
199def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
200  "HasLdsBranchVmemWARHazard",
201  "true",
202  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
203>;
204
205def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
206  "HasNSAtoVMEMBug",
207  "true",
208  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
209>;
210
211def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
212  "HasFlatSegmentOffsetBug",
213  "true",
214  "GFX10 bug, inst_offset ignored in flat segment"
215>;
216
217def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
218  "HasOffset3fBug",
219  "true",
220  "Branch offset of 3f hardware bug"
221>;
222
223class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
224  "ldsbankcount"#Value,
225  "LDSBankCount",
226  !cast<string>(Value),
227  "The number of LDS banks per compute unit."
228>;
229
230def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
231def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
232
233def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
234  "GCN3Encoding",
235  "true",
236  "Encoding format for VI"
237>;
238
239def FeatureCIInsts : SubtargetFeature<"ci-insts",
240  "CIInsts",
241  "true",
242  "Additional instructions for CI+"
243>;
244
245def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
246  "GFX8Insts",
247  "true",
248  "Additional instructions for GFX8+"
249>;
250
251def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
252  "GFX9Insts",
253  "true",
254  "Additional instructions for GFX9+"
255>;
256
257def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
258  "GFX10Insts",
259  "true",
260  "Additional instructions for GFX10+"
261>;
262
263def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
264  "GFX7GFX8GFX9Insts",
265  "true",
266  "Instructions shared in GFX7, GFX8, GFX9"
267>;
268
269def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
270  "HasSMemRealTime",
271  "true",
272  "Has s_memrealtime instruction"
273>;
274
275def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
276  "HasInv2PiInlineImm",
277  "true",
278  "Has 1 / (2 * pi) as inline immediate"
279>;
280
281def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
282  "Has16BitInsts",
283  "true",
284  "Has i16/f16 instructions"
285>;
286
287def FeatureVOP3P : SubtargetFeature<"vop3p",
288  "HasVOP3PInsts",
289  "true",
290  "Has VOP3P packed instructions"
291>;
292
293def FeatureMovrel : SubtargetFeature<"movrel",
294  "HasMovrel",
295  "true",
296  "Has v_movrel*_b32 instructions"
297>;
298
299def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
300  "HasVGPRIndexMode",
301  "true",
302  "Has VGPR mode register indexing"
303>;
304
305def FeatureScalarStores : SubtargetFeature<"scalar-stores",
306  "HasScalarStores",
307  "true",
308  "Has store scalar memory instructions"
309>;
310
311def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
312  "HasScalarAtomics",
313  "true",
314  "Has atomic scalar memory instructions"
315>;
316
317def FeatureSDWA : SubtargetFeature<"sdwa",
318  "HasSDWA",
319  "true",
320  "Support SDWA (Sub-DWORD Addressing) extension"
321>;
322
323def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
324  "HasSDWAOmod",
325  "true",
326  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
327>;
328
329def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
330  "HasSDWAScalar",
331  "true",
332  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
333>;
334
335def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
336  "HasSDWASdst",
337  "true",
338  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
339>;
340
341def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
342  "HasSDWAMac",
343  "true",
344  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
345>;
346
347def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
348  "HasSDWAOutModsVOPC",
349  "true",
350  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
351>;
352
353def FeatureDPP : SubtargetFeature<"dpp",
354  "HasDPP",
355  "true",
356  "Support DPP (Data Parallel Primitives) extension"
357>;
358
359// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
360def FeatureDPP8 : SubtargetFeature<"dpp8",
361  "HasDPP8",
362  "true",
363  "Support DPP8 (Data Parallel Primitives) extension"
364>;
365
366def FeatureR128A16 : SubtargetFeature<"r128-a16",
367  "HasR128A16",
368  "true",
369  "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
370>;
371
372def FeatureGFX10A16 : SubtargetFeature<"a16",
373  "HasGFX10A16",
374  "true",
375  "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
376>;
377
378def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
379  "HasNSAEncoding",
380  "true",
381  "Support NSA encoding for image instructions"
382>;
383
384def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
385  "HasIntClamp",
386  "true",
387  "Support clamp for integer destination"
388>;
389
390def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
391  "HasUnpackedD16VMem",
392  "true",
393  "Has unpacked d16 vmem instructions"
394>;
395
396def FeatureDLInsts : SubtargetFeature<"dl-insts",
397  "HasDLInsts",
398  "true",
399  "Has v_fmac_f32 and v_xnor_b32 instructions"
400>;
401
402def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
403  "HasDot1Insts",
404  "true",
405  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
406>;
407
408def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
409  "HasDot2Insts",
410  "true",
411  "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
412>;
413
414def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
415  "HasDot3Insts",
416  "true",
417  "Has v_dot8c_i32_i4 instruction"
418>;
419
420def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
421  "HasDot4Insts",
422  "true",
423  "Has v_dot2c_i32_i16 instruction"
424>;
425
426def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
427  "HasDot5Insts",
428  "true",
429  "Has v_dot2c_f32_f16 instruction"
430>;
431
432def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
433  "HasDot6Insts",
434  "true",
435  "Has v_dot4c_i32_i8 instruction"
436>;
437
438def FeatureMAIInsts : SubtargetFeature<"mai-insts",
439  "HasMAIInsts",
440  "true",
441  "Has mAI instructions"
442>;
443
444def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
445  "HasPkFmacF16Inst",
446  "true",
447  "Has v_pk_fmac_f16 instruction"
448>;
449
450def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
451  "HasAtomicFaddInsts",
452  "true",
453  "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
454  "global_atomic_pk_add_f16 instructions",
455  [FeatureFlatGlobalInsts]
456>;
457
458def FeatureDoesNotSupportSRAMECC : SubtargetFeature<"no-sram-ecc-support",
459  "DoesNotSupportSRAMECC",
460  "true",
461  "Hardware does not support SRAM ECC"
462>;
463
464def FeatureSRAMECC : SubtargetFeature<"sram-ecc",
465  "EnableSRAMECC",
466  "true",
467  "Enable SRAM ECC"
468>;
469
470def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
471  "HasNoSdstCMPX",
472  "true",
473  "V_CMPX does not write VCC/SGPR in addition to EXEC"
474>;
475
476def FeatureVscnt : SubtargetFeature<"vscnt",
477  "HasVscnt",
478  "true",
479  "Has separate store vscnt counter"
480>;
481
482def FeatureRegisterBanking : SubtargetFeature<"register-banking",
483  "HasRegisterBanking",
484  "true",
485  "Has register banking"
486>;
487
488def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
489  "HasVOP3Literal",
490  "true",
491  "Can use one literal in VOP3"
492>;
493
494def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
495  "HasNoDataDepHazard",
496  "true",
497  "Does not need SW waitstates"
498>;
499
500//===------------------------------------------------------------===//
501// Subtarget Features (options and debugging)
502//===------------------------------------------------------------===//
503
504class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
505  "max-private-element-size-"#size,
506  "MaxPrivateElementSize",
507  !cast<string>(size),
508  "Maximum private access size may be "#size
509>;
510
511def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
512def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
513def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
514
515def FeatureDumpCode : SubtargetFeature <"DumpCode",
516  "DumpCode",
517  "true",
518  "Dump MachineInstrs in the CodeEmitter"
519>;
520
521def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
522  "DumpCode",
523  "true",
524  "Dump MachineInstrs in the CodeEmitter"
525>;
526
527// XXX - This should probably be removed once enabled by default
528def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
529  "EnableLoadStoreOpt",
530  "true",
531  "Enable SI load/store optimizer pass"
532>;
533
534// Performance debugging feature. Allow using DS instruction immediate
535// offsets even if the base pointer can't be proven to be base. On SI,
536// base pointer values that won't give the same result as a 16-bit add
537// are not safe to fold, but this will override the conservative test
538// for the base pointer.
539def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
540  "unsafe-ds-offset-folding",
541  "EnableUnsafeDSOffsetFolding",
542  "true",
543  "Force using DS instruction immediate offsets on SI"
544>;
545
546def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
547  "EnableSIScheduler",
548  "true",
549  "Enable SI Machine Scheduler"
550>;
551
552def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
553  "EnableDS128",
554  "true",
555  "Use ds_{read|write}_b128"
556>;
557
558// Sparse texture support requires that all result registers are zeroed when
559// PRTStrictNull is set to true. This feature is turned on for all architectures
560// but is enabled as a feature in case there are situations where PRTStrictNull
561// is disabled by the driver.
562def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
563  "EnablePRTStrictNull",
564  "true",
565  "Enable zeroing of result registers for sparse texture fetches"
566>;
567
568// Unless +-flat-for-global is specified, turn on FlatForGlobal for
569// all OS-es on VI and newer hardware to avoid assertion failures due
570// to missing ADDR64 variants of MUBUF instructions.
571// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
572// instructions.
573
574def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
575  "FlatForGlobal",
576  "true",
577  "Force to generate flat instruction for global"
578>;
579
580def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
581  "auto-waitcnt-before-barrier",
582  "AutoWaitcntBeforeBarrier",
583  "true",
584  "Hardware automatically inserts waitcnt before barrier"
585>;
586
587def FeatureCodeObjectV3 : SubtargetFeature <
588  "code-object-v3",
589  "CodeObjectV3",
590  "true",
591  "Generate code object version 3"
592>;
593
594def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
595  "HasTrigReducedRange",
596  "true",
597  "Requires use of fract on arguments to trig instructions"
598>;
599
600// Dummy feature used to disable assembler instructions.
601def FeatureDisable : SubtargetFeature<"",
602  "FeatureDisable","true",
603  "Dummy feature to disable assembler instructions"
604>;
605
606class GCNSubtargetFeatureGeneration <string Value,
607                                     string FeatureName,
608                                     list<SubtargetFeature> Implies> :
609        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
610
611def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
612    "southern-islands",
613  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
614  FeatureWavefrontSize64,
615  FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange,
616  FeatureDoesNotSupportSRAMECC, FeatureDoesNotSupportXNACK]
617>;
618
619def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
620    "sea-islands",
621  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
622  FeatureWavefrontSize64, FeatureFlatAddressSpace,
623  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
624  FeatureGFX7GFX8GFX9Insts, FeatureDoesNotSupportSRAMECC]
625>;
626
627def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
628  "volcanic-islands",
629  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
630   FeatureWavefrontSize64, FeatureFlatAddressSpace,
631   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
632   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
633   FeatureScalarStores, FeatureInv2PiInlineImm,
634   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
635   FeatureIntClamp, FeatureTrigReducedRange, FeatureDoesNotSupportSRAMECC,
636   FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts, FeatureFastDenormalF32
637  ]
638>;
639
640def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
641  "gfx9",
642  [FeatureFP64, FeatureLocalMemorySize65536,
643   FeatureWavefrontSize64, FeatureFlatAddressSpace,
644   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
645   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
646   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
647   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
648   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
649   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
650   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
651   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
652   FeatureFastDenormalF32]
653>;
654
655def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
656  "gfx10",
657  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
658   FeatureFlatAddressSpace,
659   FeatureCIInsts, Feature16BitInsts,
660   FeatureSMemRealTime, FeatureInv2PiInlineImm,
661   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
662   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
663   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
664   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
665   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
666   FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
667   FeatureVOP3Literal, FeatureDPP8,
668   FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureDoesNotSupportSRAMECC,
669   FeatureGFX10A16, FeatureFastDenormalF32
670  ]
671>;
672
673class FeatureSet<list<SubtargetFeature> Features_> {
674  list<SubtargetFeature> Features = Features_;
675}
676
677def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
678   FeatureFastFMAF32,
679   HalfRate64Ops,
680   FeatureLDSBankCount32,
681   FeatureDoesNotSupportXNACK,
682   FeatureCodeObjectV3]>;
683
684def FeatureISAVersion6_0_1 : FeatureSet<
685  [FeatureSouthernIslands,
686   FeatureLDSBankCount32,
687   FeatureDoesNotSupportXNACK,
688   FeatureCodeObjectV3]>;
689
690def FeatureISAVersion7_0_0 : FeatureSet<
691  [FeatureSeaIslands,
692   FeatureLDSBankCount32,
693   FeatureDoesNotSupportXNACK,
694   FeatureCodeObjectV3]>;
695
696def FeatureISAVersion7_0_1 : FeatureSet<
697  [FeatureSeaIslands,
698   HalfRate64Ops,
699   FeatureLDSBankCount32,
700   FeatureFastFMAF32,
701   FeatureDoesNotSupportXNACK,
702   FeatureCodeObjectV3]>;
703
704def FeatureISAVersion7_0_2 : FeatureSet<
705  [FeatureSeaIslands,
706   FeatureLDSBankCount16,
707   FeatureFastFMAF32,
708   FeatureDoesNotSupportXNACK,
709   FeatureCodeObjectV3]>;
710
711def FeatureISAVersion7_0_3 : FeatureSet<
712  [FeatureSeaIslands,
713   FeatureLDSBankCount16,
714   FeatureDoesNotSupportXNACK,
715   FeatureCodeObjectV3]>;
716
717def FeatureISAVersion7_0_4 : FeatureSet<
718  [FeatureSeaIslands,
719   FeatureLDSBankCount32,
720   FeatureDoesNotSupportXNACK,
721   FeatureCodeObjectV3]>;
722
723def FeatureISAVersion8_0_1 : FeatureSet<
724  [FeatureVolcanicIslands,
725   FeatureFastFMAF32,
726   HalfRate64Ops,
727   FeatureLDSBankCount32,
728   FeatureXNACK,
729   FeatureUnpackedD16VMem,
730   FeatureCodeObjectV3]>;
731
732def FeatureISAVersion8_0_2 : FeatureSet<
733  [FeatureVolcanicIslands,
734   FeatureLDSBankCount32,
735   FeatureSGPRInitBug,
736   FeatureUnpackedD16VMem,
737   FeatureDoesNotSupportXNACK,
738   FeatureCodeObjectV3]>;
739
740def FeatureISAVersion8_0_3 : FeatureSet<
741  [FeatureVolcanicIslands,
742   FeatureLDSBankCount32,
743   FeatureUnpackedD16VMem,
744   FeatureDoesNotSupportXNACK,
745   FeatureCodeObjectV3]>;
746
747def FeatureISAVersion8_1_0 : FeatureSet<
748  [FeatureVolcanicIslands,
749   FeatureLDSBankCount16,
750   FeatureXNACK,
751   FeatureCodeObjectV3]>;
752
753def FeatureISAVersion9_0_0 : FeatureSet<
754  [FeatureGFX9,
755   FeatureMadMixInsts,
756   FeatureLDSBankCount32,
757   FeatureCodeObjectV3,
758   FeatureDoesNotSupportXNACK,
759   FeatureDoesNotSupportSRAMECC]>;
760
761def FeatureISAVersion9_0_2 : FeatureSet<
762  [FeatureGFX9,
763   FeatureMadMixInsts,
764   FeatureLDSBankCount32,
765   FeatureXNACK,
766   FeatureDoesNotSupportSRAMECC,
767   FeatureCodeObjectV3]>;
768
769def FeatureISAVersion9_0_4 : FeatureSet<
770  [FeatureGFX9,
771   FeatureLDSBankCount32,
772   FeatureFmaMixInsts,
773   FeatureDoesNotSupportXNACK,
774   FeatureDoesNotSupportSRAMECC,
775   FeatureCodeObjectV3]>;
776
777def FeatureISAVersion9_0_6 : FeatureSet<
778  [FeatureGFX9,
779   HalfRate64Ops,
780   FeatureFmaMixInsts,
781   FeatureLDSBankCount32,
782   FeatureDLInsts,
783   FeatureDot1Insts,
784   FeatureDot2Insts,
785   FeatureDoesNotSupportXNACK,
786   FeatureCodeObjectV3]>;
787
788def FeatureISAVersion9_0_8 : FeatureSet<
789  [FeatureGFX9,
790   HalfRate64Ops,
791   FeatureFmaMixInsts,
792   FeatureLDSBankCount32,
793   FeatureDLInsts,
794   FeatureDot1Insts,
795   FeatureDot2Insts,
796   FeatureDot3Insts,
797   FeatureDot4Insts,
798   FeatureDot5Insts,
799   FeatureDot6Insts,
800   FeatureMAIInsts,
801   FeaturePkFmacF16Inst,
802   FeatureAtomicFaddInsts,
803   FeatureSRAMECC,
804   FeatureMFMAInlineLiteralBug,
805   FeatureCodeObjectV3]>;
806
807def FeatureISAVersion9_0_9 : FeatureSet<
808  [FeatureGFX9,
809   FeatureMadMixInsts,
810   FeatureLDSBankCount32,
811   FeatureXNACK,
812   FeatureCodeObjectV3]>;
813
814// TODO: Organize more features into groups.
815def FeatureGroup {
816  // Bugs present on gfx10.1.
817  list<SubtargetFeature> GFX10_1_Bugs = [
818    FeatureVcmpxPermlaneHazard,
819    FeatureVMEMtoScalarWriteHazard,
820    FeatureSMEMtoVectorWriteHazard,
821    FeatureInstFwdPrefetchBug,
822    FeatureVcmpxExecWARHazard,
823    FeatureLdsBranchVmemWARHazard,
824    FeatureNSAtoVMEMBug,
825    FeatureOffset3fBug,
826    FeatureFlatSegmentOffsetBug
827   ];
828}
829
830def FeatureISAVersion10_1_0 : FeatureSet<
831  !listconcat(FeatureGroup.GFX10_1_Bugs,
832    [FeatureGFX10,
833     FeatureLDSBankCount32,
834     FeatureDLInsts,
835     FeatureNSAEncoding,
836     FeatureWavefrontSize32,
837     FeatureScalarStores,
838     FeatureScalarAtomics,
839     FeatureScalarFlatScratchInsts,
840     FeatureLdsMisalignedBug,
841     FeatureDoesNotSupportXNACK,
842     FeatureCodeObjectV3])>;
843
844def FeatureISAVersion10_1_1 : FeatureSet<
845  !listconcat(FeatureGroup.GFX10_1_Bugs,
846    [FeatureGFX10,
847     FeatureLDSBankCount32,
848     FeatureDLInsts,
849     FeatureDot1Insts,
850     FeatureDot2Insts,
851     FeatureDot5Insts,
852     FeatureDot6Insts,
853     FeatureNSAEncoding,
854     FeatureWavefrontSize32,
855     FeatureScalarStores,
856     FeatureScalarAtomics,
857     FeatureScalarFlatScratchInsts,
858     FeatureDoesNotSupportXNACK,
859     FeatureCodeObjectV3])>;
860
861def FeatureISAVersion10_1_2 : FeatureSet<
862  !listconcat(FeatureGroup.GFX10_1_Bugs,
863    [FeatureGFX10,
864     FeatureLDSBankCount32,
865     FeatureDLInsts,
866     FeatureDot1Insts,
867     FeatureDot2Insts,
868     FeatureDot5Insts,
869     FeatureDot6Insts,
870     FeatureNSAEncoding,
871     FeatureWavefrontSize32,
872     FeatureScalarStores,
873     FeatureScalarAtomics,
874     FeatureScalarFlatScratchInsts,
875     FeatureLdsMisalignedBug,
876     FeatureDoesNotSupportXNACK,
877     FeatureCodeObjectV3])>;
878
879//===----------------------------------------------------------------------===//
880
881def AMDGPUInstrInfo : InstrInfo {
882  let guessInstructionProperties = 1;
883  let noNamedPositionallyEncodedOperands = 1;
884}
885
886def AMDGPUAsmParser : AsmParser {
887  // Some of the R600 registers have the same name, so this crashes.
888  // For example T0_XYZW and T0_XY both have the asm name T0.
889  let ShouldEmitMatchRegisterName = 0;
890}
891
892def AMDGPUAsmWriter : AsmWriter {
893  int PassSubtarget = 1;
894}
895
896def AMDGPUAsmVariants {
897  string Default = "Default";
898  int Default_ID = 0;
899  string VOP3 = "VOP3";
900  int VOP3_ID = 1;
901  string SDWA = "SDWA";
902  int SDWA_ID = 2;
903  string SDWA9 = "SDWA9";
904  int SDWA9_ID = 3;
905  string DPP = "DPP";
906  int DPP_ID = 4;
907  string Disable = "Disable";
908  int Disable_ID = 5;
909}
910
911def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
912  let Variant = AMDGPUAsmVariants.Default_ID;
913  let Name = AMDGPUAsmVariants.Default;
914}
915
916def VOP3AsmParserVariant : AsmParserVariant {
917  let Variant = AMDGPUAsmVariants.VOP3_ID;
918  let Name = AMDGPUAsmVariants.VOP3;
919}
920
921def SDWAAsmParserVariant : AsmParserVariant {
922  let Variant = AMDGPUAsmVariants.SDWA_ID;
923  let Name = AMDGPUAsmVariants.SDWA;
924}
925
926def SDWA9AsmParserVariant : AsmParserVariant {
927  let Variant = AMDGPUAsmVariants.SDWA9_ID;
928  let Name = AMDGPUAsmVariants.SDWA9;
929}
930
931
932def DPPAsmParserVariant : AsmParserVariant {
933  let Variant = AMDGPUAsmVariants.DPP_ID;
934  let Name = AMDGPUAsmVariants.DPP;
935}
936
937def AMDGPU : Target {
938  // Pull in Instruction Info:
939  let InstructionSet = AMDGPUInstrInfo;
940  let AssemblyParsers = [AMDGPUAsmParser];
941  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
942                                VOP3AsmParserVariant,
943                                SDWAAsmParserVariant,
944                                SDWA9AsmParserVariant,
945                                DPPAsmParserVariant];
946  let AssemblyWriters = [AMDGPUAsmWriter];
947  let AllowRegisterRenaming = 1;
948}
949
950// Dummy Instruction itineraries for pseudo instructions
951def ALU_NULL : FuncUnit;
952def NullALU : InstrItinClass;
953
954//===----------------------------------------------------------------------===//
955// Predicate helper class
956//===----------------------------------------------------------------------===//
957
958def isGFX6 :
959  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
960  AssemblerPredicate<(all_of FeatureSouthernIslands)>;
961
962def isGFX6GFX7 :
963  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
964            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
965  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
966
967def isGFX6GFX7GFX10 :
968  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
969            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
970            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
971  AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
972
973def isGFX7Only :
974  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
975  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
976
977def isGFX7GFX10 :
978  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
979            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
980  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
981
982def isGFX7GFX8GFX9 :
983  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
984            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
985            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
986  AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
987
988def isGFX6GFX7GFX8GFX9 :
989  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
990            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
991            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
992            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
993  AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
994
995def isGFX7Plus :
996  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
997  AssemblerPredicate<(all_of FeatureCIInsts)>;
998
999def isGFX8Plus :
1000  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1001  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1002
1003def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1004                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1005  AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1006
1007def isGFX9Plus :
1008  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1009  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1010
1011def isGFX9Only : Predicate <
1012  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1013  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1014
1015def isGFX8GFX9 :
1016  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1017            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1018  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1019
1020def isGFX10Plus :
1021  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1022  AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1023
1024def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1025  AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1026
1027def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1028  AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1029def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1030  AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1031def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1032  AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1033def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1034  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1035
1036def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1037  AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1038def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1039  AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1040
1041def D16PreservesUnusedBits :
1042  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1043  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1044
1045def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1046def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1047
1048def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1049  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1050
1051def HasLDSFPAtomics : Predicate<"Subtarget->hasLDSFPAtomics()">,
1052  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1053
1054def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1055  AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1056
1057def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1058
1059def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1060  AssemblerPredicate<(all_of Feature16BitInsts)>;
1061def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1062  AssemblerPredicate<(all_of FeatureVOP3P)>;
1063
1064def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
1065def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
1066
1067def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1068  AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1069
1070def HasSDWA9 :
1071  Predicate<"Subtarget->hasSDWA()">,
1072  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1073
1074def HasSDWA10 :
1075  Predicate<"Subtarget->hasSDWA()">,
1076  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1077
1078def HasDPP : Predicate<"Subtarget->hasDPP()">,
1079  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1080
1081def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1082  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1083
1084def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1085  AssemblerPredicate<(all_of FeatureR128A16)>;
1086
1087def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1088  AssemblerPredicate<(all_of FeatureGFX10A16)>;
1089
1090def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1091  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1092
1093def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1094  AssemblerPredicate<(all_of FeatureIntClamp)>;
1095
1096def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1097  AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1098
1099def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1100  AssemblerPredicate<(all_of FeatureScalarStores)>;
1101
1102def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1103  AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1104
1105def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1106  AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1107
1108def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1109  AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1110
1111def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1112def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1113def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1114                      AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1115def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1116                AssemblerPredicate<(all_of FeatureMovrel)>;
1117
1118def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1119  AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1120
1121def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1122  AssemblerPredicate<(all_of FeatureDLInsts)>;
1123
1124def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1125  AssemblerPredicate<(all_of FeatureDot1Insts)>;
1126
1127def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1128  AssemblerPredicate<(all_of FeatureDot2Insts)>;
1129
1130def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1131  AssemblerPredicate<(all_of FeatureDot3Insts)>;
1132
1133def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1134  AssemblerPredicate<(all_of FeatureDot4Insts)>;
1135
1136def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1137  AssemblerPredicate<(all_of FeatureDot5Insts)>;
1138
1139def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1140  AssemblerPredicate<(all_of FeatureDot6Insts)>;
1141
1142def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1143  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1144
1145def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1146  AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1147
1148def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1149  AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>;
1150
1151def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">,
1152  AssemblerPredicate<(all_of FeatureOffset3fBug)>;
1153
1154def EnableLateCFGStructurize : Predicate<
1155  "EnableLateStructurizeCFG">;
1156
1157// Include AMDGPU TD files
1158include "SISchedule.td"
1159include "GCNProcessors.td"
1160include "AMDGPUInstrInfo.td"
1161include "SIRegisterInfo.td"
1162include "AMDGPURegisterBanks.td"
1163include "AMDGPUInstructions.td"
1164include "SIInstrInfo.td"
1165include "AMDGPUCallingConv.td"
1166include "AMDGPUSearchableTables.td"
1167