1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21
22class BoolToList<bit Value> {
23  list<int> ret = !if(Value, [1]<int>, []<int>);
24}
25
26//===------------------------------------------------------------===//
27// Subtarget Features (device properties)
28//===------------------------------------------------------------===//
29
30def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
31  "FastFMAF32",
32  "true",
33  "Assuming f32 fma is at least as fast as mul + add"
34>;
35
36def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
37  "FastDenormalF32",
38  "true",
39  "Enabling denormals does not cause f32 instructions to run at f64 rates"
40>;
41
42def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
43  "MIMG_R128",
44  "true",
45  "Support 128-bit texture resources"
46>;
47
48def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
49  "HalfRate64Ops",
50  "true",
51  "Most fp64 instructions are half rate instead of quarter"
52>;
53
54def FullRate64Ops : SubtargetFeature<"full-rate-64-ops",
55  "FullRate64Ops",
56  "true",
57  "Most fp64 instructions are full rate"
58>;
59
60def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
61  "FlatAddressSpace",
62  "true",
63  "Support flat address space"
64>;
65
66def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
67  "FlatInstOffsets",
68  "true",
69  "Flat instructions have immediate offset addressing mode"
70>;
71
72def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
73  "FlatGlobalInsts",
74  "true",
75  "Have global_* flat memory instructions"
76>;
77
78def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
79  "FlatScratchInsts",
80  "true",
81  "Have scratch_* flat memory instructions"
82>;
83
84def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
85  "ScalarFlatScratchInsts",
86  "true",
87  "Have s_scratch_* flat memory instructions"
88>;
89
90def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
91  "AddNoCarryInsts",
92  "true",
93  "Have VALU add/sub instructions without carry out"
94>;
95
96def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
97  "UnalignedBufferAccess",
98  "true",
99  "Hardware supports unaligned global loads and stores"
100>;
101
102def FeatureTrapHandler: SubtargetFeature<"trap-handler",
103  "TrapHandler",
104  "true",
105  "Trap handler support"
106>;
107
108def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
109  "UnalignedScratchAccess",
110  "true",
111  "Support unaligned scratch loads and stores"
112>;
113
114def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access",
115  "UnalignedDSAccess",
116  "true",
117  "Hardware supports unaligned local and region loads and stores"
118>;
119
120def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
121  "HasApertureRegs",
122  "true",
123  "Has Memory Aperture Base and Size Registers"
124>;
125
126def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
127  "HasMadMixInsts",
128  "true",
129  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
130>;
131
132def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
133  "HasFmaMixInsts",
134  "true",
135  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
136>;
137
138def FeatureSupportsXNACK : SubtargetFeature<"xnack-support",
139  "SupportsXNACK",
140  "true",
141  "Hardware supports XNACK"
142>;
143
144// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
145// XNACK. The current default kernel driver setting is:
146// - graphics ring: XNACK disabled
147// - compute ring: XNACK enabled
148//
149// If XNACK is enabled, the VMEM latency can be worse.
150// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
151def FeatureXNACK : SubtargetFeature<"xnack",
152  "EnableXNACK",
153  "true",
154  "Enable XNACK support"
155>;
156
157def FeatureTgSplit : SubtargetFeature<"tgsplit",
158  "EnableTgSplit",
159  "true",
160  "Enable threadgroup split execution"
161>;
162
163def FeatureCuMode : SubtargetFeature<"cumode",
164  "EnableCuMode",
165  "true",
166  "Enable CU wavefront execution mode"
167>;
168
169def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
170  "SGPRInitBug",
171  "true",
172  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
173>;
174
175def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
176  "LDSMisalignedBug",
177  "true",
178  "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode"
179>;
180
181def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
182  "HasMFMAInlineLiteralBug",
183  "true",
184  "MFMA cannot use inline literal as SrcC"
185>;
186
187def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
188  "HasVcmpxPermlaneHazard",
189  "true",
190  "TODO: describe me"
191>;
192
193def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
194  "HasVMEMtoScalarWriteHazard",
195  "true",
196  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
197>;
198
199def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
200  "HasSMEMtoVectorWriteHazard",
201  "true",
202  "s_load_dword followed by v_cmp page faults"
203>;
204
205def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
206  "HasInstFwdPrefetchBug",
207  "true",
208  "S_INST_PREFETCH instruction causes shader to hang"
209>;
210
211def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
212  "HasVcmpxExecWARHazard",
213  "true",
214  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
215>;
216
217def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
218  "HasLdsBranchVmemWARHazard",
219  "true",
220  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
221>;
222
223def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
224  "HasNSAtoVMEMBug",
225  "true",
226  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
227>;
228
229def FeatureNSAClauseBug : SubtargetFeature<"nsa-clause-bug",
230  "HasNSAClauseBug",
231  "true",
232  "MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
233>;
234
235def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
236  "HasFlatSegmentOffsetBug",
237  "true",
238  "GFX10 bug where inst_offset is ignored when flat instructions access global memory"
239>;
240
241def FeatureNegativeScratchOffsetBug : SubtargetFeature<"negative-scratch-offset-bug",
242  "NegativeScratchOffsetBug",
243  "true",
244  "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9"
245>;
246
247def FeatureNegativeUnalignedScratchOffsetBug : SubtargetFeature<"negative-unaligned-scratch-offset-bug",
248  "NegativeUnalignedScratchOffsetBug",
249  "true",
250  "Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10"
251>;
252
253def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
254  "HasOffset3fBug",
255  "true",
256  "Branch offset of 3f hardware bug"
257>;
258
259def FeatureImageStoreD16Bug : SubtargetFeature<"image-store-d16-bug",
260  "HasImageStoreD16Bug",
261  "true",
262  "Image Store D16 hardware bug"
263>;
264
265def FeatureImageGather4D16Bug : SubtargetFeature<"image-gather4-d16-bug",
266  "HasImageGather4D16Bug",
267  "true",
268  "Image Gather4 D16 hardware bug"
269>;
270
271class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
272  "ldsbankcount"#Value,
273  "LDSBankCount",
274  !cast<string>(Value),
275  "The number of LDS banks per compute unit."
276>;
277
278def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
279def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
280
281def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
282  "GCN3Encoding",
283  "true",
284  "Encoding format for VI"
285>;
286
287def FeatureCIInsts : SubtargetFeature<"ci-insts",
288  "CIInsts",
289  "true",
290  "Additional instructions for CI+"
291>;
292
293def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
294  "GFX8Insts",
295  "true",
296  "Additional instructions for GFX8+"
297>;
298
299def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
300  "GFX9Insts",
301  "true",
302  "Additional instructions for GFX9+"
303>;
304
305def FeatureGFX90AInsts : SubtargetFeature<"gfx90a-insts",
306  "GFX90AInsts",
307  "true",
308  "Additional instructions for GFX90A+"
309>;
310
311def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
312  "GFX10Insts",
313  "true",
314  "Additional instructions for GFX10+"
315>;
316
317def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts",
318  "GFX10_3Insts",
319  "true",
320  "Additional instructions for GFX10.3"
321>;
322
323def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
324  "GFX7GFX8GFX9Insts",
325  "true",
326  "Instructions shared in GFX7, GFX8, GFX9"
327>;
328
329def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
330  "HasSMemRealTime",
331  "true",
332  "Has s_memrealtime instruction"
333>;
334
335def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
336  "HasInv2PiInlineImm",
337  "true",
338  "Has 1 / (2 * pi) as inline immediate"
339>;
340
341def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
342  "Has16BitInsts",
343  "true",
344  "Has i16/f16 instructions"
345>;
346
347def FeatureVOP3P : SubtargetFeature<"vop3p",
348  "HasVOP3PInsts",
349  "true",
350  "Has VOP3P packed instructions"
351>;
352
353def FeatureMovrel : SubtargetFeature<"movrel",
354  "HasMovrel",
355  "true",
356  "Has v_movrel*_b32 instructions"
357>;
358
359def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
360  "HasVGPRIndexMode",
361  "true",
362  "Has VGPR mode register indexing"
363>;
364
365def FeatureScalarStores : SubtargetFeature<"scalar-stores",
366  "HasScalarStores",
367  "true",
368  "Has store scalar memory instructions"
369>;
370
371def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
372  "HasScalarAtomics",
373  "true",
374  "Has atomic scalar memory instructions"
375>;
376
377def FeatureSDWA : SubtargetFeature<"sdwa",
378  "HasSDWA",
379  "true",
380  "Support SDWA (Sub-DWORD Addressing) extension"
381>;
382
383def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
384  "HasSDWAOmod",
385  "true",
386  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
387>;
388
389def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
390  "HasSDWAScalar",
391  "true",
392  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
393>;
394
395def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
396  "HasSDWASdst",
397  "true",
398  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
399>;
400
401def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
402  "HasSDWAMac",
403  "true",
404  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
405>;
406
407def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
408  "HasSDWAOutModsVOPC",
409  "true",
410  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
411>;
412
413def FeatureDPP : SubtargetFeature<"dpp",
414  "HasDPP",
415  "true",
416  "Support DPP (Data Parallel Primitives) extension"
417>;
418
419// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
420def FeatureDPP8 : SubtargetFeature<"dpp8",
421  "HasDPP8",
422  "true",
423  "Support DPP8 (Data Parallel Primitives) extension"
424>;
425
426def Feature64BitDPP : SubtargetFeature<"dpp-64bit",
427  "Has64BitDPP",
428  "true",
429  "Support DPP (Data Parallel Primitives) extension"
430>;
431
432def FeaturePackedFP32Ops : SubtargetFeature<"packed-fp32-ops",
433  "HasPackedFP32Ops",
434  "true",
435  "Support packed fp32 instructions"
436>;
437
438def FeatureR128A16 : SubtargetFeature<"r128-a16",
439  "HasR128A16",
440  "true",
441  "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
442>;
443
444def FeatureGFX10A16 : SubtargetFeature<"a16",
445  "HasGFX10A16",
446  "true",
447  "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
448>;
449
450def FeatureG16 : SubtargetFeature<"g16",
451  "HasG16",
452  "true",
453  "Support G16 for 16-bit gradient image operands"
454>;
455
456def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
457  "HasNSAEncoding",
458  "true",
459  "Support NSA encoding for image instructions"
460>;
461
462def FeatureExtendedImageInsts : SubtargetFeature<"extended-image-insts",
463  "HasExtendedImageInsts",
464  "true",
465  "Support mips != 0, lod != 0, gather4, and get_lod"
466>;
467
468def FeatureGFX10_BEncoding : SubtargetFeature<"gfx10_b-encoding",
469  "GFX10_BEncoding",
470  "true",
471  "Encoding format GFX10_B"
472>;
473
474def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
475  "HasIntClamp",
476  "true",
477  "Support clamp for integer destination"
478>;
479
480def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
481  "HasUnpackedD16VMem",
482  "true",
483  "Has unpacked d16 vmem instructions"
484>;
485
486def FeatureDLInsts : SubtargetFeature<"dl-insts",
487  "HasDLInsts",
488  "true",
489  "Has v_fmac_f32 and v_xnor_b32 instructions"
490>;
491
492def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
493  "HasDot1Insts",
494  "true",
495  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
496>;
497
498def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
499  "HasDot2Insts",
500  "true",
501  "Has v_dot2_i32_i16, v_dot2_u32_u16 instructions"
502>;
503
504def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
505  "HasDot3Insts",
506  "true",
507  "Has v_dot8c_i32_i4 instruction"
508>;
509
510def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
511  "HasDot4Insts",
512  "true",
513  "Has v_dot2c_i32_i16 instruction"
514>;
515
516def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
517  "HasDot5Insts",
518  "true",
519  "Has v_dot2c_f32_f16 instruction"
520>;
521
522def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
523  "HasDot6Insts",
524  "true",
525  "Has v_dot4c_i32_i8 instruction"
526>;
527
528def FeatureDot7Insts : SubtargetFeature<"dot7-insts",
529  "HasDot7Insts",
530  "true",
531  "Has v_dot2_f32_f16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
532>;
533
534def FeatureMAIInsts : SubtargetFeature<"mai-insts",
535  "HasMAIInsts",
536  "true",
537  "Has mAI instructions"
538>;
539
540def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
541  "HasPkFmacF16Inst",
542  "true",
543  "Has v_pk_fmac_f16 instruction"
544>;
545
546def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
547  "HasAtomicFaddInsts",
548  "true",
549  "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
550  "global_atomic_pk_add_f16 instructions",
551  [FeatureFlatGlobalInsts]
552>;
553
554def FeatureSupportsSRAMECC : SubtargetFeature<"sramecc-support",
555  "SupportsSRAMECC",
556  "true",
557  "Hardware supports SRAMECC"
558>;
559
560def FeatureSRAMECC : SubtargetFeature<"sramecc",
561  "EnableSRAMECC",
562  "true",
563  "Enable SRAMECC"
564>;
565
566def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
567  "HasNoSdstCMPX",
568  "true",
569  "V_CMPX does not write VCC/SGPR in addition to EXEC"
570>;
571
572def FeatureVscnt : SubtargetFeature<"vscnt",
573  "HasVscnt",
574  "true",
575  "Has separate store vscnt counter"
576>;
577
578def FeatureGetWaveIdInst : SubtargetFeature<"get-wave-id-inst",
579  "HasGetWaveIdInst",
580  "true",
581  "Has s_get_waveid_in_workgroup instruction"
582>;
583
584def FeatureSMemTimeInst : SubtargetFeature<"s-memtime-inst",
585  "HasSMemTimeInst",
586  "true",
587  "Has s_memtime instruction"
588>;
589
590def FeatureShaderCyclesRegister : SubtargetFeature<"shader-cycles-register",
591  "HasShaderCyclesRegister",
592  "true",
593  "Has SHADER_CYCLES hardware register"
594>;
595
596def FeatureMadMacF32Insts : SubtargetFeature<"mad-mac-f32-insts",
597  "HasMadMacF32Insts",
598  "true",
599  "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions"
600>;
601
602def FeatureDsSrc2Insts : SubtargetFeature<"ds-src2-insts",
603  "HasDsSrc2Insts",
604  "true",
605  "Has ds_*_src2 instructions"
606>;
607
608def FeatureRegisterBanking : SubtargetFeature<"register-banking",
609  "HasRegisterBanking",
610  "true",
611  "Has register banking"
612>;
613
614def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
615  "HasVOP3Literal",
616  "true",
617  "Can use one literal in VOP3"
618>;
619
620def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
621  "HasNoDataDepHazard",
622  "true",
623  "Does not need SW waitstates"
624>;
625
626//===------------------------------------------------------------===//
627// Subtarget Features (options and debugging)
628//===------------------------------------------------------------===//
629
630class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
631  "max-private-element-size-"#size,
632  "MaxPrivateElementSize",
633  !cast<string>(size),
634  "Maximum private access size may be "#size
635>;
636
637def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
638def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
639def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
640
641def FeatureDumpCode : SubtargetFeature <"DumpCode",
642  "DumpCode",
643  "true",
644  "Dump MachineInstrs in the CodeEmitter"
645>;
646
647def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
648  "DumpCode",
649  "true",
650  "Dump MachineInstrs in the CodeEmitter"
651>;
652
653// XXX - This should probably be removed once enabled by default
654def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
655  "EnableLoadStoreOpt",
656  "true",
657  "Enable SI load/store optimizer pass"
658>;
659
660// Performance debugging feature. Allow using DS instruction immediate
661// offsets even if the base pointer can't be proven to be base. On SI,
662// base pointer values that won't give the same result as a 16-bit add
663// are not safe to fold, but this will override the conservative test
664// for the base pointer.
665def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
666  "unsafe-ds-offset-folding",
667  "EnableUnsafeDSOffsetFolding",
668  "true",
669  "Force using DS instruction immediate offsets on SI"
670>;
671
672def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
673  "EnableSIScheduler",
674  "true",
675  "Enable SI Machine Scheduler"
676>;
677
678def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
679  "EnableDS128",
680  "true",
681  "Use ds_{read|write}_b128"
682>;
683
684// Sparse texture support requires that all result registers are zeroed when
685// PRTStrictNull is set to true. This feature is turned on for all architectures
686// but is enabled as a feature in case there are situations where PRTStrictNull
687// is disabled by the driver.
688def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
689  "EnablePRTStrictNull",
690  "true",
691  "Enable zeroing of result registers for sparse texture fetches"
692>;
693
694// Unless +-flat-for-global is specified, turn on FlatForGlobal for
695// all OS-es on VI and newer hardware to avoid assertion failures due
696// to missing ADDR64 variants of MUBUF instructions.
697// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
698// instructions.
699
700def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
701  "FlatForGlobal",
702  "true",
703  "Force to generate flat instruction for global"
704>;
705
706def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
707  "auto-waitcnt-before-barrier",
708  "AutoWaitcntBeforeBarrier",
709  "true",
710  "Hardware automatically inserts waitcnt before barrier"
711>;
712
713def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
714  "HasTrigReducedRange",
715  "true",
716  "Requires use of fract on arguments to trig instructions"
717>;
718
719// Alignment enforcement is controlled by a configuration register:
720// SH_MEM_CONFIG.alignment_mode
721def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode",
722  "UnalignedAccessMode",
723  "true",
724  "Enable unaligned global, local and region loads and stores if the hardware"
725  " supports it"
726>;
727
728def FeaturePackedTID : SubtargetFeature<"packed-tid",
729  "HasPackedTID",
730  "true",
731  "Workitem IDs are packed into v0 at kernel launch"
732>;
733
734// Dummy feature used to disable assembler instructions.
735def FeatureDisable : SubtargetFeature<"",
736  "FeatureDisable","true",
737  "Dummy feature to disable assembler instructions"
738>;
739
740class GCNSubtargetFeatureGeneration <string Value,
741                                     string FeatureName,
742                                     list<SubtargetFeature> Implies> :
743        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
744
745def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
746    "southern-islands",
747  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
748  FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,
749  FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
750  FeatureTrigReducedRange, FeatureExtendedImageInsts
751  ]
752>;
753
754def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
755    "sea-islands",
756  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
757  FeatureWavefrontSize64, FeatureFlatAddressSpace,
758  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
759  FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
760  FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureUnalignedBufferAccess
761  ]
762>;
763
764def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
765  "volcanic-islands",
766  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
767   FeatureWavefrontSize64, FeatureFlatAddressSpace,
768   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
769   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
770   FeatureScalarStores, FeatureInv2PiInlineImm,
771   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
772   FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
773   FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
774   FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureFastDenormalF32,
775   FeatureUnalignedBufferAccess
776  ]
777>;
778
779def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
780  "gfx9",
781  [FeatureFP64, FeatureLocalMemorySize65536,
782   FeatureWavefrontSize64, FeatureFlatAddressSpace,
783   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
784   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
785   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
786   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
787   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
788   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
789   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
790   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
791   FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureSupportsXNACK,
792   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess,
793   FeatureNegativeScratchOffsetBug
794  ]
795>;
796
797def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
798  "gfx10",
799  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
800   FeatureFlatAddressSpace,
801   FeatureCIInsts, Feature16BitInsts,
802   FeatureSMemRealTime, FeatureInv2PiInlineImm,
803   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
804   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
805   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
806   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
807   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
808   FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
809   FeatureVOP3Literal, FeatureDPP8, FeatureExtendedImageInsts,
810   FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
811   FeatureGFX10A16, FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureG16,
812   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess
813  ]
814>;
815
816class FeatureSet<list<SubtargetFeature> Features_> {
817  list<SubtargetFeature> Features = Features_;
818}
819
820def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
821   FeatureFastFMAF32,
822   HalfRate64Ops,
823   FeatureLDSBankCount32]>;
824
825def FeatureISAVersion6_0_1 : FeatureSet<
826  [FeatureSouthernIslands,
827   FeatureLDSBankCount32]>;
828
829def FeatureISAVersion6_0_2 : FeatureSet<
830  [FeatureSouthernIslands,
831   FeatureLDSBankCount32]>;
832
833def FeatureISAVersion7_0_0 : FeatureSet<
834  [FeatureSeaIslands,
835   FeatureLDSBankCount32]>;
836
837def FeatureISAVersion7_0_1 : FeatureSet<
838  [FeatureSeaIslands,
839   HalfRate64Ops,
840   FeatureLDSBankCount32,
841   FeatureFastFMAF32]>;
842
843def FeatureISAVersion7_0_2 : FeatureSet<
844  [FeatureSeaIslands,
845   FeatureLDSBankCount16,
846   FeatureFastFMAF32]>;
847
848def FeatureISAVersion7_0_3 : FeatureSet<
849  [FeatureSeaIslands,
850   FeatureLDSBankCount16]>;
851
852def FeatureISAVersion7_0_4 : FeatureSet<
853  [FeatureSeaIslands,
854   FeatureLDSBankCount32]>;
855
856def FeatureISAVersion7_0_5 : FeatureSet<
857  [FeatureSeaIslands,
858   FeatureLDSBankCount16]>;
859
860def FeatureISAVersion8_0_1 : FeatureSet<
861  [FeatureVolcanicIslands,
862   FeatureFastFMAF32,
863   HalfRate64Ops,
864   FeatureLDSBankCount32,
865   FeatureSupportsXNACK,
866   FeatureUnpackedD16VMem]>;
867
868def FeatureISAVersion8_0_2 : FeatureSet<
869  [FeatureVolcanicIslands,
870   FeatureLDSBankCount32,
871   FeatureSGPRInitBug,
872   FeatureUnpackedD16VMem]>;
873
874def FeatureISAVersion8_0_3 : FeatureSet<
875  [FeatureVolcanicIslands,
876   FeatureLDSBankCount32,
877   FeatureUnpackedD16VMem]>;
878
879def FeatureISAVersion8_0_5 : FeatureSet<
880  [FeatureVolcanicIslands,
881   FeatureLDSBankCount32,
882   FeatureSGPRInitBug,
883   FeatureUnpackedD16VMem]>;
884
885def FeatureISAVersion8_1_0 : FeatureSet<
886  [FeatureVolcanicIslands,
887   FeatureLDSBankCount16,
888   FeatureSupportsXNACK,
889   FeatureImageStoreD16Bug,
890   FeatureImageGather4D16Bug]>;
891
892def FeatureISAVersion9_0_0 : FeatureSet<
893  [FeatureGFX9,
894   FeatureMadMixInsts,
895   FeatureLDSBankCount32,
896   FeatureDsSrc2Insts,
897   FeatureExtendedImageInsts,
898   FeatureMadMacF32Insts,
899   FeatureImageGather4D16Bug]>;
900
901def FeatureISAVersion9_0_2 : FeatureSet<
902  [FeatureGFX9,
903   FeatureMadMixInsts,
904   FeatureLDSBankCount32,
905   FeatureDsSrc2Insts,
906   FeatureExtendedImageInsts,
907   FeatureMadMacF32Insts,
908   FeatureImageGather4D16Bug]>;
909
910def FeatureISAVersion9_0_4 : FeatureSet<
911  [FeatureGFX9,
912   FeatureLDSBankCount32,
913   FeatureDsSrc2Insts,
914   FeatureExtendedImageInsts,
915   FeatureMadMacF32Insts,
916   FeatureFmaMixInsts,
917   FeatureImageGather4D16Bug]>;
918
919def FeatureISAVersion9_0_6 : FeatureSet<
920  [FeatureGFX9,
921   HalfRate64Ops,
922   FeatureFmaMixInsts,
923   FeatureLDSBankCount32,
924   FeatureDsSrc2Insts,
925   FeatureExtendedImageInsts,
926   FeatureMadMacF32Insts,
927   FeatureDLInsts,
928   FeatureDot1Insts,
929   FeatureDot2Insts,
930   FeatureDot7Insts,
931   FeatureSupportsSRAMECC,
932   FeatureImageGather4D16Bug]>;
933
934def FeatureISAVersion9_0_8 : FeatureSet<
935  [FeatureGFX9,
936   HalfRate64Ops,
937   FeatureFmaMixInsts,
938   FeatureLDSBankCount32,
939   FeatureDsSrc2Insts,
940   FeatureExtendedImageInsts,
941   FeatureMadMacF32Insts,
942   FeatureDLInsts,
943   FeatureDot1Insts,
944   FeatureDot2Insts,
945   FeatureDot3Insts,
946   FeatureDot4Insts,
947   FeatureDot5Insts,
948   FeatureDot6Insts,
949   FeatureDot7Insts,
950   FeatureMAIInsts,
951   FeaturePkFmacF16Inst,
952   FeatureAtomicFaddInsts,
953   FeatureSupportsSRAMECC,
954   FeatureMFMAInlineLiteralBug,
955   FeatureImageGather4D16Bug]>;
956
957def FeatureISAVersion9_0_9 : FeatureSet<
958  [FeatureGFX9,
959   FeatureMadMixInsts,
960   FeatureLDSBankCount32,
961   FeatureDsSrc2Insts,
962   FeatureExtendedImageInsts,
963   FeatureMadMacF32Insts,
964   FeatureImageGather4D16Bug]>;
965
966def FeatureISAVersion9_0_A : FeatureSet<
967  [FeatureGFX9,
968   FeatureGFX90AInsts,
969   FeatureFmaMixInsts,
970   FeatureLDSBankCount32,
971   FeatureDLInsts,
972   FeatureDot1Insts,
973   FeatureDot2Insts,
974   FeatureDot3Insts,
975   FeatureDot4Insts,
976   FeatureDot5Insts,
977   FeatureDot6Insts,
978   FeatureDot7Insts,
979   Feature64BitDPP,
980   FeaturePackedFP32Ops,
981   FeatureMAIInsts,
982   FeaturePkFmacF16Inst,
983   FeatureAtomicFaddInsts,
984   FeatureMadMacF32Insts,
985   FeatureSupportsSRAMECC,
986   FeaturePackedTID,
987   FullRate64Ops]>;
988
989def FeatureISAVersion9_0_C : FeatureSet<
990  [FeatureGFX9,
991   FeatureMadMixInsts,
992   FeatureLDSBankCount32,
993   FeatureDsSrc2Insts,
994   FeatureExtendedImageInsts,
995   FeatureMadMacF32Insts,
996   FeatureImageGather4D16Bug]>;
997
998// TODO: Organize more features into groups.
999def FeatureGroup {
1000  // Bugs present on gfx10.1.
1001  list<SubtargetFeature> GFX10_1_Bugs = [
1002    FeatureVcmpxPermlaneHazard,
1003    FeatureVMEMtoScalarWriteHazard,
1004    FeatureSMEMtoVectorWriteHazard,
1005    FeatureInstFwdPrefetchBug,
1006    FeatureVcmpxExecWARHazard,
1007    FeatureLdsBranchVmemWARHazard,
1008    FeatureNSAtoVMEMBug,
1009    FeatureNSAClauseBug,
1010    FeatureOffset3fBug,
1011    FeatureFlatSegmentOffsetBug,
1012    FeatureNegativeUnalignedScratchOffsetBug
1013   ];
1014}
1015
1016def FeatureISAVersion10_1_0 : FeatureSet<
1017  !listconcat(FeatureGroup.GFX10_1_Bugs,
1018    [FeatureGFX10,
1019     FeatureLDSBankCount32,
1020     FeatureDLInsts,
1021     FeatureNSAEncoding,
1022     FeatureWavefrontSize32,
1023     FeatureScalarStores,
1024     FeatureScalarAtomics,
1025     FeatureScalarFlatScratchInsts,
1026     FeatureGetWaveIdInst,
1027     FeatureMadMacF32Insts,
1028     FeatureDsSrc2Insts,
1029     FeatureLdsMisalignedBug,
1030     FeatureSupportsXNACK])>;
1031
1032def FeatureISAVersion10_1_1 : FeatureSet<
1033  !listconcat(FeatureGroup.GFX10_1_Bugs,
1034    [FeatureGFX10,
1035     FeatureLDSBankCount32,
1036     FeatureDLInsts,
1037     FeatureDot1Insts,
1038     FeatureDot2Insts,
1039     FeatureDot5Insts,
1040     FeatureDot6Insts,
1041     FeatureDot7Insts,
1042     FeatureNSAEncoding,
1043     FeatureWavefrontSize32,
1044     FeatureScalarStores,
1045     FeatureScalarAtomics,
1046     FeatureScalarFlatScratchInsts,
1047     FeatureGetWaveIdInst,
1048     FeatureMadMacF32Insts,
1049     FeatureDsSrc2Insts,
1050     FeatureLdsMisalignedBug,
1051     FeatureSupportsXNACK])>;
1052
1053def FeatureISAVersion10_1_2 : FeatureSet<
1054  !listconcat(FeatureGroup.GFX10_1_Bugs,
1055    [FeatureGFX10,
1056     FeatureLDSBankCount32,
1057     FeatureDLInsts,
1058     FeatureDot1Insts,
1059     FeatureDot2Insts,
1060     FeatureDot5Insts,
1061     FeatureDot6Insts,
1062     FeatureDot7Insts,
1063     FeatureNSAEncoding,
1064     FeatureWavefrontSize32,
1065     FeatureScalarStores,
1066     FeatureScalarAtomics,
1067     FeatureScalarFlatScratchInsts,
1068     FeatureGetWaveIdInst,
1069     FeatureMadMacF32Insts,
1070     FeatureDsSrc2Insts,
1071     FeatureLdsMisalignedBug,
1072     FeatureSupportsXNACK])>;
1073
1074def FeatureISAVersion10_3_0 : FeatureSet<
1075  [FeatureGFX10,
1076   FeatureGFX10_BEncoding,
1077   FeatureGFX10_3Insts,
1078   FeatureLDSBankCount32,
1079   FeatureDLInsts,
1080   FeatureDot1Insts,
1081   FeatureDot2Insts,
1082   FeatureDot5Insts,
1083   FeatureDot6Insts,
1084   FeatureDot7Insts,
1085   FeatureNSAEncoding,
1086   FeatureWavefrontSize32,
1087   FeatureShaderCyclesRegister]>;
1088
1089//===----------------------------------------------------------------------===//
1090
1091def AMDGPUInstrInfo : InstrInfo {
1092  let guessInstructionProperties = 1;
1093  let noNamedPositionallyEncodedOperands = 1;
1094}
1095
1096def AMDGPUAsmParser : AsmParser {
1097  // Some of the R600 registers have the same name, so this crashes.
1098  // For example T0_XYZW and T0_XY both have the asm name T0.
1099  let ShouldEmitMatchRegisterName = 0;
1100}
1101
1102def AMDGPUAsmWriter : AsmWriter {
1103  int PassSubtarget = 1;
1104}
1105
1106def AMDGPUAsmVariants {
1107  string Default = "Default";
1108  int Default_ID = 0;
1109  string VOP3 = "VOP3";
1110  int VOP3_ID = 1;
1111  string SDWA = "SDWA";
1112  int SDWA_ID = 2;
1113  string SDWA9 = "SDWA9";
1114  int SDWA9_ID = 3;
1115  string DPP = "DPP";
1116  int DPP_ID = 4;
1117  string Disable = "Disable";
1118  int Disable_ID = 5;
1119}
1120
1121def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
1122  let Variant = AMDGPUAsmVariants.Default_ID;
1123  let Name = AMDGPUAsmVariants.Default;
1124}
1125
1126def VOP3AsmParserVariant : AsmParserVariant {
1127  let Variant = AMDGPUAsmVariants.VOP3_ID;
1128  let Name = AMDGPUAsmVariants.VOP3;
1129}
1130
1131def SDWAAsmParserVariant : AsmParserVariant {
1132  let Variant = AMDGPUAsmVariants.SDWA_ID;
1133  let Name = AMDGPUAsmVariants.SDWA;
1134}
1135
1136def SDWA9AsmParserVariant : AsmParserVariant {
1137  let Variant = AMDGPUAsmVariants.SDWA9_ID;
1138  let Name = AMDGPUAsmVariants.SDWA9;
1139}
1140
1141
1142def DPPAsmParserVariant : AsmParserVariant {
1143  let Variant = AMDGPUAsmVariants.DPP_ID;
1144  let Name = AMDGPUAsmVariants.DPP;
1145}
1146
1147def AMDGPU : Target {
1148  // Pull in Instruction Info:
1149  let InstructionSet = AMDGPUInstrInfo;
1150  let AssemblyParsers = [AMDGPUAsmParser];
1151  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
1152                                VOP3AsmParserVariant,
1153                                SDWAAsmParserVariant,
1154                                SDWA9AsmParserVariant,
1155                                DPPAsmParserVariant];
1156  let AssemblyWriters = [AMDGPUAsmWriter];
1157  let AllowRegisterRenaming = 1;
1158}
1159
1160// Dummy Instruction itineraries for pseudo instructions
1161def ALU_NULL : FuncUnit;
1162def NullALU : InstrItinClass;
1163
1164//===----------------------------------------------------------------------===//
1165// Predicate helper class
1166//===----------------------------------------------------------------------===//
1167
1168def isGFX6 :
1169  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1170  AssemblerPredicate<(all_of FeatureSouthernIslands)>;
1171
1172def isGFX6GFX7 :
1173  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1174            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1175  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
1176
1177def isGFX6GFX7GFX10 :
1178  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1179            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1180            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1181  AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
1182
1183def isGFX7Only :
1184  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1185  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
1186
1187def isGFX7GFX10 :
1188  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1189            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1190  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
1191
1192def isGFX7GFX8GFX9 :
1193  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1194            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1195            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1196  AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
1197
1198def isGFX6GFX7GFX8GFX9 :
1199  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1200            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1201            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1202            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1203  AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
1204
1205def isGFX6GFX7GFX8GFX9NotGFX90A :
1206  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1207            "(Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1208            " Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1209            " Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1210            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1211  AssemblerPredicate<(all_of (not FeatureGFX10Insts), (not FeatureGFX90AInsts))>;
1212
1213def isGFX7Plus :
1214  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1215  AssemblerPredicate<(all_of FeatureCIInsts)>;
1216
1217def isGFX8Plus :
1218  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1219  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1220
1221def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1222                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1223  AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1224
1225def isGFX9Plus :
1226  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1227  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1228
1229def isGFX9Only : Predicate <
1230  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1231  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1232
1233def isGCN3ExcludingGFX90A :
1234  Predicate<"Subtarget->isGCN3Encoding() && !Subtarget->hasGFX90AInsts()">,
1235  AssemblerPredicate<(all_of FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1236
1237def isGFX90APlus :
1238  Predicate<"Subtarget->hasGFX90AInsts()">,
1239  AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1240
1241def isNotGFX90APlus :
1242  Predicate<"!Subtarget->hasGFX90AInsts()">,
1243  AssemblerPredicate<(all_of (not FeatureGFX90AInsts))>;
1244
1245def isGFX8GFX9NotGFX90A :
1246  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1247            "(Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1248            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1249  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1250
1251def isGFX90AOnly :
1252  Predicate<"Subtarget->hasGFX90AInsts()">,
1253  AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1254
1255def isGFX908orGFX90A :
1256  Predicate<"Subtarget->hasMAIInsts()">,
1257  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1258
1259def isGFX8GFX9 :
1260  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1261            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1262  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1263
1264def isGFX10Plus :
1265  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1266  AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1267
1268def isGFX10Before1030 :
1269  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 &&"
1270            "!Subtarget->hasGFX10_3Insts()">,
1271  AssemblerPredicate<(all_of FeatureGFX10Insts,(not FeatureGFX10_3Insts))>;
1272
1273def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1274  AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1275
1276def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1277  AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1278def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1279  AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1280def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1281  AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1282def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1283  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1284
1285def HasFlatScratchSTMode : Predicate<"Subtarget->hasFlatScratchSTMode()">,
1286  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1287
1288def HasGFX10_BEncoding : Predicate<"Subtarget->hasGFX10_BEncoding()">,
1289  AssemblerPredicate<(all_of FeatureGFX10_BEncoding)>;
1290
1291def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1292  AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1293def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1294  AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1295
1296def D16PreservesUnusedBits :
1297  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1298  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1299
1300def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1301def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1302
1303def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1304  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1305
1306def HasLDSFPAtomics : Predicate<"Subtarget->hasLDSFPAtomics()">,
1307  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1308
1309def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1310  AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1311
1312def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1313
1314def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1315  AssemblerPredicate<(all_of Feature16BitInsts)>;
1316def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1317  AssemblerPredicate<(all_of FeatureVOP3P)>;
1318
1319def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
1320def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
1321
1322def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1323  AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1324
1325def HasSDWA9 :
1326  Predicate<"Subtarget->hasSDWA()">,
1327  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1328
1329def HasSDWA10 :
1330  Predicate<"Subtarget->hasSDWA()">,
1331  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1332
1333def HasDPP : Predicate<"Subtarget->hasDPP()">,
1334  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1335
1336def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1337  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1338
1339def Has64BitDPP : Predicate<"Subtarget->has64BitDPP()">,
1340  AssemblerPredicate<(all_of Feature64BitDPP)>;
1341
1342def HasPackedFP32Ops : Predicate<"Subtarget->hasPackedFP32Ops()">,
1343  AssemblerPredicate<(all_of FeaturePackedFP32Ops)>;
1344
1345def HasFmaakFmamkF32Insts :
1346  Predicate<"Subtarget->hasFmaakFmamkF32Insts()">,
1347  AssemblerPredicate<(any_of FeatureGFX10Insts)>;
1348
1349def HasExtendedImageInsts : Predicate<"Subtarget->hasExtendedImageInsts()">,
1350  AssemblerPredicate<(all_of FeatureExtendedImageInsts)>;
1351
1352def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1353  AssemblerPredicate<(all_of FeatureR128A16)>;
1354
1355def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1356  AssemblerPredicate<(all_of FeatureGFX10A16)>;
1357
1358def HasG16 : Predicate<"Subtarget->hasG16()">,
1359  AssemblerPredicate<(all_of FeatureG16)>;
1360
1361def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1362  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1363
1364def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1365  AssemblerPredicate<(all_of FeatureIntClamp)>;
1366
1367def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1368  AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1369
1370def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1371  AssemblerPredicate<(all_of FeatureScalarStores)>;
1372
1373def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1374  AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1375
1376def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1377  AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1378
1379def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1380  AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1381
1382def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1383def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1384def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1385                      AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1386def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1387                AssemblerPredicate<(all_of FeatureMovrel)>;
1388
1389def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1390  AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1391
1392def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1393  AssemblerPredicate<(all_of FeatureDLInsts)>;
1394
1395def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1396  AssemblerPredicate<(all_of FeatureDot1Insts)>;
1397
1398def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1399  AssemblerPredicate<(all_of FeatureDot2Insts)>;
1400
1401def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1402  AssemblerPredicate<(all_of FeatureDot3Insts)>;
1403
1404def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1405  AssemblerPredicate<(all_of FeatureDot4Insts)>;
1406
1407def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1408  AssemblerPredicate<(all_of FeatureDot5Insts)>;
1409
1410def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1411  AssemblerPredicate<(all_of FeatureDot6Insts)>;
1412
1413def HasDot7Insts : Predicate<"Subtarget->hasDot7Insts()">,
1414  AssemblerPredicate<(all_of FeatureDot7Insts)>;
1415
1416def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">,
1417  AssemblerPredicate<(all_of FeatureGetWaveIdInst)>;
1418
1419def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1420  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1421
1422def HasSMemRealTime : Predicate<"Subtarget->hasSMemRealTime()">,
1423  AssemblerPredicate<(all_of FeatureSMemRealTime)>;
1424
1425def HasSMemTimeInst : Predicate<"Subtarget->hasSMemTimeInst()">,
1426  AssemblerPredicate<(all_of FeatureSMemTimeInst)>;
1427
1428def HasShaderCyclesRegister : Predicate<"Subtarget->hasShaderCyclesRegister()">,
1429  AssemblerPredicate<(all_of FeatureShaderCyclesRegister)>;
1430
1431def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1432  AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1433
1434def HasMadMacF32Insts : Predicate<"Subtarget->hasMadMacF32Insts()">,
1435  AssemblerPredicate<(all_of FeatureMadMacF32Insts)>;
1436
1437def HasFmaLegacy32 : Predicate<"Subtarget->hasGFX10_3Insts()">,
1438  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1439
1440def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1441  AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>;
1442
1443def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
1444  AssemblerPredicate<(all_of FeatureDsSrc2Insts)>;
1445
1446def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">,
1447  AssemblerPredicate<(all_of FeatureOffset3fBug)>;
1448
1449def EnableLateCFGStructurize : Predicate<
1450  "EnableLateStructurizeCFG">;
1451
1452def EnableFlatScratch : Predicate<"Subtarget->enableFlatScratch()">;
1453
1454def DisableFlatScratch : Predicate<"!Subtarget->enableFlatScratch()">;
1455
1456def HasUnalignedAccessMode : Predicate<"Subtarget->hasUnalignedAccessMode()">,
1457  AssemblerPredicate<(all_of FeatureUnalignedAccessMode)>;
1458
1459// Include AMDGPU TD files
1460include "SISchedule.td"
1461include "GCNProcessors.td"
1462include "AMDGPUInstrInfo.td"
1463include "SIRegisterInfo.td"
1464include "AMDGPURegisterBanks.td"
1465include "AMDGPUInstructions.td"
1466include "SIInstrInfo.td"
1467include "AMDGPUCallingConv.td"
1468include "AMDGPUSearchableTables.td"
1469