1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===------------------------------------------------------------===//
9
10include "llvm/TableGen/SearchableTable.td"
11include "llvm/Target/Target.td"
12include "AMDGPUFeatures.td"
13
14//===------------------------------------------------------------===//
15// Subtarget Features (device properties)
16//===------------------------------------------------------------===//
17
18def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
19  "FastFMAF32",
20  "true",
21  "Assuming f32 fma is at least as fast as mul + add"
22>;
23
24def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
25  "MIMG_R128",
26  "true",
27  "Support 128-bit texture resources"
28>;
29
30def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
31  "HalfRate64Ops",
32  "true",
33  "Most fp64 instructions are half rate instead of quarter"
34>;
35
36def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
37  "FlatAddressSpace",
38  "true",
39  "Support flat address space"
40>;
41
42def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
43  "FlatInstOffsets",
44  "true",
45  "Flat instructions have immediate offset addressing mode"
46>;
47
48def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
49  "FlatGlobalInsts",
50  "true",
51  "Have global_* flat memory instructions"
52>;
53
54def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
55  "FlatScratchInsts",
56  "true",
57  "Have scratch_* flat memory instructions"
58>;
59
60def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
61  "AddNoCarryInsts",
62  "true",
63  "Have VALU add/sub instructions without carry out"
64>;
65
66def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
67  "UnalignedBufferAccess",
68  "true",
69  "Support unaligned global loads and stores"
70>;
71
72def FeatureTrapHandler: SubtargetFeature<"trap-handler",
73  "TrapHandler",
74  "true",
75  "Trap handler support"
76>;
77
78def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
79  "UnalignedScratchAccess",
80  "true",
81  "Support unaligned scratch loads and stores"
82>;
83
84def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
85  "HasApertureRegs",
86  "true",
87  "Has Memory Aperture Base and Size Registers"
88>;
89
90def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
91  "HasMadMixInsts",
92  "true",
93  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
94>;
95
96def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
97  "HasFmaMixInsts",
98  "true",
99  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
100>;
101
102// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
103// XNACK. The current default kernel driver setting is:
104// - graphics ring: XNACK disabled
105// - compute ring: XNACK enabled
106//
107// If XNACK is enabled, the VMEM latency can be worse.
108// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
109def FeatureXNACK : SubtargetFeature<"xnack",
110  "EnableXNACK",
111  "true",
112  "Enable XNACK support"
113>;
114
115def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
116  "SGPRInitBug",
117  "true",
118  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
119>;
120
121class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
122  "ldsbankcount"#Value,
123  "LDSBankCount",
124  !cast<string>(Value),
125  "The number of LDS banks per compute unit."
126>;
127
128def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
129def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
130
131def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
132  "GCN3Encoding",
133  "true",
134  "Encoding format for VI"
135>;
136
137def FeatureCIInsts : SubtargetFeature<"ci-insts",
138  "CIInsts",
139  "true",
140  "Additional instructions for CI+"
141>;
142
143def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
144  "GFX9Insts",
145  "true",
146  "Additional instructions for GFX9+"
147>;
148
149def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
150  "HasSMemRealTime",
151  "true",
152  "Has s_memrealtime instruction"
153>;
154
155def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
156  "HasInv2PiInlineImm",
157  "true",
158  "Has 1 / (2 * pi) as inline immediate"
159>;
160
161def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
162  "Has16BitInsts",
163  "true",
164  "Has i16/f16 instructions"
165>;
166
167def FeatureVOP3P : SubtargetFeature<"vop3p",
168  "HasVOP3PInsts",
169  "true",
170  "Has VOP3P packed instructions"
171>;
172
173def FeatureMovrel : SubtargetFeature<"movrel",
174  "HasMovrel",
175  "true",
176  "Has v_movrel*_b32 instructions"
177>;
178
179def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
180  "HasVGPRIndexMode",
181  "true",
182  "Has VGPR mode register indexing"
183>;
184
185def FeatureScalarStores : SubtargetFeature<"scalar-stores",
186  "HasScalarStores",
187  "true",
188  "Has store scalar memory instructions"
189>;
190
191def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
192  "HasScalarAtomics",
193  "true",
194  "Has atomic scalar memory instructions"
195>;
196
197def FeatureSDWA : SubtargetFeature<"sdwa",
198  "HasSDWA",
199  "true",
200  "Support SDWA (Sub-DWORD Addressing) extension"
201>;
202
203def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
204  "HasSDWAOmod",
205  "true",
206  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
207>;
208
209def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
210  "HasSDWAScalar",
211  "true",
212  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
213>;
214
215def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
216  "HasSDWASdst",
217  "true",
218  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
219>;
220
221def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
222  "HasSDWAMac",
223  "true",
224  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
225>;
226
227def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
228  "HasSDWAOutModsVOPC",
229  "true",
230  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
231>;
232
233def FeatureDPP : SubtargetFeature<"dpp",
234  "HasDPP",
235  "true",
236  "Support DPP (Data Parallel Primitives) extension"
237>;
238
239def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
240  "HasIntClamp",
241  "true",
242  "Support clamp for integer destination"
243>;
244
245def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
246  "HasUnpackedD16VMem",
247  "true",
248  "Has unpacked d16 vmem instructions"
249>;
250
251def FeatureDLInsts : SubtargetFeature<"dl-insts",
252  "HasDLInsts",
253  "true",
254  "Has deep learning instructions"
255>;
256
257def FeatureD16PreservesUnusedBits : SubtargetFeature<
258  "d16-preserves-unused-bits",
259  "D16PreservesUnusedBits",
260  "true",
261  "If present, then instructions defined by HasD16LoadStore predicate preserve "
262  "unused bits. Otherwise instructions defined by HasD16LoadStore predicate "
263  "zero unused bits."
264>;
265
266//===------------------------------------------------------------===//
267// Subtarget Features (options and debugging)
268//===------------------------------------------------------------===//
269
270// Some instructions do not support denormals despite this flag. Using
271// fp32 denormals also causes instructions to run at the double
272// precision rate for the device.
273def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
274  "FP32Denormals",
275  "true",
276  "Enable single precision denormal handling"
277>;
278
279// Denormal handling for fp64 and fp16 is controlled by the same
280// config register when fp16 supported.
281// TODO: Do we need a separate f16 setting when not legal?
282def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
283  "FP64FP16Denormals",
284  "true",
285  "Enable double and half precision denormal handling",
286  [FeatureFP64]
287>;
288
289def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
290  "FP64FP16Denormals",
291  "true",
292  "Enable double and half precision denormal handling",
293  [FeatureFP64, FeatureFP64FP16Denormals]
294>;
295
296def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
297  "FP64FP16Denormals",
298  "true",
299  "Enable half precision denormal handling",
300  [FeatureFP64FP16Denormals]
301>;
302
303def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
304  "FPExceptions",
305  "true",
306  "Enable floating point exceptions"
307>;
308
309class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
310  "max-private-element-size-"#size,
311  "MaxPrivateElementSize",
312  !cast<string>(size),
313  "Maximum private access size may be "#size
314>;
315
316def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
317def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
318def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
319
320def FeatureEnableHugePrivateBuffer : SubtargetFeature<
321  "huge-private-buffer",
322  "EnableHugePrivateBuffer",
323  "true",
324  "Enable private/scratch buffer sizes greater than 128 GB"
325>;
326
327def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
328  "EnableVGPRSpilling",
329  "true",
330  "Enable spilling of VGPRs to scratch memory"
331>;
332
333def FeatureDumpCode : SubtargetFeature <"DumpCode",
334  "DumpCode",
335  "true",
336  "Dump MachineInstrs in the CodeEmitter"
337>;
338
339def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
340  "DumpCode",
341  "true",
342  "Dump MachineInstrs in the CodeEmitter"
343>;
344
345// XXX - This should probably be removed once enabled by default
346def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
347  "EnableLoadStoreOpt",
348  "true",
349  "Enable SI load/store optimizer pass"
350>;
351
352// Performance debugging feature. Allow using DS instruction immediate
353// offsets even if the base pointer can't be proven to be base. On SI,
354// base pointer values that won't give the same result as a 16-bit add
355// are not safe to fold, but this will override the conservative test
356// for the base pointer.
357def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
358  "unsafe-ds-offset-folding",
359  "EnableUnsafeDSOffsetFolding",
360  "true",
361  "Force using DS instruction immediate offsets on SI"
362>;
363
364def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
365  "EnableSIScheduler",
366  "true",
367  "Enable SI Machine Scheduler"
368>;
369
370def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
371  "EnableDS128",
372  "true",
373  "Use ds_{read|write}_b128"
374>;
375
376// Unless +-flat-for-global is specified, turn on FlatForGlobal for
377// all OS-es on VI and newer hardware to avoid assertion failures due
378// to missing ADDR64 variants of MUBUF instructions.
379// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
380// instructions.
381
382def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
383  "FlatForGlobal",
384  "true",
385  "Force to generate flat instruction for global"
386>;
387
388def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
389  "auto-waitcnt-before-barrier",
390  "AutoWaitcntBeforeBarrier",
391  "true",
392  "Hardware automatically inserts waitcnt before barrier"
393>;
394
395def FeatureCodeObjectV3 : SubtargetFeature <
396  "code-object-v3",
397  "CodeObjectV3",
398  "true",
399  "Generate code object version 3"
400>;
401
402// Dummy feature used to disable assembler instructions.
403def FeatureDisable : SubtargetFeature<"",
404  "FeatureDisable","true",
405  "Dummy feature to disable assembler instructions"
406>;
407
408def FeatureGCN : SubtargetFeature<"gcn",
409  "IsGCN",
410  "true",
411  "GCN or newer GPU"
412>;
413
414class GCNSubtargetFeatureGeneration <string Value,
415                                  list<SubtargetFeature> Implies> :
416        SubtargetFeatureGeneration <Value, "GCNSubtarget", Implies>;
417
418def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
419  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
420  FeatureWavefrontSize64, FeatureGCN,
421  FeatureLDSBankCount32, FeatureMovrel]
422>;
423
424def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
425  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
426  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
427  FeatureCIInsts, FeatureMovrel]
428>;
429
430def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
431  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
432   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
433   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
434   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
435   FeatureScalarStores, FeatureInv2PiInlineImm,
436   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
437   FeatureIntClamp
438  ]
439>;
440
441def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
442  [FeatureFP64, FeatureLocalMemorySize65536,
443   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
444   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
445   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
446   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
447   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
448   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
449   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
450   FeatureAddNoCarryInsts, FeatureScalarAtomics
451  ]
452>;
453
454class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
455                                  list<SubtargetFeature> Implies>
456                                 : SubtargetFeature <
457  "isaver"#Major#"."#Minor#"."#Stepping,
458  "IsaVersion",
459  "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
460  "Instruction set version number",
461  Implies
462>;
463
464def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
465  [FeatureSouthernIslands,
466   FeatureFastFMAF32,
467   HalfRate64Ops,
468   FeatureLDSBankCount32]>;
469
470def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
471  [FeatureSouthernIslands,
472   FeatureLDSBankCount32]>;
473
474def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
475  [FeatureSeaIslands,
476   FeatureLDSBankCount32]>;
477
478def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
479  [FeatureSeaIslands,
480   HalfRate64Ops,
481   FeatureLDSBankCount32,
482   FeatureFastFMAF32]>;
483
484def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
485  [FeatureSeaIslands,
486   FeatureLDSBankCount16,
487   FeatureFastFMAF32]>;
488
489def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
490  [FeatureSeaIslands,
491   FeatureLDSBankCount16]>;
492
493def FeatureISAVersion7_0_4 : SubtargetFeatureISAVersion <7,0,4,
494  [FeatureSeaIslands,
495   FeatureLDSBankCount32]>;
496
497def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
498  [FeatureVolcanicIslands,
499   FeatureFastFMAF32,
500   HalfRate64Ops,
501   FeatureLDSBankCount32,
502   FeatureXNACK,
503   FeatureUnpackedD16VMem]>;
504
505def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
506  [FeatureVolcanicIslands,
507   FeatureLDSBankCount32,
508   FeatureSGPRInitBug,
509   FeatureUnpackedD16VMem]>;
510
511def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
512  [FeatureVolcanicIslands,
513   FeatureLDSBankCount32,
514   FeatureUnpackedD16VMem]>;
515
516def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
517  [FeatureVolcanicIslands,
518   FeatureLDSBankCount16,
519   FeatureXNACK]>;
520
521def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
522  [FeatureGFX9,
523   FeatureMadMixInsts,
524   FeatureLDSBankCount32,
525   FeatureD16PreservesUnusedBits]>;
526
527def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
528  [FeatureGFX9,
529   FeatureMadMixInsts,
530   FeatureLDSBankCount32,
531   FeatureXNACK,
532   FeatureD16PreservesUnusedBits]>;
533
534def FeatureISAVersion9_0_4 : SubtargetFeatureISAVersion <9,0,4,
535  [FeatureGFX9,
536   FeatureLDSBankCount32,
537   FeatureFmaMixInsts,
538   FeatureD16PreservesUnusedBits]>;
539
540def FeatureISAVersion9_0_6 : SubtargetFeatureISAVersion <9,0,6,
541  [FeatureGFX9,
542   HalfRate64Ops,
543   FeatureFmaMixInsts,
544   FeatureLDSBankCount32,
545   FeatureDLInsts]>;
546
547//===----------------------------------------------------------------------===//
548// Debugger related subtarget features.
549//===----------------------------------------------------------------------===//
550
551def FeatureDebuggerInsertNops : SubtargetFeature<
552  "amdgpu-debugger-insert-nops",
553  "DebuggerInsertNops",
554  "true",
555  "Insert one nop instruction for each high level source statement"
556>;
557
558def FeatureDebuggerEmitPrologue : SubtargetFeature<
559  "amdgpu-debugger-emit-prologue",
560  "DebuggerEmitPrologue",
561  "true",
562  "Emit debugger prologue"
563>;
564
565//===----------------------------------------------------------------------===//
566
567def AMDGPUInstrInfo : InstrInfo {
568  let guessInstructionProperties = 1;
569  let noNamedPositionallyEncodedOperands = 1;
570}
571
572def AMDGPUAsmParser : AsmParser {
573  // Some of the R600 registers have the same name, so this crashes.
574  // For example T0_XYZW and T0_XY both have the asm name T0.
575  let ShouldEmitMatchRegisterName = 0;
576}
577
578def AMDGPUAsmWriter : AsmWriter {
579  int PassSubtarget = 1;
580}
581
582def AMDGPUAsmVariants {
583  string Default = "Default";
584  int Default_ID = 0;
585  string VOP3 = "VOP3";
586  int VOP3_ID = 1;
587  string SDWA = "SDWA";
588  int SDWA_ID = 2;
589  string SDWA9 = "SDWA9";
590  int SDWA9_ID = 3;
591  string DPP = "DPP";
592  int DPP_ID = 4;
593  string Disable = "Disable";
594  int Disable_ID = 5;
595}
596
597def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
598  let Variant = AMDGPUAsmVariants.Default_ID;
599  let Name = AMDGPUAsmVariants.Default;
600}
601
602def VOP3AsmParserVariant : AsmParserVariant {
603  let Variant = AMDGPUAsmVariants.VOP3_ID;
604  let Name = AMDGPUAsmVariants.VOP3;
605}
606
607def SDWAAsmParserVariant : AsmParserVariant {
608  let Variant = AMDGPUAsmVariants.SDWA_ID;
609  let Name = AMDGPUAsmVariants.SDWA;
610}
611
612def SDWA9AsmParserVariant : AsmParserVariant {
613  let Variant = AMDGPUAsmVariants.SDWA9_ID;
614  let Name = AMDGPUAsmVariants.SDWA9;
615}
616
617
618def DPPAsmParserVariant : AsmParserVariant {
619  let Variant = AMDGPUAsmVariants.DPP_ID;
620  let Name = AMDGPUAsmVariants.DPP;
621}
622
623def AMDGPU : Target {
624  // Pull in Instruction Info:
625  let InstructionSet = AMDGPUInstrInfo;
626  let AssemblyParsers = [AMDGPUAsmParser];
627  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
628                                VOP3AsmParserVariant,
629                                SDWAAsmParserVariant,
630                                SDWA9AsmParserVariant,
631                                DPPAsmParserVariant];
632  let AssemblyWriters = [AMDGPUAsmWriter];
633  let AllowRegisterRenaming = 1;
634}
635
636// Dummy Instruction itineraries for pseudo instructions
637def ALU_NULL : FuncUnit;
638def NullALU : InstrItinClass;
639
640//===----------------------------------------------------------------------===//
641// Predicate helper class
642//===----------------------------------------------------------------------===//
643
644def isSICI : Predicate<
645  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
646  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
647>, AssemblerPredicate<"!FeatureGCN3Encoding">;
648
649def isVI : Predicate <
650  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
651  AssemblerPredicate<"FeatureGCN3Encoding">;
652
653def isGFX9 : Predicate <
654  "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
655  AssemblerPredicate<"FeatureGFX9Insts">;
656
657// TODO: Either the name to be changed or we simply use IsCI!
658def isCIVI : Predicate <
659  "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
660  AssemblerPredicate<"FeatureCIInsts">;
661
662def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
663  AssemblerPredicate<"FeatureFlatAddressSpace">;
664
665def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
666  AssemblerPredicate<"FeatureFlatGlobalInsts">;
667def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
668  AssemblerPredicate<"FeatureFlatScratchInsts">;
669def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
670  AssemblerPredicate<"FeatureGFX9Insts">;
671
672def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
673  AssemblerPredicate<"FeatureUnpackedD16VMem">;
674def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
675  AssemblerPredicate<"!FeatureUnpackedD16VMem">;
676
677def D16PreservesUnusedBits : Predicate<"Subtarget->d16PreservesUnusedBits()">,
678  AssemblerPredicate<"FeatureD16PreservesUnusedBits">;
679
680def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
681def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
682
683def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
684  AssemblerPredicate<"FeatureGFX9Insts">;
685
686def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarryInsts()">,
687  AssemblerPredicate<"FeatureAddNoCarryInsts">;
688
689def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarryInsts()">,
690  AssemblerPredicate<"!FeatureAddNoCarryInsts">;
691
692def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
693  AssemblerPredicate<"Feature16BitInsts">;
694def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
695  AssemblerPredicate<"FeatureVOP3P">;
696
697def NotHasVOP3PInsts : Predicate<"!Subtarget->hasVOP3PInsts()">,
698  AssemblerPredicate<"!FeatureVOP3P">;
699
700def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
701  AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
702
703def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
704  AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
705
706def HasDPP : Predicate<"Subtarget->hasDPP()">,
707  AssemblerPredicate<"FeatureDPP">;
708
709def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
710  AssemblerPredicate<"FeatureIntClamp">;
711
712def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
713  AssemblerPredicate<"FeatureMadMixInsts">;
714
715def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
716  AssemblerPredicate<"FeatureScalarAtomics">;
717
718def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
719def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
720def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
721                      AssemblerPredicate<"FeatureVGPRIndexMode">;
722def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
723                AssemblerPredicate<"FeatureMovrel">;
724
725def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
726  AssemblerPredicate<"FeatureFmaMixInsts">;
727
728def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
729  AssemblerPredicate<"FeatureDLInsts">;
730
731
732def EnableLateCFGStructurize : Predicate<
733  "EnableLateStructurizeCFG">;
734
735// Include AMDGPU TD files
736include "SISchedule.td"
737include "GCNProcessors.td"
738include "AMDGPUInstrInfo.td"
739include "AMDGPUIntrinsics.td"
740include "SIIntrinsics.td"
741include "AMDGPURegisterInfo.td"
742include "AMDGPURegisterBanks.td"
743include "AMDGPUInstructions.td"
744include "SIInstrInfo.td"
745include "AMDGPUCallingConv.td"
746include "AMDGPUSearchableTables.td"
747