1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21
22class BoolToList<bit Value> {
23  list<int> ret = !if(Value, [1]<int>, []<int>);
24}
25
26//===------------------------------------------------------------===//
27// Subtarget Features (device properties)
28//===------------------------------------------------------------===//
29
30def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
31  "FastFMAF32",
32  "true",
33  "Assuming f32 fma is at least as fast as mul + add"
34>;
35
36def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
37  "FastDenormalF32",
38  "true",
39  "Enabling denormals does not cause f32 instructions to run at f64 rates"
40>;
41
42def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
43  "MIMG_R128",
44  "true",
45  "Support 128-bit texture resources"
46>;
47
48def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
49  "HalfRate64Ops",
50  "true",
51  "Most fp64 instructions are half rate instead of quarter"
52>;
53
54def FullRate64Ops : SubtargetFeature<"full-rate-64-ops",
55  "FullRate64Ops",
56  "true",
57  "Most fp64 instructions are full rate"
58>;
59
60def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
61  "FlatAddressSpace",
62  "true",
63  "Support flat address space"
64>;
65
66def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
67  "FlatInstOffsets",
68  "true",
69  "Flat instructions have immediate offset addressing mode"
70>;
71
72def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
73  "FlatGlobalInsts",
74  "true",
75  "Have global_* flat memory instructions"
76>;
77
78def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
79  "FlatScratchInsts",
80  "true",
81  "Have scratch_* flat memory instructions"
82>;
83
84def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
85  "ScalarFlatScratchInsts",
86  "true",
87  "Have s_scratch_* flat memory instructions"
88>;
89
90def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
91  "AddNoCarryInsts",
92  "true",
93  "Have VALU add/sub instructions without carry out"
94>;
95
96def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
97  "UnalignedBufferAccess",
98  "true",
99  "Hardware supports unaligned global loads and stores"
100>;
101
102def FeatureTrapHandler: SubtargetFeature<"trap-handler",
103  "TrapHandler",
104  "true",
105  "Trap handler support"
106>;
107
108def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
109  "UnalignedScratchAccess",
110  "true",
111  "Support unaligned scratch loads and stores"
112>;
113
114def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access",
115  "UnalignedDSAccess",
116  "true",
117  "Hardware supports unaligned local and region loads and stores"
118>;
119
120def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
121  "HasApertureRegs",
122  "true",
123  "Has Memory Aperture Base and Size Registers"
124>;
125
126def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
127  "HasMadMixInsts",
128  "true",
129  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
130>;
131
132def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
133  "HasFmaMixInsts",
134  "true",
135  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
136>;
137
138def FeatureSupportsXNACK : SubtargetFeature<"xnack-support",
139  "SupportsXNACK",
140  "true",
141  "Hardware supports XNACK"
142>;
143
144// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
145// XNACK. The current default kernel driver setting is:
146// - graphics ring: XNACK disabled
147// - compute ring: XNACK enabled
148//
149// If XNACK is enabled, the VMEM latency can be worse.
150// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
151def FeatureXNACK : SubtargetFeature<"xnack",
152  "EnableXNACK",
153  "true",
154  "Enable XNACK support"
155>;
156
157def FeatureTgSplit : SubtargetFeature<"tgsplit",
158  "EnableTgSplit",
159  "true",
160  "Enable threadgroup split execution"
161>;
162
163def FeatureCuMode : SubtargetFeature<"cumode",
164  "EnableCuMode",
165  "true",
166  "Enable CU wavefront execution mode"
167>;
168
169def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
170  "SGPRInitBug",
171  "true",
172  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
173>;
174
175def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
176  "LDSMisalignedBug",
177  "true",
178  "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode"
179>;
180
181def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
182  "HasMFMAInlineLiteralBug",
183  "true",
184  "MFMA cannot use inline literal as SrcC"
185>;
186
187def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
188  "HasVcmpxPermlaneHazard",
189  "true",
190  "TODO: describe me"
191>;
192
193def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
194  "HasVMEMtoScalarWriteHazard",
195  "true",
196  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
197>;
198
199def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
200  "HasSMEMtoVectorWriteHazard",
201  "true",
202  "s_load_dword followed by v_cmp page faults"
203>;
204
205def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
206  "HasInstFwdPrefetchBug",
207  "true",
208  "S_INST_PREFETCH instruction causes shader to hang"
209>;
210
211def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
212  "HasVcmpxExecWARHazard",
213  "true",
214  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
215>;
216
217def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
218  "HasLdsBranchVmemWARHazard",
219  "true",
220  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
221>;
222
223def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
224  "HasNSAtoVMEMBug",
225  "true",
226  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
227>;
228
229def FeatureNSAClauseBug : SubtargetFeature<"nsa-clause-bug",
230  "HasNSAClauseBug",
231  "true",
232  "MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
233>;
234
235def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
236  "HasFlatSegmentOffsetBug",
237  "true",
238  "GFX10 bug where inst_offset is ignored when flat instructions access global memory"
239>;
240
241def FeatureNegativeScratchOffsetBug : SubtargetFeature<"negative-scratch-offset-bug",
242  "NegativeScratchOffsetBug",
243  "true",
244  "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9"
245>;
246
247def FeatureNegativeUnalignedScratchOffsetBug : SubtargetFeature<"negative-unaligned-scratch-offset-bug",
248  "NegativeUnalignedScratchOffsetBug",
249  "true",
250  "Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10"
251>;
252
253def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
254  "HasOffset3fBug",
255  "true",
256  "Branch offset of 3f hardware bug"
257>;
258
259def FeatureImageStoreD16Bug : SubtargetFeature<"image-store-d16-bug",
260  "HasImageStoreD16Bug",
261  "true",
262  "Image Store D16 hardware bug"
263>;
264
265def FeatureImageGather4D16Bug : SubtargetFeature<"image-gather4-d16-bug",
266  "HasImageGather4D16Bug",
267  "true",
268  "Image Gather4 D16 hardware bug"
269>;
270
271class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
272  "ldsbankcount"#Value,
273  "LDSBankCount",
274  !cast<string>(Value),
275  "The number of LDS banks per compute unit."
276>;
277
278def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
279def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
280
281def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
282  "GCN3Encoding",
283  "true",
284  "Encoding format for VI"
285>;
286
287def FeatureCIInsts : SubtargetFeature<"ci-insts",
288  "CIInsts",
289  "true",
290  "Additional instructions for CI+"
291>;
292
293def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
294  "GFX8Insts",
295  "true",
296  "Additional instructions for GFX8+"
297>;
298
299def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
300  "GFX9Insts",
301  "true",
302  "Additional instructions for GFX9+"
303>;
304
305def FeatureGFX90AInsts : SubtargetFeature<"gfx90a-insts",
306  "GFX90AInsts",
307  "true",
308  "Additional instructions for GFX90A+"
309>;
310
311def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
312  "GFX10Insts",
313  "true",
314  "Additional instructions for GFX10+"
315>;
316
317def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts",
318  "GFX10_3Insts",
319  "true",
320  "Additional instructions for GFX10.3"
321>;
322
323def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
324  "GFX7GFX8GFX9Insts",
325  "true",
326  "Instructions shared in GFX7, GFX8, GFX9"
327>;
328
329def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
330  "HasSMemRealTime",
331  "true",
332  "Has s_memrealtime instruction"
333>;
334
335def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
336  "HasInv2PiInlineImm",
337  "true",
338  "Has 1 / (2 * pi) as inline immediate"
339>;
340
341def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
342  "Has16BitInsts",
343  "true",
344  "Has i16/f16 instructions"
345>;
346
347def FeatureVOP3P : SubtargetFeature<"vop3p",
348  "HasVOP3PInsts",
349  "true",
350  "Has VOP3P packed instructions"
351>;
352
353def FeatureMovrel : SubtargetFeature<"movrel",
354  "HasMovrel",
355  "true",
356  "Has v_movrel*_b32 instructions"
357>;
358
359def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
360  "HasVGPRIndexMode",
361  "true",
362  "Has VGPR mode register indexing"
363>;
364
365def FeatureScalarStores : SubtargetFeature<"scalar-stores",
366  "HasScalarStores",
367  "true",
368  "Has store scalar memory instructions"
369>;
370
371def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
372  "HasScalarAtomics",
373  "true",
374  "Has atomic scalar memory instructions"
375>;
376
377def FeatureSDWA : SubtargetFeature<"sdwa",
378  "HasSDWA",
379  "true",
380  "Support SDWA (Sub-DWORD Addressing) extension"
381>;
382
383def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
384  "HasSDWAOmod",
385  "true",
386  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
387>;
388
389def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
390  "HasSDWAScalar",
391  "true",
392  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
393>;
394
395def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
396  "HasSDWASdst",
397  "true",
398  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
399>;
400
401def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
402  "HasSDWAMac",
403  "true",
404  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
405>;
406
407def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
408  "HasSDWAOutModsVOPC",
409  "true",
410  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
411>;
412
413def FeatureDPP : SubtargetFeature<"dpp",
414  "HasDPP",
415  "true",
416  "Support DPP (Data Parallel Primitives) extension"
417>;
418
419// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
420def FeatureDPP8 : SubtargetFeature<"dpp8",
421  "HasDPP8",
422  "true",
423  "Support DPP8 (Data Parallel Primitives) extension"
424>;
425
426def Feature64BitDPP : SubtargetFeature<"dpp-64bit",
427  "Has64BitDPP",
428  "true",
429  "Support DPP (Data Parallel Primitives) extension"
430>;
431
432def FeaturePackedFP32Ops : SubtargetFeature<"packed-fp32-ops",
433  "HasPackedFP32Ops",
434  "true",
435  "Support packed fp32 instructions"
436>;
437
438def FeatureR128A16 : SubtargetFeature<"r128-a16",
439  "HasR128A16",
440  "true",
441  "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
442>;
443
444def FeatureGFX10A16 : SubtargetFeature<"a16",
445  "HasGFX10A16",
446  "true",
447  "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
448>;
449
450def FeatureG16 : SubtargetFeature<"g16",
451  "HasG16",
452  "true",
453  "Support G16 for 16-bit gradient image operands"
454>;
455
456def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
457  "HasNSAEncoding",
458  "true",
459  "Support NSA encoding for image instructions"
460>;
461
462def FeatureExtendedImageInsts : SubtargetFeature<"extended-image-insts",
463  "HasExtendedImageInsts",
464  "true",
465  "Support mips != 0, lod != 0, gather4, and get_lod"
466>;
467
468def FeatureGFX10_AEncoding : SubtargetFeature<"gfx10_a-encoding",
469  "GFX10_AEncoding",
470  "true",
471  "Has BVH ray tracing instructions"
472>;
473
474def FeatureGFX10_BEncoding : SubtargetFeature<"gfx10_b-encoding",
475  "GFX10_BEncoding",
476  "true",
477  "Encoding format GFX10_B"
478>;
479
480def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
481  "HasIntClamp",
482  "true",
483  "Support clamp for integer destination"
484>;
485
486def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
487  "HasUnpackedD16VMem",
488  "true",
489  "Has unpacked d16 vmem instructions"
490>;
491
492def FeatureDLInsts : SubtargetFeature<"dl-insts",
493  "HasDLInsts",
494  "true",
495  "Has v_fmac_f32 and v_xnor_b32 instructions"
496>;
497
498def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
499  "HasDot1Insts",
500  "true",
501  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
502>;
503
504def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
505  "HasDot2Insts",
506  "true",
507  "Has v_dot2_i32_i16, v_dot2_u32_u16 instructions"
508>;
509
510def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
511  "HasDot3Insts",
512  "true",
513  "Has v_dot8c_i32_i4 instruction"
514>;
515
516def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
517  "HasDot4Insts",
518  "true",
519  "Has v_dot2c_i32_i16 instruction"
520>;
521
522def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
523  "HasDot5Insts",
524  "true",
525  "Has v_dot2c_f32_f16 instruction"
526>;
527
528def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
529  "HasDot6Insts",
530  "true",
531  "Has v_dot4c_i32_i8 instruction"
532>;
533
534def FeatureDot7Insts : SubtargetFeature<"dot7-insts",
535  "HasDot7Insts",
536  "true",
537  "Has v_dot2_f32_f16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
538>;
539
540def FeatureMAIInsts : SubtargetFeature<"mai-insts",
541  "HasMAIInsts",
542  "true",
543  "Has mAI instructions"
544>;
545
546def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
547  "HasPkFmacF16Inst",
548  "true",
549  "Has v_pk_fmac_f16 instruction"
550>;
551
552def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
553  "HasAtomicFaddInsts",
554  "true",
555  "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
556  "global_atomic_pk_add_f16 instructions",
557  [FeatureFlatGlobalInsts]
558>;
559
560def FeatureSupportsSRAMECC : SubtargetFeature<"sramecc-support",
561  "SupportsSRAMECC",
562  "true",
563  "Hardware supports SRAMECC"
564>;
565
566def FeatureSRAMECC : SubtargetFeature<"sramecc",
567  "EnableSRAMECC",
568  "true",
569  "Enable SRAMECC"
570>;
571
572def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
573  "HasNoSdstCMPX",
574  "true",
575  "V_CMPX does not write VCC/SGPR in addition to EXEC"
576>;
577
578def FeatureVscnt : SubtargetFeature<"vscnt",
579  "HasVscnt",
580  "true",
581  "Has separate store vscnt counter"
582>;
583
584def FeatureGetWaveIdInst : SubtargetFeature<"get-wave-id-inst",
585  "HasGetWaveIdInst",
586  "true",
587  "Has s_get_waveid_in_workgroup instruction"
588>;
589
590def FeatureSMemTimeInst : SubtargetFeature<"s-memtime-inst",
591  "HasSMemTimeInst",
592  "true",
593  "Has s_memtime instruction"
594>;
595
596def FeatureShaderCyclesRegister : SubtargetFeature<"shader-cycles-register",
597  "HasShaderCyclesRegister",
598  "true",
599  "Has SHADER_CYCLES hardware register"
600>;
601
602def FeatureMadMacF32Insts : SubtargetFeature<"mad-mac-f32-insts",
603  "HasMadMacF32Insts",
604  "true",
605  "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions"
606>;
607
608def FeatureDsSrc2Insts : SubtargetFeature<"ds-src2-insts",
609  "HasDsSrc2Insts",
610  "true",
611  "Has ds_*_src2 instructions"
612>;
613
614def FeatureRegisterBanking : SubtargetFeature<"register-banking",
615  "HasRegisterBanking",
616  "true",
617  "Has register banking"
618>;
619
620def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
621  "HasVOP3Literal",
622  "true",
623  "Can use one literal in VOP3"
624>;
625
626def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
627  "HasNoDataDepHazard",
628  "true",
629  "Does not need SW waitstates"
630>;
631
632//===------------------------------------------------------------===//
633// Subtarget Features (options and debugging)
634//===------------------------------------------------------------===//
635
636class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
637  "max-private-element-size-"#size,
638  "MaxPrivateElementSize",
639  !cast<string>(size),
640  "Maximum private access size may be "#size
641>;
642
643def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
644def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
645def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
646
647def FeatureDumpCode : SubtargetFeature <"DumpCode",
648  "DumpCode",
649  "true",
650  "Dump MachineInstrs in the CodeEmitter"
651>;
652
653def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
654  "DumpCode",
655  "true",
656  "Dump MachineInstrs in the CodeEmitter"
657>;
658
659// XXX - This should probably be removed once enabled by default
660def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
661  "EnableLoadStoreOpt",
662  "true",
663  "Enable SI load/store optimizer pass"
664>;
665
666// Performance debugging feature. Allow using DS instruction immediate
667// offsets even if the base pointer can't be proven to be base. On SI,
668// base pointer values that won't give the same result as a 16-bit add
669// are not safe to fold, but this will override the conservative test
670// for the base pointer.
671def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
672  "unsafe-ds-offset-folding",
673  "EnableUnsafeDSOffsetFolding",
674  "true",
675  "Force using DS instruction immediate offsets on SI"
676>;
677
678def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
679  "EnableSIScheduler",
680  "true",
681  "Enable SI Machine Scheduler"
682>;
683
684def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
685  "EnableDS128",
686  "true",
687  "Use ds_{read|write}_b128"
688>;
689
690// Sparse texture support requires that all result registers are zeroed when
691// PRTStrictNull is set to true. This feature is turned on for all architectures
692// but is enabled as a feature in case there are situations where PRTStrictNull
693// is disabled by the driver.
694def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
695  "EnablePRTStrictNull",
696  "true",
697  "Enable zeroing of result registers for sparse texture fetches"
698>;
699
700// Unless +-flat-for-global is specified, turn on FlatForGlobal for
701// all OS-es on VI and newer hardware to avoid assertion failures due
702// to missing ADDR64 variants of MUBUF instructions.
703// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
704// instructions.
705
706def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
707  "FlatForGlobal",
708  "true",
709  "Force to generate flat instruction for global"
710>;
711
712def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
713  "auto-waitcnt-before-barrier",
714  "AutoWaitcntBeforeBarrier",
715  "true",
716  "Hardware automatically inserts waitcnt before barrier"
717>;
718
719def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
720  "HasTrigReducedRange",
721  "true",
722  "Requires use of fract on arguments to trig instructions"
723>;
724
725// Alignment enforcement is controlled by a configuration register:
726// SH_MEM_CONFIG.alignment_mode
727def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode",
728  "UnalignedAccessMode",
729  "true",
730  "Enable unaligned global, local and region loads and stores if the hardware"
731  " supports it"
732>;
733
734def FeaturePackedTID : SubtargetFeature<"packed-tid",
735  "HasPackedTID",
736  "true",
737  "Workitem IDs are packed into v0 at kernel launch"
738>;
739
740def FeatureArchitectedFlatScratch : SubtargetFeature<"architected-flat-scratch",
741  "HasArchitectedFlatScratch",
742  "true",
743  "Flat Scratch register is a readonly SPI initialized architected register"
744>;
745
746// Dummy feature used to disable assembler instructions.
747def FeatureDisable : SubtargetFeature<"",
748  "FeatureDisable","true",
749  "Dummy feature to disable assembler instructions"
750>;
751
752class GCNSubtargetFeatureGeneration <string Value,
753                                     string FeatureName,
754                                     list<SubtargetFeature> Implies> :
755        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
756
757def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
758    "southern-islands",
759  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
760  FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,
761  FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
762  FeatureTrigReducedRange, FeatureExtendedImageInsts
763  ]
764>;
765
766def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
767    "sea-islands",
768  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
769  FeatureWavefrontSize64, FeatureFlatAddressSpace,
770  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
771  FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
772  FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureUnalignedBufferAccess
773  ]
774>;
775
776def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
777  "volcanic-islands",
778  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
779   FeatureWavefrontSize64, FeatureFlatAddressSpace,
780   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
781   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
782   FeatureScalarStores, FeatureInv2PiInlineImm,
783   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
784   FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
785   FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
786   FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureFastDenormalF32,
787   FeatureUnalignedBufferAccess
788  ]
789>;
790
791def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
792  "gfx9",
793  [FeatureFP64, FeatureLocalMemorySize65536,
794   FeatureWavefrontSize64, FeatureFlatAddressSpace,
795   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
796   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
797   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
798   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
799   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
800   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
801   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
802   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
803   FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureSupportsXNACK,
804   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess,
805   FeatureNegativeScratchOffsetBug
806  ]
807>;
808
809def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
810  "gfx10",
811  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
812   FeatureFlatAddressSpace,
813   FeatureCIInsts, Feature16BitInsts,
814   FeatureSMemRealTime, FeatureInv2PiInlineImm,
815   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
816   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
817   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
818   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
819   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
820   FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
821   FeatureVOP3Literal, FeatureDPP8, FeatureExtendedImageInsts,
822   FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
823   FeatureGFX10A16, FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureG16,
824   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess
825  ]
826>;
827
828class FeatureSet<list<SubtargetFeature> Features_> {
829  list<SubtargetFeature> Features = Features_;
830}
831
832def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
833   FeatureFastFMAF32,
834   HalfRate64Ops,
835   FeatureLDSBankCount32]>;
836
837def FeatureISAVersion6_0_1 : FeatureSet<
838  [FeatureSouthernIslands,
839   FeatureLDSBankCount32]>;
840
841def FeatureISAVersion6_0_2 : FeatureSet<
842  [FeatureSouthernIslands,
843   FeatureLDSBankCount32]>;
844
845def FeatureISAVersion7_0_0 : FeatureSet<
846  [FeatureSeaIslands,
847   FeatureLDSBankCount32]>;
848
849def FeatureISAVersion7_0_1 : FeatureSet<
850  [FeatureSeaIslands,
851   HalfRate64Ops,
852   FeatureLDSBankCount32,
853   FeatureFastFMAF32]>;
854
855def FeatureISAVersion7_0_2 : FeatureSet<
856  [FeatureSeaIslands,
857   FeatureLDSBankCount16,
858   FeatureFastFMAF32]>;
859
860def FeatureISAVersion7_0_3 : FeatureSet<
861  [FeatureSeaIslands,
862   FeatureLDSBankCount16]>;
863
864def FeatureISAVersion7_0_4 : FeatureSet<
865  [FeatureSeaIslands,
866   FeatureLDSBankCount32]>;
867
868def FeatureISAVersion7_0_5 : FeatureSet<
869  [FeatureSeaIslands,
870   FeatureLDSBankCount16]>;
871
872def FeatureISAVersion8_0_1 : FeatureSet<
873  [FeatureVolcanicIslands,
874   FeatureFastFMAF32,
875   HalfRate64Ops,
876   FeatureLDSBankCount32,
877   FeatureSupportsXNACK,
878   FeatureUnpackedD16VMem]>;
879
880def FeatureISAVersion8_0_2 : FeatureSet<
881  [FeatureVolcanicIslands,
882   FeatureLDSBankCount32,
883   FeatureSGPRInitBug,
884   FeatureUnpackedD16VMem]>;
885
886def FeatureISAVersion8_0_3 : FeatureSet<
887  [FeatureVolcanicIslands,
888   FeatureLDSBankCount32,
889   FeatureUnpackedD16VMem]>;
890
891def FeatureISAVersion8_0_5 : FeatureSet<
892  [FeatureVolcanicIslands,
893   FeatureLDSBankCount32,
894   FeatureSGPRInitBug,
895   FeatureUnpackedD16VMem]>;
896
897def FeatureISAVersion8_1_0 : FeatureSet<
898  [FeatureVolcanicIslands,
899   FeatureLDSBankCount16,
900   FeatureSupportsXNACK,
901   FeatureImageStoreD16Bug,
902   FeatureImageGather4D16Bug]>;
903
904def FeatureISAVersion9_0_0 : FeatureSet<
905  [FeatureGFX9,
906   FeatureMadMixInsts,
907   FeatureLDSBankCount32,
908   FeatureDsSrc2Insts,
909   FeatureExtendedImageInsts,
910   FeatureMadMacF32Insts,
911   FeatureImageGather4D16Bug]>;
912
913def FeatureISAVersion9_0_2 : FeatureSet<
914  [FeatureGFX9,
915   FeatureMadMixInsts,
916   FeatureLDSBankCount32,
917   FeatureDsSrc2Insts,
918   FeatureExtendedImageInsts,
919   FeatureMadMacF32Insts,
920   FeatureImageGather4D16Bug]>;
921
922def FeatureISAVersion9_0_4 : FeatureSet<
923  [FeatureGFX9,
924   FeatureLDSBankCount32,
925   FeatureDsSrc2Insts,
926   FeatureExtendedImageInsts,
927   FeatureMadMacF32Insts,
928   FeatureFmaMixInsts,
929   FeatureImageGather4D16Bug]>;
930
931def FeatureISAVersion9_0_6 : FeatureSet<
932  [FeatureGFX9,
933   HalfRate64Ops,
934   FeatureFmaMixInsts,
935   FeatureLDSBankCount32,
936   FeatureDsSrc2Insts,
937   FeatureExtendedImageInsts,
938   FeatureMadMacF32Insts,
939   FeatureDLInsts,
940   FeatureDot1Insts,
941   FeatureDot2Insts,
942   FeatureDot7Insts,
943   FeatureSupportsSRAMECC,
944   FeatureImageGather4D16Bug]>;
945
946def FeatureISAVersion9_0_8 : FeatureSet<
947  [FeatureGFX9,
948   HalfRate64Ops,
949   FeatureFmaMixInsts,
950   FeatureLDSBankCount32,
951   FeatureDsSrc2Insts,
952   FeatureExtendedImageInsts,
953   FeatureMadMacF32Insts,
954   FeatureDLInsts,
955   FeatureDot1Insts,
956   FeatureDot2Insts,
957   FeatureDot3Insts,
958   FeatureDot4Insts,
959   FeatureDot5Insts,
960   FeatureDot6Insts,
961   FeatureDot7Insts,
962   FeatureMAIInsts,
963   FeaturePkFmacF16Inst,
964   FeatureAtomicFaddInsts,
965   FeatureSupportsSRAMECC,
966   FeatureMFMAInlineLiteralBug,
967   FeatureImageGather4D16Bug]>;
968
969def FeatureISAVersion9_0_9 : FeatureSet<
970  [FeatureGFX9,
971   FeatureMadMixInsts,
972   FeatureLDSBankCount32,
973   FeatureDsSrc2Insts,
974   FeatureExtendedImageInsts,
975   FeatureMadMacF32Insts,
976   FeatureImageGather4D16Bug]>;
977
978def FeatureISAVersion9_0_A : FeatureSet<
979  [FeatureGFX9,
980   FeatureGFX90AInsts,
981   FeatureFmaMixInsts,
982   FeatureLDSBankCount32,
983   FeatureDLInsts,
984   FeatureDot1Insts,
985   FeatureDot2Insts,
986   FeatureDot3Insts,
987   FeatureDot4Insts,
988   FeatureDot5Insts,
989   FeatureDot6Insts,
990   FeatureDot7Insts,
991   Feature64BitDPP,
992   FeaturePackedFP32Ops,
993   FeatureMAIInsts,
994   FeaturePkFmacF16Inst,
995   FeatureAtomicFaddInsts,
996   FeatureMadMacF32Insts,
997   FeatureSupportsSRAMECC,
998   FeaturePackedTID,
999   FullRate64Ops]>;
1000
1001def FeatureISAVersion9_0_C : FeatureSet<
1002  [FeatureGFX9,
1003   FeatureMadMixInsts,
1004   FeatureLDSBankCount32,
1005   FeatureDsSrc2Insts,
1006   FeatureExtendedImageInsts,
1007   FeatureMadMacF32Insts,
1008   FeatureImageGather4D16Bug]>;
1009
1010// TODO: Organize more features into groups.
1011def FeatureGroup {
1012  // Bugs present on gfx10.1.
1013  list<SubtargetFeature> GFX10_1_Bugs = [
1014    FeatureVcmpxPermlaneHazard,
1015    FeatureVMEMtoScalarWriteHazard,
1016    FeatureSMEMtoVectorWriteHazard,
1017    FeatureInstFwdPrefetchBug,
1018    FeatureVcmpxExecWARHazard,
1019    FeatureLdsBranchVmemWARHazard,
1020    FeatureNSAtoVMEMBug,
1021    FeatureNSAClauseBug,
1022    FeatureOffset3fBug,
1023    FeatureFlatSegmentOffsetBug,
1024    FeatureNegativeUnalignedScratchOffsetBug
1025   ];
1026}
1027
1028def FeatureISAVersion10_1_0 : FeatureSet<
1029  !listconcat(FeatureGroup.GFX10_1_Bugs,
1030    [FeatureGFX10,
1031     FeatureLDSBankCount32,
1032     FeatureDLInsts,
1033     FeatureNSAEncoding,
1034     FeatureWavefrontSize32,
1035     FeatureScalarStores,
1036     FeatureScalarAtomics,
1037     FeatureScalarFlatScratchInsts,
1038     FeatureGetWaveIdInst,
1039     FeatureMadMacF32Insts,
1040     FeatureDsSrc2Insts,
1041     FeatureLdsMisalignedBug,
1042     FeatureSupportsXNACK])>;
1043
1044def FeatureISAVersion10_1_1 : FeatureSet<
1045  !listconcat(FeatureGroup.GFX10_1_Bugs,
1046    [FeatureGFX10,
1047     FeatureLDSBankCount32,
1048     FeatureDLInsts,
1049     FeatureDot1Insts,
1050     FeatureDot2Insts,
1051     FeatureDot5Insts,
1052     FeatureDot6Insts,
1053     FeatureDot7Insts,
1054     FeatureNSAEncoding,
1055     FeatureWavefrontSize32,
1056     FeatureScalarStores,
1057     FeatureScalarAtomics,
1058     FeatureScalarFlatScratchInsts,
1059     FeatureGetWaveIdInst,
1060     FeatureMadMacF32Insts,
1061     FeatureDsSrc2Insts,
1062     FeatureLdsMisalignedBug,
1063     FeatureSupportsXNACK])>;
1064
1065def FeatureISAVersion10_1_2 : FeatureSet<
1066  !listconcat(FeatureGroup.GFX10_1_Bugs,
1067    [FeatureGFX10,
1068     FeatureLDSBankCount32,
1069     FeatureDLInsts,
1070     FeatureDot1Insts,
1071     FeatureDot2Insts,
1072     FeatureDot5Insts,
1073     FeatureDot6Insts,
1074     FeatureDot7Insts,
1075     FeatureNSAEncoding,
1076     FeatureWavefrontSize32,
1077     FeatureScalarStores,
1078     FeatureScalarAtomics,
1079     FeatureScalarFlatScratchInsts,
1080     FeatureGetWaveIdInst,
1081     FeatureMadMacF32Insts,
1082     FeatureDsSrc2Insts,
1083     FeatureLdsMisalignedBug,
1084     FeatureSupportsXNACK])>;
1085
1086def FeatureISAVersion10_1_3 : FeatureSet<
1087  !listconcat(FeatureGroup.GFX10_1_Bugs,
1088    [FeatureGFX10,
1089     FeatureGFX10_AEncoding,
1090     FeatureLDSBankCount32,
1091     FeatureDLInsts,
1092     FeatureNSAEncoding,
1093     FeatureWavefrontSize32,
1094     FeatureScalarStores,
1095     FeatureScalarAtomics,
1096     FeatureScalarFlatScratchInsts,
1097     FeatureGetWaveIdInst,
1098     FeatureMadMacF32Insts,
1099     FeatureDsSrc2Insts,
1100     FeatureLdsMisalignedBug,
1101     FeatureSupportsXNACK])>;
1102
1103def FeatureISAVersion10_3_0 : FeatureSet<
1104  [FeatureGFX10,
1105   FeatureGFX10_AEncoding,
1106   FeatureGFX10_BEncoding,
1107   FeatureGFX10_3Insts,
1108   FeatureLDSBankCount32,
1109   FeatureDLInsts,
1110   FeatureDot1Insts,
1111   FeatureDot2Insts,
1112   FeatureDot5Insts,
1113   FeatureDot6Insts,
1114   FeatureDot7Insts,
1115   FeatureNSAEncoding,
1116   FeatureWavefrontSize32,
1117   FeatureShaderCyclesRegister]>;
1118
1119//===----------------------------------------------------------------------===//
1120
1121def AMDGPUInstrInfo : InstrInfo {
1122  let guessInstructionProperties = 1;
1123  let noNamedPositionallyEncodedOperands = 1;
1124}
1125
1126def AMDGPUAsmParser : AsmParser {
1127  // Some of the R600 registers have the same name, so this crashes.
1128  // For example T0_XYZW and T0_XY both have the asm name T0.
1129  let ShouldEmitMatchRegisterName = 0;
1130}
1131
1132def AMDGPUAsmWriter : AsmWriter {
1133  int PassSubtarget = 1;
1134}
1135
1136def AMDGPUAsmVariants {
1137  string Default = "Default";
1138  int Default_ID = 0;
1139  string VOP3 = "VOP3";
1140  int VOP3_ID = 1;
1141  string SDWA = "SDWA";
1142  int SDWA_ID = 2;
1143  string SDWA9 = "SDWA9";
1144  int SDWA9_ID = 3;
1145  string DPP = "DPP";
1146  int DPP_ID = 4;
1147  string Disable = "Disable";
1148  int Disable_ID = 5;
1149}
1150
1151def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
1152  let Variant = AMDGPUAsmVariants.Default_ID;
1153  let Name = AMDGPUAsmVariants.Default;
1154}
1155
1156def VOP3AsmParserVariant : AsmParserVariant {
1157  let Variant = AMDGPUAsmVariants.VOP3_ID;
1158  let Name = AMDGPUAsmVariants.VOP3;
1159}
1160
1161def SDWAAsmParserVariant : AsmParserVariant {
1162  let Variant = AMDGPUAsmVariants.SDWA_ID;
1163  let Name = AMDGPUAsmVariants.SDWA;
1164}
1165
1166def SDWA9AsmParserVariant : AsmParserVariant {
1167  let Variant = AMDGPUAsmVariants.SDWA9_ID;
1168  let Name = AMDGPUAsmVariants.SDWA9;
1169}
1170
1171
1172def DPPAsmParserVariant : AsmParserVariant {
1173  let Variant = AMDGPUAsmVariants.DPP_ID;
1174  let Name = AMDGPUAsmVariants.DPP;
1175}
1176
1177def AMDGPU : Target {
1178  // Pull in Instruction Info:
1179  let InstructionSet = AMDGPUInstrInfo;
1180  let AssemblyParsers = [AMDGPUAsmParser];
1181  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
1182                                VOP3AsmParserVariant,
1183                                SDWAAsmParserVariant,
1184                                SDWA9AsmParserVariant,
1185                                DPPAsmParserVariant];
1186  let AssemblyWriters = [AMDGPUAsmWriter];
1187  let AllowRegisterRenaming = 1;
1188}
1189
1190// Dummy Instruction itineraries for pseudo instructions
1191def ALU_NULL : FuncUnit;
1192def NullALU : InstrItinClass;
1193
1194//===----------------------------------------------------------------------===//
1195// Predicate helper class
1196//===----------------------------------------------------------------------===//
1197
1198def isGFX6 :
1199  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1200  AssemblerPredicate<(all_of FeatureSouthernIslands)>;
1201
1202def isGFX6GFX7 :
1203  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1204            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1205  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
1206
1207def isGFX6GFX7GFX10 :
1208  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1209            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1210            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1211  AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
1212
1213def isGFX7Only :
1214  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1215  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
1216
1217def isGFX7GFX10 :
1218  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1219            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1220  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
1221
1222def isGFX7GFX8GFX9 :
1223  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1224            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1225            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1226  AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
1227
1228def isGFX6GFX7GFX8GFX9 :
1229  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1230            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1231            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1232            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1233  AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
1234
1235def isGFX6GFX7GFX8GFX9NotGFX90A :
1236  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1237            "(Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1238            " Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1239            " Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1240            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1241  AssemblerPredicate<(all_of (not FeatureGFX10Insts), (not FeatureGFX90AInsts))>;
1242
1243def isGFX7Plus :
1244  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1245  AssemblerPredicate<(all_of FeatureCIInsts)>;
1246
1247def isGFX8Plus :
1248  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1249  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1250
1251def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1252                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1253  AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1254
1255def isGFX9Plus :
1256  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1257  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1258
1259def isGFX9Only : Predicate <
1260  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1261  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1262
1263def isGCN3ExcludingGFX90A :
1264  Predicate<"Subtarget->isGCN3Encoding() && !Subtarget->hasGFX90AInsts()">,
1265  AssemblerPredicate<(all_of FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1266
1267def isGFX90APlus :
1268  Predicate<"Subtarget->hasGFX90AInsts()">,
1269  AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1270
1271def isNotGFX90APlus :
1272  Predicate<"!Subtarget->hasGFX90AInsts()">,
1273  AssemblerPredicate<(all_of (not FeatureGFX90AInsts))>;
1274
1275def isGFX8GFX9NotGFX90A :
1276  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1277            "(Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1278            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1279  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1280
1281def isGFX90AOnly :
1282  Predicate<"Subtarget->hasGFX90AInsts()">,
1283  AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1284
1285def isGFX908orGFX90A :
1286  Predicate<"Subtarget->hasMAIInsts()">,
1287  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1288
1289def isGFX8GFX9 :
1290  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1291            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1292  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1293
1294def isGFX10Plus :
1295  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1296  AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1297
1298def isGFX10Before1030 :
1299  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 &&"
1300            "!Subtarget->hasGFX10_3Insts()">,
1301  AssemblerPredicate<(all_of FeatureGFX10Insts,(not FeatureGFX10_3Insts))>;
1302
1303def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1304  AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1305
1306def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1307  AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1308def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1309  AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1310def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1311  AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1312def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1313  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1314
1315def HasFlatScratchSTMode : Predicate<"Subtarget->hasFlatScratchSTMode()">,
1316  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1317
1318def HasGFX10_AEncoding : Predicate<"Subtarget->hasGFX10_AEncoding()">,
1319  AssemblerPredicate<(all_of FeatureGFX10_AEncoding)>;
1320
1321def HasGFX10_BEncoding : Predicate<"Subtarget->hasGFX10_BEncoding()">,
1322  AssemblerPredicate<(all_of FeatureGFX10_BEncoding)>;
1323
1324def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1325  AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1326def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1327  AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1328
1329def D16PreservesUnusedBits :
1330  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1331  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1332
1333def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1334def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1335
1336def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1337  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1338
1339def HasLDSFPAtomics : Predicate<"Subtarget->hasLDSFPAtomics()">,
1340  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1341
1342def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1343  AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1344
1345def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1346
1347def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1348  AssemblerPredicate<(all_of Feature16BitInsts)>;
1349def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1350  AssemblerPredicate<(all_of FeatureVOP3P)>;
1351
1352def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
1353def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
1354
1355def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1356  AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1357
1358def HasSDWA9 :
1359  Predicate<"Subtarget->hasSDWA()">,
1360  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1361
1362def HasSDWA10 :
1363  Predicate<"Subtarget->hasSDWA()">,
1364  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1365
1366def HasDPP : Predicate<"Subtarget->hasDPP()">,
1367  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1368
1369def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1370  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1371
1372def Has64BitDPP : Predicate<"Subtarget->has64BitDPP()">,
1373  AssemblerPredicate<(all_of Feature64BitDPP)>;
1374
1375def HasPackedFP32Ops : Predicate<"Subtarget->hasPackedFP32Ops()">,
1376  AssemblerPredicate<(all_of FeaturePackedFP32Ops)>;
1377
1378def HasFmaakFmamkF32Insts :
1379  Predicate<"Subtarget->hasFmaakFmamkF32Insts()">,
1380  AssemblerPredicate<(any_of FeatureGFX10Insts)>;
1381
1382def HasExtendedImageInsts : Predicate<"Subtarget->hasExtendedImageInsts()">,
1383  AssemblerPredicate<(all_of FeatureExtendedImageInsts)>;
1384
1385def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1386  AssemblerPredicate<(all_of FeatureR128A16)>;
1387
1388def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1389  AssemblerPredicate<(all_of FeatureGFX10A16)>;
1390
1391def HasG16 : Predicate<"Subtarget->hasG16()">,
1392  AssemblerPredicate<(all_of FeatureG16)>;
1393
1394def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1395  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1396
1397def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1398  AssemblerPredicate<(all_of FeatureIntClamp)>;
1399
1400def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1401  AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1402
1403def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1404  AssemblerPredicate<(all_of FeatureScalarStores)>;
1405
1406def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1407  AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1408
1409def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1410  AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1411
1412def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1413  AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1414
1415def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1416def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1417def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1418                      AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1419def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1420                AssemblerPredicate<(all_of FeatureMovrel)>;
1421
1422def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1423  AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1424
1425def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1426  AssemblerPredicate<(all_of FeatureDLInsts)>;
1427
1428def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1429  AssemblerPredicate<(all_of FeatureDot1Insts)>;
1430
1431def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1432  AssemblerPredicate<(all_of FeatureDot2Insts)>;
1433
1434def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1435  AssemblerPredicate<(all_of FeatureDot3Insts)>;
1436
1437def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1438  AssemblerPredicate<(all_of FeatureDot4Insts)>;
1439
1440def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1441  AssemblerPredicate<(all_of FeatureDot5Insts)>;
1442
1443def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1444  AssemblerPredicate<(all_of FeatureDot6Insts)>;
1445
1446def HasDot7Insts : Predicate<"Subtarget->hasDot7Insts()">,
1447  AssemblerPredicate<(all_of FeatureDot7Insts)>;
1448
1449def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">,
1450  AssemblerPredicate<(all_of FeatureGetWaveIdInst)>;
1451
1452def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1453  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1454
1455def HasSMemRealTime : Predicate<"Subtarget->hasSMemRealTime()">,
1456  AssemblerPredicate<(all_of FeatureSMemRealTime)>;
1457
1458def HasSMemTimeInst : Predicate<"Subtarget->hasSMemTimeInst()">,
1459  AssemblerPredicate<(all_of FeatureSMemTimeInst)>;
1460
1461def HasShaderCyclesRegister : Predicate<"Subtarget->hasShaderCyclesRegister()">,
1462  AssemblerPredicate<(all_of FeatureShaderCyclesRegister)>;
1463
1464def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1465  AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1466
1467def HasMadMacF32Insts : Predicate<"Subtarget->hasMadMacF32Insts()">,
1468  AssemblerPredicate<(all_of FeatureMadMacF32Insts)>;
1469
1470def HasFmaLegacy32 : Predicate<"Subtarget->hasGFX10_3Insts()">,
1471  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1472
1473def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1474  AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>;
1475
1476def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
1477  AssemblerPredicate<(all_of FeatureDsSrc2Insts)>;
1478
1479def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">,
1480  AssemblerPredicate<(all_of FeatureOffset3fBug)>;
1481
1482def EnableLateCFGStructurize : Predicate<
1483  "EnableLateStructurizeCFG">;
1484
1485def EnableFlatScratch : Predicate<"Subtarget->enableFlatScratch()">;
1486
1487def DisableFlatScratch : Predicate<"!Subtarget->enableFlatScratch()">;
1488
1489def HasUnalignedAccessMode : Predicate<"Subtarget->hasUnalignedAccessMode()">,
1490  AssemblerPredicate<(all_of FeatureUnalignedAccessMode)>;
1491
1492// Include AMDGPU TD files
1493include "SISchedule.td"
1494include "GCNProcessors.td"
1495include "AMDGPUInstrInfo.td"
1496include "SIRegisterInfo.td"
1497include "AMDGPURegisterBanks.td"
1498include "AMDGPUInstructions.td"
1499include "SIInstrInfo.td"
1500include "AMDGPUCallingConv.td"
1501include "AMDGPUSearchableTables.td"
1502