1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===------------------------------------------------------------===//
9
10include "llvm/Target/Target.td"
11
12//===------------------------------------------------------------===//
13// Subtarget Features (device properties)
14//===------------------------------------------------------------===//
15
16def FeatureFP64 : SubtargetFeature<"fp64",
17  "FP64",
18  "true",
19  "Enable double precision operations"
20>;
21
22def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
23  "FastFMAF32",
24  "true",
25  "Assuming f32 fma is at least as fast as mul + add"
26>;
27
28def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
29  "HalfRate64Ops",
30  "true",
31  "Most fp64 instructions are half rate instead of quarter"
32>;
33
34def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
35  "R600ALUInst",
36  "false",
37  "Older version of ALU instructions encoding"
38>;
39
40def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
41  "HasVertexCache",
42  "true",
43  "Specify use of dedicated vertex cache"
44>;
45
46def FeatureCaymanISA : SubtargetFeature<"caymanISA",
47  "CaymanISA",
48  "true",
49  "Use Cayman ISA"
50>;
51
52def FeatureCFALUBug : SubtargetFeature<"cfalubug",
53  "CFALUBug",
54  "true",
55  "GPU has CF_ALU bug"
56>;
57
58def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
59  "FlatAddressSpace",
60  "true",
61  "Support flat address space"
62>;
63
64def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
65  "UnalignedBufferAccess",
66  "true",
67  "Support unaligned global loads and stores"
68>;
69
70def FeatureTrapHandler: SubtargetFeature<"trap-handler",
71  "TrapHandler",
72  "true",
73  "Trap handler support"
74>;
75
76def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
77  "UnalignedScratchAccess",
78  "true",
79  "Support unaligned scratch loads and stores"
80>;
81
82def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
83  "HasApertureRegs",
84  "true",
85  "Has Memory Aperture Base and Size Registers"
86>;
87
88// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
89// XNACK. The current default kernel driver setting is:
90// - graphics ring: XNACK disabled
91// - compute ring: XNACK enabled
92//
93// If XNACK is enabled, the VMEM latency can be worse.
94// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
95def FeatureXNACK : SubtargetFeature<"xnack",
96  "EnableXNACK",
97  "true",
98  "Enable XNACK support"
99>;
100
101def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
102  "SGPRInitBug",
103  "true",
104  "VI SGPR initilization bug requiring a fixed SGPR allocation size"
105>;
106
107class SubtargetFeatureFetchLimit <string Value> :
108                          SubtargetFeature <"fetch"#Value,
109  "TexVTXClauseSize",
110  Value,
111  "Limit the maximum number of fetches in a clause to "#Value
112>;
113
114def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
115def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
116
117class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
118  "wavefrontsize"#Value,
119  "WavefrontSize",
120  !cast<string>(Value),
121  "The number of threads per wavefront"
122>;
123
124def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
125def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
126def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
127
128class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
129  "ldsbankcount"#Value,
130  "LDSBankCount",
131  !cast<string>(Value),
132  "The number of LDS banks per compute unit."
133>;
134
135def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
136def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
137
138class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
139  "localmemorysize"#Value,
140  "LocalMemorySize",
141  !cast<string>(Value),
142  "The size of local memory in bytes"
143>;
144
145def FeatureGCN : SubtargetFeature<"gcn",
146  "IsGCN",
147  "true",
148  "GCN or newer GPU"
149>;
150
151def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",
152  "GCN1Encoding",
153  "true",
154  "Encoding format for SI and CI"
155>;
156
157def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
158  "GCN3Encoding",
159  "true",
160  "Encoding format for VI"
161>;
162
163def FeatureCIInsts : SubtargetFeature<"ci-insts",
164  "CIInsts",
165  "true",
166  "Additional intstructions for CI+"
167>;
168
169def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
170  "GFX9Insts",
171  "true",
172  "Additional intstructions for GFX9+"
173>;
174
175def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
176  "HasSMemRealTime",
177  "true",
178  "Has s_memrealtime instruction"
179>;
180
181def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
182  "HasInv2PiInlineImm",
183  "true",
184  "Has 1 / (2 * pi) as inline immediate"
185>;
186
187def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
188  "Has16BitInsts",
189  "true",
190  "Has i16/f16 instructions"
191>;
192
193def FeatureVOP3P : SubtargetFeature<"vop3p",
194  "HasVOP3PInsts",
195  "true",
196  "Has VOP3P packed instructions"
197>;
198
199def FeatureMovrel : SubtargetFeature<"movrel",
200  "HasMovrel",
201  "true",
202  "Has v_movrel*_b32 instructions"
203>;
204
205def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
206  "HasVGPRIndexMode",
207  "true",
208  "Has VGPR mode register indexing"
209>;
210
211def FeatureScalarStores : SubtargetFeature<"scalar-stores",
212  "HasScalarStores",
213  "true",
214  "Has store scalar memory instructions"
215>;
216
217def FeatureSDWA : SubtargetFeature<"sdwa",
218  "HasSDWA",
219  "true",
220  "Support SDWA (Sub-DWORD Addressing) extension"
221>;
222
223def FeatureDPP : SubtargetFeature<"dpp",
224  "HasDPP",
225  "true",
226  "Support DPP (Data Parallel Primitives) extension"
227>;
228
229//===------------------------------------------------------------===//
230// Subtarget Features (options and debugging)
231//===------------------------------------------------------------===//
232
233// Some instructions do not support denormals despite this flag. Using
234// fp32 denormals also causes instructions to run at the double
235// precision rate for the device.
236def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
237  "FP32Denormals",
238  "true",
239  "Enable single precision denormal handling"
240>;
241
242// Denormal handling for fp64 and fp16 is controlled by the same
243// config register when fp16 supported.
244// TODO: Do we need a separate f16 setting when not legal?
245def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
246  "FP64FP16Denormals",
247  "true",
248  "Enable double and half precision denormal handling",
249  [FeatureFP64]
250>;
251
252def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
253  "FP64FP16Denormals",
254  "true",
255  "Enable double and half precision denormal handling",
256  [FeatureFP64, FeatureFP64FP16Denormals]
257>;
258
259def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
260  "FP64FP16Denormals",
261  "true",
262  "Enable half precision denormal handling",
263  [FeatureFP64FP16Denormals]
264>;
265
266def FeatureDX10Clamp : SubtargetFeature<"dx10-clamp",
267  "DX10Clamp",
268  "true",
269  "clamp modifier clamps NaNs to 0.0"
270>;
271
272def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
273  "FPExceptions",
274  "true",
275  "Enable floating point exceptions"
276>;
277
278class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
279  "max-private-element-size-"#size,
280  "MaxPrivateElementSize",
281  !cast<string>(size),
282  "Maximum private access size may be "#size
283>;
284
285def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
286def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
287def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
288
289def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
290  "EnableVGPRSpilling",
291  "true",
292  "Enable spilling of VGPRs to scratch memory"
293>;
294
295def FeatureDumpCode : SubtargetFeature <"DumpCode",
296  "DumpCode",
297  "true",
298  "Dump MachineInstrs in the CodeEmitter"
299>;
300
301def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
302  "DumpCode",
303  "true",
304  "Dump MachineInstrs in the CodeEmitter"
305>;
306
307def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
308  "EnablePromoteAlloca",
309  "true",
310  "Enable promote alloca pass"
311>;
312
313// XXX - This should probably be removed once enabled by default
314def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
315  "EnableLoadStoreOpt",
316  "true",
317  "Enable SI load/store optimizer pass"
318>;
319
320// Performance debugging feature. Allow using DS instruction immediate
321// offsets even if the base pointer can't be proven to be base. On SI,
322// base pointer values that won't give the same result as a 16-bit add
323// are not safe to fold, but this will override the conservative test
324// for the base pointer.
325def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
326  "unsafe-ds-offset-folding",
327  "EnableUnsafeDSOffsetFolding",
328  "true",
329  "Force using DS instruction immediate offsets on SI"
330>;
331
332def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
333  "EnableSIScheduler",
334  "true",
335  "Enable SI Machine Scheduler"
336>;
337
338// Unless +-flat-for-global is specified, turn on FlatForGlobal for
339// all OS-es on VI and newer hardware to avoid assertion failures due
340// to missing ADDR64 variants of MUBUF instructions.
341// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
342// instructions.
343
344def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
345  "FlatForGlobal",
346  "true",
347  "Force to generate flat instruction for global"
348>;
349
350// Dummy feature used to disable assembler instructions.
351def FeatureDisable : SubtargetFeature<"",
352  "FeatureDisable","true",
353  "Dummy feature to disable assembler instructions"
354>;
355
356class SubtargetFeatureGeneration <string Value,
357                                  list<SubtargetFeature> Implies> :
358        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
359                          Value#" GPU generation", Implies>;
360
361def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
362def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
363def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
364
365def FeatureR600 : SubtargetFeatureGeneration<"R600",
366  [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]
367>;
368
369def FeatureR700 : SubtargetFeatureGeneration<"R700",
370  [FeatureFetchLimit16, FeatureLocalMemorySize0]
371>;
372
373def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
374  [FeatureFetchLimit16, FeatureLocalMemorySize32768]
375>;
376
377def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
378  [FeatureFetchLimit16, FeatureWavefrontSize64,
379   FeatureLocalMemorySize32768]
380>;
381
382def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
383  [FeatureFP64, FeatureLocalMemorySize32768,
384  FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
385  FeatureLDSBankCount32, FeatureMovrel]
386>;
387
388def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
389  [FeatureFP64, FeatureLocalMemorySize65536,
390  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
391  FeatureGCN1Encoding, FeatureCIInsts, FeatureMovrel]
392>;
393
394def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
395  [FeatureFP64, FeatureLocalMemorySize65536,
396   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
397   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
398   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
399   FeatureScalarStores, FeatureInv2PiInlineImm, FeatureSDWA,
400   FeatureDPP
401  ]
402>;
403
404def FeatureGFX9 : SubtargetFeatureGeneration<"GFX9",
405  [FeatureFP64, FeatureLocalMemorySize65536,
406   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
407   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
408   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
409   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P
410  ]
411>;
412
413class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
414                                  list<SubtargetFeature> Implies>
415                                 : SubtargetFeature <
416  "isaver"#Major#"."#Minor#"."#Stepping,
417  "IsaVersion",
418  "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
419  "Instruction set version number",
420  Implies
421>;
422
423def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
424  [FeatureSeaIslands,
425   FeatureLDSBankCount32]>;
426
427def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
428  [FeatureSeaIslands,
429   HalfRate64Ops,
430   FeatureLDSBankCount32,
431   FeatureFastFMAF32]>;
432
433def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
434  [FeatureSeaIslands,
435   FeatureLDSBankCount16]>;
436
437def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0,
438  [FeatureVolcanicIslands,
439   FeatureLDSBankCount32,
440   FeatureSGPRInitBug]>;
441
442def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
443  [FeatureVolcanicIslands,
444   FeatureLDSBankCount32,
445   FeatureXNACK]>;
446
447def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
448  [FeatureVolcanicIslands,
449   FeatureLDSBankCount32,
450   FeatureSGPRInitBug]>;
451
452def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
453  [FeatureVolcanicIslands,
454   FeatureLDSBankCount32]>;
455
456def FeatureISAVersion8_0_4 : SubtargetFeatureISAVersion <8,0,4,
457  [FeatureVolcanicIslands,
458   FeatureLDSBankCount32]>;
459
460def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
461  [FeatureVolcanicIslands,
462   FeatureLDSBankCount16,
463   FeatureXNACK]>;
464
465def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,[]>;
466def FeatureISAVersion9_0_1 : SubtargetFeatureISAVersion <9,0,1,[]>;
467
468//===----------------------------------------------------------------------===//
469// Debugger related subtarget features.
470//===----------------------------------------------------------------------===//
471
472def FeatureDebuggerInsertNops : SubtargetFeature<
473  "amdgpu-debugger-insert-nops",
474  "DebuggerInsertNops",
475  "true",
476  "Insert one nop instruction for each high level source statement"
477>;
478
479def FeatureDebuggerReserveRegs : SubtargetFeature<
480  "amdgpu-debugger-reserve-regs",
481  "DebuggerReserveRegs",
482  "true",
483  "Reserve registers for debugger usage"
484>;
485
486def FeatureDebuggerEmitPrologue : SubtargetFeature<
487  "amdgpu-debugger-emit-prologue",
488  "DebuggerEmitPrologue",
489  "true",
490  "Emit debugger prologue"
491>;
492
493//===----------------------------------------------------------------------===//
494
495def AMDGPUInstrInfo : InstrInfo {
496  let guessInstructionProperties = 1;
497  let noNamedPositionallyEncodedOperands = 1;
498}
499
500def AMDGPUAsmParser : AsmParser {
501  // Some of the R600 registers have the same name, so this crashes.
502  // For example T0_XYZW and T0_XY both have the asm name T0.
503  let ShouldEmitMatchRegisterName = 0;
504}
505
506def AMDGPUAsmWriter : AsmWriter {
507  int PassSubtarget = 1;
508}
509
510def AMDGPUAsmVariants {
511  string Default = "Default";
512  int Default_ID = 0;
513  string VOP3 = "VOP3";
514  int VOP3_ID = 1;
515  string SDWA = "SDWA";
516  int SDWA_ID = 2;
517  string DPP = "DPP";
518  int DPP_ID = 3;
519  string Disable = "Disable";
520  int Disable_ID = 4;
521}
522
523def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
524  let Variant = AMDGPUAsmVariants.Default_ID;
525  let Name = AMDGPUAsmVariants.Default;
526}
527
528def VOP3AsmParserVariant : AsmParserVariant {
529  let Variant = AMDGPUAsmVariants.VOP3_ID;
530  let Name = AMDGPUAsmVariants.VOP3;
531}
532
533def SDWAAsmParserVariant : AsmParserVariant {
534  let Variant = AMDGPUAsmVariants.SDWA_ID;
535  let Name = AMDGPUAsmVariants.SDWA;
536}
537
538def DPPAsmParserVariant : AsmParserVariant {
539  let Variant = AMDGPUAsmVariants.DPP_ID;
540  let Name = AMDGPUAsmVariants.DPP;
541}
542
543def AMDGPU : Target {
544  // Pull in Instruction Info:
545  let InstructionSet = AMDGPUInstrInfo;
546  let AssemblyParsers = [AMDGPUAsmParser];
547  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
548                                VOP3AsmParserVariant,
549                                SDWAAsmParserVariant,
550                                DPPAsmParserVariant];
551  let AssemblyWriters = [AMDGPUAsmWriter];
552}
553
554// Dummy Instruction itineraries for pseudo instructions
555def ALU_NULL : FuncUnit;
556def NullALU : InstrItinClass;
557
558//===----------------------------------------------------------------------===//
559// Predicate helper class
560//===----------------------------------------------------------------------===//
561
562def TruePredicate : Predicate<"true">;
563
564def isSICI : Predicate<
565  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
566  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
567>, AssemblerPredicate<"FeatureGCN1Encoding">;
568
569def isVI : Predicate <
570  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
571  AssemblerPredicate<"FeatureGCN3Encoding">;
572
573def isGFX9 : Predicate <
574  "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
575  AssemblerPredicate<"FeatureGFX9Insts">;
576
577// TODO: Either the name to be changed or we simply use IsCI!
578def isCIVI : Predicate <
579  "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
580  AssemblerPredicate<"FeatureCIInsts">;
581
582def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">;
583
584def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
585  AssemblerPredicate<"Feature16BitInsts">;
586def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
587  AssemblerPredicate<"FeatureVOP3P">;
588
589def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
590  AssemblerPredicate<"FeatureSDWA">;
591
592def HasDPP : Predicate<"Subtarget->hasDPP()">,
593  AssemblerPredicate<"FeatureDPP">;
594
595class PredicateControl {
596  Predicate SubtargetPredicate;
597  Predicate SIAssemblerPredicate = isSICI;
598  Predicate VIAssemblerPredicate = isVI;
599  list<Predicate> AssemblerPredicates = [];
600  Predicate AssemblerPredicate = TruePredicate;
601  list<Predicate> OtherPredicates = [];
602  list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
603                                            AssemblerPredicates,
604                                            OtherPredicates);
605}
606
607// Include AMDGPU TD files
608include "R600Schedule.td"
609include "SISchedule.td"
610include "Processors.td"
611include "AMDGPUInstrInfo.td"
612include "AMDGPUIntrinsics.td"
613include "AMDGPURegisterInfo.td"
614include "AMDGPURegisterBanks.td"
615include "AMDGPUInstructions.td"
616include "AMDGPUCallingConv.td"
617