1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21class BoolToList<bit Value> {
22  list<int> ret = !if(Value, [1]<int>, []<int>);
23}
24
25//===------------------------------------------------------------===//
26// Subtarget Features (device properties)
27//===------------------------------------------------------------===//
28
29def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
30  "FastFMAF32",
31  "true",
32  "Assuming f32 fma is at least as fast as mul + add"
33>;
34
35def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
36  "FastDenormalF32",
37  "true",
38  "Enabling denormals does not cause f32 instructions to run at f64 rates"
39>;
40
41def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
42  "MIMG_R128",
43  "true",
44  "Support 128-bit texture resources"
45>;
46
47def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
48  "HalfRate64Ops",
49  "true",
50  "Most fp64 instructions are half rate instead of quarter"
51>;
52
53def FullRate64Ops : SubtargetFeature<"full-rate-64-ops",
54  "FullRate64Ops",
55  "true",
56  "Most fp64 instructions are full rate"
57>;
58
59def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
60  "FlatAddressSpace",
61  "true",
62  "Support flat address space"
63>;
64
65def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
66  "FlatInstOffsets",
67  "true",
68  "Flat instructions have immediate offset addressing mode"
69>;
70
71def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
72  "FlatGlobalInsts",
73  "true",
74  "Have global_* flat memory instructions"
75>;
76
77def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
78  "FlatScratchInsts",
79  "true",
80  "Have scratch_* flat memory instructions"
81>;
82
83def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
84  "ScalarFlatScratchInsts",
85  "true",
86  "Have s_scratch_* flat memory instructions"
87>;
88
89def FeatureEnableFlatScratch : SubtargetFeature<"enable-flat-scratch",
90  "EnableFlatScratch",
91  "true",
92  "Use scratch_* flat memory instructions to access scratch"
93>;
94
95def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
96  "AddNoCarryInsts",
97  "true",
98  "Have VALU add/sub instructions without carry out"
99>;
100
101def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
102  "UnalignedBufferAccess",
103  "true",
104  "Hardware supports unaligned global loads and stores"
105>;
106
107def FeatureTrapHandler: SubtargetFeature<"trap-handler",
108  "TrapHandler",
109  "true",
110  "Trap handler support"
111>;
112
113def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
114  "UnalignedScratchAccess",
115  "true",
116  "Support unaligned scratch loads and stores"
117>;
118
119def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access",
120  "UnalignedDSAccess",
121  "true",
122  "Hardware supports unaligned local and region loads and stores"
123>;
124
125def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
126  "HasApertureRegs",
127  "true",
128  "Has Memory Aperture Base and Size Registers"
129>;
130
131def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
132  "HasMadMixInsts",
133  "true",
134  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
135>;
136
137def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
138  "HasFmaMixInsts",
139  "true",
140  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
141>;
142
143def FeatureSupportsXNACK : SubtargetFeature<"xnack-support",
144  "SupportsXNACK",
145  "true",
146  "Hardware supports XNACK"
147>;
148
149// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
150// XNACK. The current default kernel driver setting is:
151// - graphics ring: XNACK disabled
152// - compute ring: XNACK enabled
153//
154// If XNACK is enabled, the VMEM latency can be worse.
155// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
156def FeatureXNACK : SubtargetFeature<"xnack",
157  "EnableXNACK",
158  "true",
159  "Enable XNACK support"
160>;
161
162def FeatureTgSplit : SubtargetFeature<"tgsplit",
163  "EnableTgSplit",
164  "true",
165  "Enable threadgroup split execution"
166>;
167
168def FeatureCuMode : SubtargetFeature<"cumode",
169  "EnableCuMode",
170  "true",
171  "Enable CU wavefront execution mode"
172>;
173
174def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
175  "SGPRInitBug",
176  "true",
177  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
178>;
179
180def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
181  "LDSMisalignedBug",
182  "true",
183  "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode"
184>;
185
186def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
187  "HasMFMAInlineLiteralBug",
188  "true",
189  "MFMA cannot use inline literal as SrcC"
190>;
191
192def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
193  "HasVcmpxPermlaneHazard",
194  "true",
195  "TODO: describe me"
196>;
197
198def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
199  "HasVMEMtoScalarWriteHazard",
200  "true",
201  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
202>;
203
204def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
205  "HasSMEMtoVectorWriteHazard",
206  "true",
207  "s_load_dword followed by v_cmp page faults"
208>;
209
210def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
211  "HasInstFwdPrefetchBug",
212  "true",
213  "S_INST_PREFETCH instruction causes shader to hang"
214>;
215
216def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
217  "HasVcmpxExecWARHazard",
218  "true",
219  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
220>;
221
222def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
223  "HasLdsBranchVmemWARHazard",
224  "true",
225  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
226>;
227
228def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
229  "HasNSAtoVMEMBug",
230  "true",
231  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
232>;
233
234def FeatureNSAClauseBug : SubtargetFeature<"nsa-clause-bug",
235  "HasNSAClauseBug",
236  "true",
237  "MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
238>;
239
240def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
241  "HasFlatSegmentOffsetBug",
242  "true",
243  "GFX10 bug where inst_offset is ignored when flat instructions access global memory"
244>;
245
246def FeatureNegativeScratchOffsetBug : SubtargetFeature<"negative-scratch-offset-bug",
247  "NegativeScratchOffsetBug",
248  "true",
249  "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9"
250>;
251
252def FeatureNegativeUnalignedScratchOffsetBug : SubtargetFeature<"negative-unaligned-scratch-offset-bug",
253  "NegativeUnalignedScratchOffsetBug",
254  "true",
255  "Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10"
256>;
257
258def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
259  "HasOffset3fBug",
260  "true",
261  "Branch offset of 3f hardware bug"
262>;
263
264def FeatureImageStoreD16Bug : SubtargetFeature<"image-store-d16-bug",
265  "HasImageStoreD16Bug",
266  "true",
267  "Image Store D16 hardware bug"
268>;
269
270def FeatureImageGather4D16Bug : SubtargetFeature<"image-gather4-d16-bug",
271  "HasImageGather4D16Bug",
272  "true",
273  "Image Gather4 D16 hardware bug"
274>;
275
276class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
277  "ldsbankcount"#Value,
278  "LDSBankCount",
279  !cast<string>(Value),
280  "The number of LDS banks per compute unit."
281>;
282
283def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
284def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
285
286def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
287  "GCN3Encoding",
288  "true",
289  "Encoding format for VI"
290>;
291
292def FeatureCIInsts : SubtargetFeature<"ci-insts",
293  "CIInsts",
294  "true",
295  "Additional instructions for CI+"
296>;
297
298def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
299  "GFX8Insts",
300  "true",
301  "Additional instructions for GFX8+"
302>;
303
304def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
305  "GFX9Insts",
306  "true",
307  "Additional instructions for GFX9+"
308>;
309
310def FeatureGFX90AInsts : SubtargetFeature<"gfx90a-insts",
311  "GFX90AInsts",
312  "true",
313  "Additional instructions for GFX90A+"
314>;
315
316def FeatureGFX940Insts : SubtargetFeature<"gfx940-insts",
317  "GFX940Insts",
318  "true",
319  "Additional instructions for GFX940+"
320>;
321
322def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
323  "GFX10Insts",
324  "true",
325  "Additional instructions for GFX10+"
326>;
327
328def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts",
329  "GFX10_3Insts",
330  "true",
331  "Additional instructions for GFX10.3"
332>;
333
334def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
335  "GFX7GFX8GFX9Insts",
336  "true",
337  "Instructions shared in GFX7, GFX8, GFX9"
338>;
339
340def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
341  "HasSMemRealTime",
342  "true",
343  "Has s_memrealtime instruction"
344>;
345
346def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
347  "HasInv2PiInlineImm",
348  "true",
349  "Has 1 / (2 * pi) as inline immediate"
350>;
351
352def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
353  "Has16BitInsts",
354  "true",
355  "Has i16/f16 instructions"
356>;
357
358def FeatureVOP3P : SubtargetFeature<"vop3p",
359  "HasVOP3PInsts",
360  "true",
361  "Has VOP3P packed instructions"
362>;
363
364def FeatureMovrel : SubtargetFeature<"movrel",
365  "HasMovrel",
366  "true",
367  "Has v_movrel*_b32 instructions"
368>;
369
370def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
371  "HasVGPRIndexMode",
372  "true",
373  "Has VGPR mode register indexing"
374>;
375
376def FeatureScalarStores : SubtargetFeature<"scalar-stores",
377  "HasScalarStores",
378  "true",
379  "Has store scalar memory instructions"
380>;
381
382def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
383  "HasScalarAtomics",
384  "true",
385  "Has atomic scalar memory instructions"
386>;
387
388def FeatureSDWA : SubtargetFeature<"sdwa",
389  "HasSDWA",
390  "true",
391  "Support SDWA (Sub-DWORD Addressing) extension"
392>;
393
394def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
395  "HasSDWAOmod",
396  "true",
397  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
398>;
399
400def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
401  "HasSDWAScalar",
402  "true",
403  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
404>;
405
406def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
407  "HasSDWASdst",
408  "true",
409  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
410>;
411
412def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
413  "HasSDWAMac",
414  "true",
415  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
416>;
417
418def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
419  "HasSDWAOutModsVOPC",
420  "true",
421  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
422>;
423
424def FeatureDPP : SubtargetFeature<"dpp",
425  "HasDPP",
426  "true",
427  "Support DPP (Data Parallel Primitives) extension"
428>;
429
430// DPP8 allows arbitrary cross-lane swizzling within groups of 8 lanes.
431def FeatureDPP8 : SubtargetFeature<"dpp8",
432  "HasDPP8",
433  "true",
434  "Support DPP8 (Data Parallel Primitives) extension"
435>;
436
437def Feature64BitDPP : SubtargetFeature<"dpp-64bit",
438  "Has64BitDPP",
439  "true",
440  "Support DPP (Data Parallel Primitives) extension"
441>;
442
443def FeaturePackedFP32Ops : SubtargetFeature<"packed-fp32-ops",
444  "HasPackedFP32Ops",
445  "true",
446  "Support packed fp32 instructions"
447>;
448
449def FeatureR128A16 : SubtargetFeature<"r128-a16",
450  "HasR128A16",
451  "true",
452  "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
453>;
454
455def FeatureGFX10A16 : SubtargetFeature<"a16",
456  "HasGFX10A16",
457  "true",
458  "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
459>;
460
461def FeatureG16 : SubtargetFeature<"g16",
462  "HasG16",
463  "true",
464  "Support G16 for 16-bit gradient image operands"
465>;
466
467def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
468  "HasNSAEncoding",
469  "true",
470  "Support NSA encoding for image instructions"
471>;
472
473def FeatureImageInsts : SubtargetFeature<"image-insts",
474  "HasImageInsts",
475  "true",
476  "Support image instructions"
477>;
478
479def FeatureExtendedImageInsts : SubtargetFeature<"extended-image-insts",
480  "HasExtendedImageInsts",
481  "true",
482  "Support mips != 0, lod != 0, gather4, and get_lod"
483>;
484
485def FeatureGFX10_AEncoding : SubtargetFeature<"gfx10_a-encoding",
486  "GFX10_AEncoding",
487  "true",
488  "Has BVH ray tracing instructions"
489>;
490
491def FeatureGFX10_BEncoding : SubtargetFeature<"gfx10_b-encoding",
492  "GFX10_BEncoding",
493  "true",
494  "Encoding format GFX10_B"
495>;
496
497def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
498  "HasIntClamp",
499  "true",
500  "Support clamp for integer destination"
501>;
502
503def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
504  "HasUnpackedD16VMem",
505  "true",
506  "Has unpacked d16 vmem instructions"
507>;
508
509def FeatureDLInsts : SubtargetFeature<"dl-insts",
510  "HasDLInsts",
511  "true",
512  "Has v_fmac_f32 and v_xnor_b32 instructions"
513>;
514
515def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
516  "HasDot1Insts",
517  "true",
518  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
519>;
520
521def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
522  "HasDot2Insts",
523  "true",
524  "Has v_dot2_i32_i16, v_dot2_u32_u16 instructions"
525>;
526
527def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
528  "HasDot3Insts",
529  "true",
530  "Has v_dot8c_i32_i4 instruction"
531>;
532
533def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
534  "HasDot4Insts",
535  "true",
536  "Has v_dot2c_i32_i16 instruction"
537>;
538
539def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
540  "HasDot5Insts",
541  "true",
542  "Has v_dot2c_f32_f16 instruction"
543>;
544
545def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
546  "HasDot6Insts",
547  "true",
548  "Has v_dot4c_i32_i8 instruction"
549>;
550
551def FeatureDot7Insts : SubtargetFeature<"dot7-insts",
552  "HasDot7Insts",
553  "true",
554  "Has v_dot2_f32_f16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
555>;
556
557def FeatureMAIInsts : SubtargetFeature<"mai-insts",
558  "HasMAIInsts",
559  "true",
560  "Has mAI instructions"
561>;
562
563def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
564  "HasPkFmacF16Inst",
565  "true",
566  "Has v_pk_fmac_f16 instruction"
567>;
568
569def FeatureAtomicFaddRtnInsts : SubtargetFeature<"atomic-fadd-rtn-insts",
570  "HasAtomicFaddRtnInsts",
571  "true",
572  "Has buffer_atomic_add_f32 and global_atomic_add_f32 instructions that "
573  "return original value",
574  [FeatureFlatGlobalInsts]
575>;
576
577def FeatureAtomicFaddNoRtnInsts : SubtargetFeature<"atomic-fadd-no-rtn-insts",
578  "HasAtomicFaddNoRtnInsts",
579  "true",
580  "Has buffer_atomic_add_f32 and global_atomic_add_f32 instructions that "
581  "don't return original value",
582  [FeatureFlatGlobalInsts]
583>;
584
585def FeatureAtomicPkFaddNoRtnInsts
586  : SubtargetFeature<"atomic-pk-fadd-no-rtn-insts",
587  "HasAtomicPkFaddNoRtnInsts",
588  "true",
589  "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that "
590  "don't return original value",
591  [FeatureFlatGlobalInsts]
592>;
593
594def FeatureSupportsSRAMECC : SubtargetFeature<"sramecc-support",
595  "SupportsSRAMECC",
596  "true",
597  "Hardware supports SRAMECC"
598>;
599
600def FeatureSRAMECC : SubtargetFeature<"sramecc",
601  "EnableSRAMECC",
602  "true",
603  "Enable SRAMECC"
604>;
605
606def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
607  "HasNoSdstCMPX",
608  "true",
609  "V_CMPX does not write VCC/SGPR in addition to EXEC"
610>;
611
612def FeatureVscnt : SubtargetFeature<"vscnt",
613  "HasVscnt",
614  "true",
615  "Has separate store vscnt counter"
616>;
617
618def FeatureGetWaveIdInst : SubtargetFeature<"get-wave-id-inst",
619  "HasGetWaveIdInst",
620  "true",
621  "Has s_get_waveid_in_workgroup instruction"
622>;
623
624def FeatureSMemTimeInst : SubtargetFeature<"s-memtime-inst",
625  "HasSMemTimeInst",
626  "true",
627  "Has s_memtime instruction"
628>;
629
630def FeatureShaderCyclesRegister : SubtargetFeature<"shader-cycles-register",
631  "HasShaderCyclesRegister",
632  "true",
633  "Has SHADER_CYCLES hardware register"
634>;
635
636def FeatureMadMacF32Insts : SubtargetFeature<"mad-mac-f32-insts",
637  "HasMadMacF32Insts",
638  "true",
639  "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions"
640>;
641
642def FeatureDsSrc2Insts : SubtargetFeature<"ds-src2-insts",
643  "HasDsSrc2Insts",
644  "true",
645  "Has ds_*_src2 instructions"
646>;
647
648def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
649  "HasVOP3Literal",
650  "true",
651  "Can use one literal in VOP3"
652>;
653
654def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
655  "HasNoDataDepHazard",
656  "true",
657  "Does not need SW waitstates"
658>;
659
660class SubtargetFeatureNSAMaxSize <int Value> : SubtargetFeature <
661  "nsa-max-size-"#Value,
662  "NSAMaxSize",
663  !cast<string>(Value),
664  "The maximum non-sequential address size in VGPRs."
665>;
666
667def FeatureNSAMaxSize5 : SubtargetFeatureNSAMaxSize<5>;
668def FeatureNSAMaxSize13 : SubtargetFeatureNSAMaxSize<13>;
669
670//===------------------------------------------------------------===//
671// Subtarget Features (options and debugging)
672//===------------------------------------------------------------===//
673
674class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
675  "max-private-element-size-"#size,
676  "MaxPrivateElementSize",
677  !cast<string>(size),
678  "Maximum private access size may be "#size
679>;
680
681def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
682def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
683def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
684
685def FeatureDumpCode : SubtargetFeature <"DumpCode",
686  "DumpCode",
687  "true",
688  "Dump MachineInstrs in the CodeEmitter"
689>;
690
691def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
692  "DumpCode",
693  "true",
694  "Dump MachineInstrs in the CodeEmitter"
695>;
696
697// XXX - This should probably be removed once enabled by default
698def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
699  "EnableLoadStoreOpt",
700  "true",
701  "Enable SI load/store optimizer pass"
702>;
703
704// Performance debugging feature. Allow using DS instruction immediate
705// offsets even if the base pointer can't be proven to be base. On SI,
706// base pointer values that won't give the same result as a 16-bit add
707// are not safe to fold, but this will override the conservative test
708// for the base pointer.
709def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
710  "unsafe-ds-offset-folding",
711  "EnableUnsafeDSOffsetFolding",
712  "true",
713  "Force using DS instruction immediate offsets on SI"
714>;
715
716def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
717  "EnableSIScheduler",
718  "true",
719  "Enable SI Machine Scheduler"
720>;
721
722def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
723  "EnableDS128",
724  "true",
725  "Use ds_{read|write}_b128"
726>;
727
728// Sparse texture support requires that all result registers are zeroed when
729// PRTStrictNull is set to true. This feature is turned on for all architectures
730// but is enabled as a feature in case there are situations where PRTStrictNull
731// is disabled by the driver.
732def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
733  "EnablePRTStrictNull",
734  "true",
735  "Enable zeroing of result registers for sparse texture fetches"
736>;
737
738// Unless +-flat-for-global is specified, turn on FlatForGlobal for
739// all OS-es on VI and newer hardware to avoid assertion failures due
740// to missing ADDR64 variants of MUBUF instructions.
741// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
742// instructions.
743
744def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
745  "FlatForGlobal",
746  "true",
747  "Force to generate flat instruction for global"
748>;
749
750def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
751  "auto-waitcnt-before-barrier",
752  "AutoWaitcntBeforeBarrier",
753  "true",
754  "Hardware automatically inserts waitcnt before barrier"
755>;
756
757def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
758  "HasTrigReducedRange",
759  "true",
760  "Requires use of fract on arguments to trig instructions"
761>;
762
763// Alignment enforcement is controlled by a configuration register:
764// SH_MEM_CONFIG.alignment_mode
765def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode",
766  "UnalignedAccessMode",
767  "true",
768  "Enable unaligned global, local and region loads and stores if the hardware"
769  " supports it"
770>;
771
772def FeaturePackedTID : SubtargetFeature<"packed-tid",
773  "HasPackedTID",
774  "true",
775  "Workitem IDs are packed into v0 at kernel launch"
776>;
777
778def FeatureArchitectedFlatScratch : SubtargetFeature<"architected-flat-scratch",
779  "HasArchitectedFlatScratch",
780  "true",
781  "Flat Scratch register is a readonly SPI initialized architected register"
782>;
783
784// Dummy feature used to disable assembler instructions.
785def FeatureDisable : SubtargetFeature<"",
786  "FeatureDisable","true",
787  "Dummy feature to disable assembler instructions"
788>;
789
790class GCNSubtargetFeatureGeneration <string Value,
791                                     string FeatureName,
792                                     list<SubtargetFeature> Implies> :
793        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
794
795def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
796    "southern-islands",
797  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
798  FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,
799  FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
800  FeatureTrigReducedRange, FeatureExtendedImageInsts, FeatureImageInsts
801  ]
802>;
803
804def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
805    "sea-islands",
806  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
807  FeatureWavefrontSize64, FeatureFlatAddressSpace,
808  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
809  FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
810  FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureUnalignedBufferAccess,
811  FeatureImageInsts
812  ]
813>;
814
815def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
816  "volcanic-islands",
817  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
818   FeatureWavefrontSize64, FeatureFlatAddressSpace,
819   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
820   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
821   FeatureScalarStores, FeatureInv2PiInlineImm,
822   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
823   FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
824   FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
825   FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureFastDenormalF32,
826   FeatureUnalignedBufferAccess, FeatureImageInsts
827  ]
828>;
829
830def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
831  "gfx9",
832  [FeatureFP64, FeatureLocalMemorySize65536,
833   FeatureWavefrontSize64, FeatureFlatAddressSpace,
834   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
835   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
836   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
837   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
838   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
839   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
840   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
841   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
842   FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureSupportsXNACK,
843   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess,
844   FeatureNegativeScratchOffsetBug
845  ]
846>;
847
848def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
849  "gfx10",
850  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
851   FeatureFlatAddressSpace,
852   FeatureCIInsts, Feature16BitInsts,
853   FeatureSMemRealTime, FeatureInv2PiInlineImm,
854   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
855   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
856   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
857   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
858   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
859   FeatureNoSdstCMPX, FeatureVscnt,
860   FeatureVOP3Literal, FeatureDPP8, FeatureExtendedImageInsts,
861   FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
862   FeatureGFX10A16, FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureG16,
863   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess, FeatureImageInsts
864  ]
865>;
866
867class FeatureSet<list<SubtargetFeature> Features_> {
868  list<SubtargetFeature> Features = Features_;
869}
870
871def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
872   FeatureFastFMAF32,
873   HalfRate64Ops,
874   FeatureLDSBankCount32]>;
875
876def FeatureISAVersion6_0_1 : FeatureSet<
877  [FeatureSouthernIslands,
878   FeatureLDSBankCount32]>;
879
880def FeatureISAVersion6_0_2 : FeatureSet<
881  [FeatureSouthernIslands,
882   FeatureLDSBankCount32]>;
883
884def FeatureISAVersion7_0_0 : FeatureSet<
885  [FeatureSeaIslands,
886   FeatureLDSBankCount32]>;
887
888def FeatureISAVersion7_0_1 : FeatureSet<
889  [FeatureSeaIslands,
890   HalfRate64Ops,
891   FeatureLDSBankCount32,
892   FeatureFastFMAF32]>;
893
894def FeatureISAVersion7_0_2 : FeatureSet<
895  [FeatureSeaIslands,
896   FeatureLDSBankCount16,
897   FeatureFastFMAF32]>;
898
899def FeatureISAVersion7_0_3 : FeatureSet<
900  [FeatureSeaIslands,
901   FeatureLDSBankCount16]>;
902
903def FeatureISAVersion7_0_4 : FeatureSet<
904  [FeatureSeaIslands,
905   FeatureLDSBankCount32]>;
906
907def FeatureISAVersion7_0_5 : FeatureSet<
908  [FeatureSeaIslands,
909   FeatureLDSBankCount16]>;
910
911def FeatureISAVersion8_0_1 : FeatureSet<
912  [FeatureVolcanicIslands,
913   FeatureFastFMAF32,
914   HalfRate64Ops,
915   FeatureLDSBankCount32,
916   FeatureSupportsXNACK,
917   FeatureUnpackedD16VMem]>;
918
919def FeatureISAVersion8_0_2 : FeatureSet<
920  [FeatureVolcanicIslands,
921   FeatureLDSBankCount32,
922   FeatureSGPRInitBug,
923   FeatureUnpackedD16VMem]>;
924
925def FeatureISAVersion8_0_3 : FeatureSet<
926  [FeatureVolcanicIslands,
927   FeatureLDSBankCount32,
928   FeatureUnpackedD16VMem]>;
929
930def FeatureISAVersion8_0_5 : FeatureSet<
931  [FeatureVolcanicIslands,
932   FeatureLDSBankCount32,
933   FeatureSGPRInitBug,
934   FeatureUnpackedD16VMem]>;
935
936def FeatureISAVersion8_1_0 : FeatureSet<
937  [FeatureVolcanicIslands,
938   FeatureLDSBankCount16,
939   FeatureSupportsXNACK,
940   FeatureImageStoreD16Bug,
941   FeatureImageGather4D16Bug]>;
942
943def FeatureISAVersion9_0_0 : FeatureSet<
944  [FeatureGFX9,
945   FeatureMadMixInsts,
946   FeatureLDSBankCount32,
947   FeatureDsSrc2Insts,
948   FeatureExtendedImageInsts,
949   FeatureImageInsts,
950   FeatureMadMacF32Insts,
951   FeatureImageGather4D16Bug]>;
952
953def FeatureISAVersion9_0_2 : FeatureSet<
954  [FeatureGFX9,
955   FeatureMadMixInsts,
956   FeatureLDSBankCount32,
957   FeatureDsSrc2Insts,
958   FeatureExtendedImageInsts,
959   FeatureImageInsts,
960   FeatureMadMacF32Insts,
961   FeatureImageGather4D16Bug]>;
962
963def FeatureISAVersion9_0_4 : FeatureSet<
964  [FeatureGFX9,
965   FeatureLDSBankCount32,
966   FeatureDsSrc2Insts,
967   FeatureExtendedImageInsts,
968   FeatureImageInsts,
969   FeatureMadMacF32Insts,
970   FeatureFmaMixInsts,
971   FeatureImageGather4D16Bug]>;
972
973def FeatureISAVersion9_0_6 : FeatureSet<
974  [FeatureGFX9,
975   HalfRate64Ops,
976   FeatureFmaMixInsts,
977   FeatureLDSBankCount32,
978   FeatureDsSrc2Insts,
979   FeatureExtendedImageInsts,
980   FeatureImageInsts,
981   FeatureMadMacF32Insts,
982   FeatureDLInsts,
983   FeatureDot1Insts,
984   FeatureDot2Insts,
985   FeatureDot7Insts,
986   FeatureSupportsSRAMECC,
987   FeatureImageGather4D16Bug]>;
988
989def FeatureISAVersion9_0_8 : FeatureSet<
990  [FeatureGFX9,
991   HalfRate64Ops,
992   FeatureFmaMixInsts,
993   FeatureLDSBankCount32,
994   FeatureDsSrc2Insts,
995   FeatureExtendedImageInsts,
996   FeatureImageInsts,
997   FeatureMadMacF32Insts,
998   FeatureDLInsts,
999   FeatureDot1Insts,
1000   FeatureDot2Insts,
1001   FeatureDot3Insts,
1002   FeatureDot4Insts,
1003   FeatureDot5Insts,
1004   FeatureDot6Insts,
1005   FeatureDot7Insts,
1006   FeatureMAIInsts,
1007   FeaturePkFmacF16Inst,
1008   FeatureAtomicFaddNoRtnInsts,
1009   FeatureAtomicPkFaddNoRtnInsts,
1010   FeatureSupportsSRAMECC,
1011   FeatureMFMAInlineLiteralBug,
1012   FeatureImageGather4D16Bug]>;
1013
1014def FeatureISAVersion9_0_9 : FeatureSet<
1015  [FeatureGFX9,
1016   FeatureMadMixInsts,
1017   FeatureLDSBankCount32,
1018   FeatureDsSrc2Insts,
1019   FeatureExtendedImageInsts,
1020   FeatureImageInsts,
1021   FeatureMadMacF32Insts,
1022   FeatureImageGather4D16Bug]>;
1023
1024def FeatureISAVersion9_0_A : FeatureSet<
1025  [FeatureGFX9,
1026   FeatureGFX90AInsts,
1027   FeatureFmaMixInsts,
1028   FeatureLDSBankCount32,
1029   FeatureDLInsts,
1030   FeatureDot1Insts,
1031   FeatureDot2Insts,
1032   FeatureDot3Insts,
1033   FeatureDot4Insts,
1034   FeatureDot5Insts,
1035   FeatureDot6Insts,
1036   FeatureDot7Insts,
1037   Feature64BitDPP,
1038   FeaturePackedFP32Ops,
1039   FeatureMAIInsts,
1040   FeaturePkFmacF16Inst,
1041   FeatureAtomicFaddRtnInsts,
1042   FeatureAtomicFaddNoRtnInsts,
1043   FeatureAtomicPkFaddNoRtnInsts,
1044   FeatureImageInsts,
1045   FeatureMadMacF32Insts,
1046   FeatureSupportsSRAMECC,
1047   FeaturePackedTID,
1048   FullRate64Ops]>;
1049
1050def FeatureISAVersion9_0_C : FeatureSet<
1051  [FeatureGFX9,
1052   FeatureMadMixInsts,
1053   FeatureLDSBankCount32,
1054   FeatureDsSrc2Insts,
1055   FeatureExtendedImageInsts,
1056   FeatureImageInsts,
1057   FeatureMadMacF32Insts,
1058   FeatureImageGather4D16Bug]>;
1059
1060def FeatureISAVersion9_4_0 : FeatureSet<
1061  [FeatureGFX9,
1062   FeatureGFX90AInsts,
1063   FeatureGFX940Insts,
1064   FeatureFmaMixInsts,
1065   FeatureLDSBankCount32,
1066   FeatureDLInsts,
1067   FeatureDot1Insts,
1068   FeatureDot2Insts,
1069   FeatureDot3Insts,
1070   FeatureDot4Insts,
1071   FeatureDot5Insts,
1072   FeatureDot6Insts,
1073   FeatureDot7Insts,
1074   Feature64BitDPP,
1075   FeaturePackedFP32Ops,
1076   FeatureMAIInsts,
1077   FeaturePkFmacF16Inst,
1078   FeatureAtomicFaddRtnInsts,
1079   FeatureAtomicFaddNoRtnInsts,
1080   FeatureAtomicPkFaddNoRtnInsts,
1081   FeatureSupportsSRAMECC,
1082   FeaturePackedTID,
1083   FeatureArchitectedFlatScratch,
1084   FullRate64Ops]>;
1085
1086// TODO: Organize more features into groups.
1087def FeatureGroup {
1088  // Bugs present on gfx10.1.
1089  list<SubtargetFeature> GFX10_1_Bugs = [
1090    FeatureVcmpxPermlaneHazard,
1091    FeatureVMEMtoScalarWriteHazard,
1092    FeatureSMEMtoVectorWriteHazard,
1093    FeatureInstFwdPrefetchBug,
1094    FeatureVcmpxExecWARHazard,
1095    FeatureLdsBranchVmemWARHazard,
1096    FeatureNSAtoVMEMBug,
1097    FeatureNSAClauseBug,
1098    FeatureOffset3fBug,
1099    FeatureFlatSegmentOffsetBug,
1100    FeatureNegativeUnalignedScratchOffsetBug
1101   ];
1102}
1103
1104def FeatureISAVersion10_1_0 : FeatureSet<
1105  !listconcat(FeatureGroup.GFX10_1_Bugs,
1106    [FeatureGFX10,
1107     FeatureLDSBankCount32,
1108     FeatureDLInsts,
1109     FeatureNSAEncoding,
1110     FeatureNSAMaxSize5,
1111     FeatureWavefrontSize32,
1112     FeatureScalarStores,
1113     FeatureScalarAtomics,
1114     FeatureScalarFlatScratchInsts,
1115     FeatureGetWaveIdInst,
1116     FeatureMadMacF32Insts,
1117     FeatureDsSrc2Insts,
1118     FeatureLdsMisalignedBug,
1119     FeatureSupportsXNACK])>;
1120
1121def FeatureISAVersion10_1_1 : FeatureSet<
1122  !listconcat(FeatureGroup.GFX10_1_Bugs,
1123    [FeatureGFX10,
1124     FeatureLDSBankCount32,
1125     FeatureDLInsts,
1126     FeatureDot1Insts,
1127     FeatureDot2Insts,
1128     FeatureDot5Insts,
1129     FeatureDot6Insts,
1130     FeatureDot7Insts,
1131     FeatureNSAEncoding,
1132     FeatureNSAMaxSize5,
1133     FeatureWavefrontSize32,
1134     FeatureScalarStores,
1135     FeatureScalarAtomics,
1136     FeatureScalarFlatScratchInsts,
1137     FeatureGetWaveIdInst,
1138     FeatureMadMacF32Insts,
1139     FeatureDsSrc2Insts,
1140     FeatureLdsMisalignedBug,
1141     FeatureSupportsXNACK])>;
1142
1143def FeatureISAVersion10_1_2 : FeatureSet<
1144  !listconcat(FeatureGroup.GFX10_1_Bugs,
1145    [FeatureGFX10,
1146     FeatureLDSBankCount32,
1147     FeatureDLInsts,
1148     FeatureDot1Insts,
1149     FeatureDot2Insts,
1150     FeatureDot5Insts,
1151     FeatureDot6Insts,
1152     FeatureDot7Insts,
1153     FeatureNSAEncoding,
1154     FeatureNSAMaxSize5,
1155     FeatureWavefrontSize32,
1156     FeatureScalarStores,
1157     FeatureScalarAtomics,
1158     FeatureScalarFlatScratchInsts,
1159     FeatureGetWaveIdInst,
1160     FeatureMadMacF32Insts,
1161     FeatureDsSrc2Insts,
1162     FeatureLdsMisalignedBug,
1163     FeatureSupportsXNACK])>;
1164
1165def FeatureISAVersion10_1_3 : FeatureSet<
1166  !listconcat(FeatureGroup.GFX10_1_Bugs,
1167    [FeatureGFX10,
1168     FeatureGFX10_AEncoding,
1169     FeatureLDSBankCount32,
1170     FeatureDLInsts,
1171     FeatureNSAEncoding,
1172     FeatureNSAMaxSize5,
1173     FeatureWavefrontSize32,
1174     FeatureScalarStores,
1175     FeatureScalarAtomics,
1176     FeatureScalarFlatScratchInsts,
1177     FeatureGetWaveIdInst,
1178     FeatureMadMacF32Insts,
1179     FeatureDsSrc2Insts,
1180     FeatureLdsMisalignedBug,
1181     FeatureSupportsXNACK])>;
1182
1183def FeatureISAVersion10_3_0 : FeatureSet<
1184  [FeatureGFX10,
1185   FeatureGFX10_AEncoding,
1186   FeatureGFX10_BEncoding,
1187   FeatureGFX10_3Insts,
1188   FeatureLDSBankCount32,
1189   FeatureDLInsts,
1190   FeatureDot1Insts,
1191   FeatureDot2Insts,
1192   FeatureDot5Insts,
1193   FeatureDot6Insts,
1194   FeatureDot7Insts,
1195   FeatureNSAEncoding,
1196   FeatureNSAMaxSize13,
1197   FeatureWavefrontSize32,
1198   FeatureShaderCyclesRegister]>;
1199
1200//===----------------------------------------------------------------------===//
1201
1202def AMDGPUInstrInfo : InstrInfo {
1203  let guessInstructionProperties = 1;
1204  let noNamedPositionallyEncodedOperands = 1;
1205}
1206
1207def AMDGPUAsmParser : AsmParser {
1208  // Some of the R600 registers have the same name, so this crashes.
1209  // For example T0_XYZW and T0_XY both have the asm name T0.
1210  let ShouldEmitMatchRegisterName = 0;
1211}
1212
1213def AMDGPUAsmWriter : AsmWriter {
1214  int PassSubtarget = 1;
1215}
1216
1217def AMDGPUAsmVariants {
1218  string Default = "Default";
1219  int Default_ID = 0;
1220  string VOP3 = "VOP3";
1221  int VOP3_ID = 1;
1222  string SDWA = "SDWA";
1223  int SDWA_ID = 2;
1224  string SDWA9 = "SDWA9";
1225  int SDWA9_ID = 3;
1226  string DPP = "DPP";
1227  int DPP_ID = 4;
1228  string Disable = "Disable";
1229  int Disable_ID = 5;
1230}
1231
1232def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
1233  let Variant = AMDGPUAsmVariants.Default_ID;
1234  let Name = AMDGPUAsmVariants.Default;
1235}
1236
1237def VOP3AsmParserVariant : AsmParserVariant {
1238  let Variant = AMDGPUAsmVariants.VOP3_ID;
1239  let Name = AMDGPUAsmVariants.VOP3;
1240}
1241
1242def SDWAAsmParserVariant : AsmParserVariant {
1243  let Variant = AMDGPUAsmVariants.SDWA_ID;
1244  let Name = AMDGPUAsmVariants.SDWA;
1245}
1246
1247def SDWA9AsmParserVariant : AsmParserVariant {
1248  let Variant = AMDGPUAsmVariants.SDWA9_ID;
1249  let Name = AMDGPUAsmVariants.SDWA9;
1250}
1251
1252
1253def DPPAsmParserVariant : AsmParserVariant {
1254  let Variant = AMDGPUAsmVariants.DPP_ID;
1255  let Name = AMDGPUAsmVariants.DPP;
1256}
1257
1258def AMDGPU : Target {
1259  // Pull in Instruction Info:
1260  let InstructionSet = AMDGPUInstrInfo;
1261  let AssemblyParsers = [AMDGPUAsmParser];
1262  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
1263                                VOP3AsmParserVariant,
1264                                SDWAAsmParserVariant,
1265                                SDWA9AsmParserVariant,
1266                                DPPAsmParserVariant];
1267  let AssemblyWriters = [AMDGPUAsmWriter];
1268  let AllowRegisterRenaming = 1;
1269}
1270
1271// Dummy Instruction itineraries for pseudo instructions
1272def ALU_NULL : FuncUnit;
1273def NullALU : InstrItinClass;
1274
1275//===----------------------------------------------------------------------===//
1276// Predicate helper class
1277//===----------------------------------------------------------------------===//
1278
1279def isGFX6 :
1280  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1281  AssemblerPredicate<(all_of FeatureSouthernIslands)>;
1282
1283def isGFX6GFX7 :
1284  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1285            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1286  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
1287
1288def isGFX6GFX7GFX10 :
1289  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1290            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1291            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1292  AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
1293
1294def isGFX7Only :
1295  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1296  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
1297
1298def isGFX7GFX10 :
1299  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1300            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1301  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
1302
1303def isGFX7GFX8GFX9 :
1304  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1305            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1306            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1307  AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
1308
1309def isGFX6GFX7GFX8GFX9 :
1310  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1311            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1312            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1313            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1314  AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
1315
1316def isGFX6GFX7GFX8GFX9NotGFX90A :
1317  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1318            "(Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1319            " Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1320            " Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1321            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1322  AssemblerPredicate<(all_of (not FeatureGFX10Insts), (not FeatureGFX90AInsts))>;
1323
1324def isGFX7Plus :
1325  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1326  AssemblerPredicate<(all_of FeatureCIInsts)>;
1327
1328def isGFX8Plus :
1329  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1330  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1331
1332def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1333                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1334  AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1335
1336def isGFX9Plus :
1337  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1338  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1339
1340def isGFX9Only : Predicate <
1341  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1342  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1343
1344def isGCN3ExcludingGFX90A :
1345  Predicate<"Subtarget->isGCN3Encoding() && !Subtarget->hasGFX90AInsts()">,
1346  AssemblerPredicate<(all_of FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1347
1348def isGFX90APlus :
1349  Predicate<"Subtarget->hasGFX90AInsts()">,
1350  AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1351
1352def isNotGFX90APlus :
1353  Predicate<"!Subtarget->hasGFX90AInsts()">,
1354  AssemblerPredicate<(all_of (not FeatureGFX90AInsts))>;
1355
1356def isGFX8GFX9NotGFX90A :
1357  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1358            "(Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1359            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1360  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1361
1362def isGFX90AOnly :
1363  Predicate<"Subtarget->hasGFX90AInsts() && !Subtarget->hasGFX940Insts()">,
1364  AssemblerPredicate<(all_of FeatureGFX90AInsts, (not FeatureGFX940Insts))>;
1365
1366def isGFX908orGFX90A :
1367  Predicate<"Subtarget->hasMAIInsts() && !Subtarget->hasGFX940Insts()">,
1368  AssemblerPredicate<(all_of FeatureMAIInsts, (not FeatureGFX940Insts))>;
1369
1370def isGFX940Plus :
1371  Predicate<"Subtarget->hasGFX940Insts()">,
1372  AssemblerPredicate<(all_of FeatureGFX940Insts)>;
1373
1374def isGFX8GFX9NotGFX940 :
1375  Predicate<"!Subtarget->hasGFX940Insts() &&"
1376            "(Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1377            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1378  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding, (not FeatureGFX940Insts))>;
1379
1380def isGFX8GFX9 :
1381  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1382            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1383  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1384
1385def isGFX10Plus :
1386  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1387  AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1388
1389def isGFX10Before1030 :
1390  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 &&"
1391            "!Subtarget->hasGFX10_3Insts()">,
1392  AssemblerPredicate<(all_of FeatureGFX10Insts,(not FeatureGFX10_3Insts))>;
1393
1394def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1395  AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1396
1397def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1398  AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1399def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1400  AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1401def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1402  AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1403def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1404  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1405
1406def HasFlatScratchSTMode : Predicate<"Subtarget->hasFlatScratchSTMode()">,
1407  AssemblerPredicate<(any_of FeatureGFX10_3Insts, FeatureGFX940Insts)>;
1408def HasFlatScratchSVSMode : Predicate<"Subtarget->hasFlatScratchSVSMode()">,
1409  AssemblerPredicate<(any_of FeatureGFX940Insts)>;
1410
1411def HasGFX10_AEncoding : Predicate<"Subtarget->hasGFX10_AEncoding()">,
1412  AssemblerPredicate<(all_of FeatureGFX10_AEncoding)>;
1413
1414def HasGFX10_BEncoding : Predicate<"Subtarget->hasGFX10_BEncoding()">,
1415  AssemblerPredicate<(all_of FeatureGFX10_BEncoding)>;
1416
1417def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1418  AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1419def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1420  AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1421
1422def D16PreservesUnusedBits :
1423  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1424  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1425
1426def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1427def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1428
1429def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1430  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1431
1432def HasLDSFPAtomicAdd : Predicate<"Subtarget->hasLDSFPAtomicAdd()">,
1433  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1434
1435def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1436  AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1437
1438def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1439
1440def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1441  AssemblerPredicate<(all_of Feature16BitInsts)>;
1442def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1443  AssemblerPredicate<(all_of FeatureVOP3P)>;
1444
1445def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
1446def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
1447
1448def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1449  AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1450
1451def HasSDWA9 :
1452  Predicate<"Subtarget->hasSDWA()">,
1453  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1454
1455def HasSDWA10 :
1456  Predicate<"Subtarget->hasSDWA()">,
1457  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1458
1459def HasDPP : Predicate<"Subtarget->hasDPP()">,
1460  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1461
1462def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1463  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1464
1465def Has64BitDPP : Predicate<"Subtarget->has64BitDPP()">,
1466  AssemblerPredicate<(all_of Feature64BitDPP)>;
1467
1468def HasPackedFP32Ops : Predicate<"Subtarget->hasPackedFP32Ops()">,
1469  AssemblerPredicate<(all_of FeaturePackedFP32Ops)>;
1470
1471def HasFmaakFmamkF32Insts :
1472  Predicate<"Subtarget->hasFmaakFmamkF32Insts()">,
1473  AssemblerPredicate<(any_of FeatureGFX10Insts, FeatureGFX940Insts)>;
1474
1475def HasImageInsts : Predicate<"Subtarget->hasImageInsts()">,
1476  AssemblerPredicate<(all_of FeatureImageInsts)>;
1477
1478def HasExtendedImageInsts : Predicate<"Subtarget->hasExtendedImageInsts()">,
1479  AssemblerPredicate<(all_of FeatureExtendedImageInsts)>;
1480
1481def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1482  AssemblerPredicate<(all_of FeatureR128A16)>;
1483
1484def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1485  AssemblerPredicate<(all_of FeatureGFX10A16)>;
1486
1487def HasG16 : Predicate<"Subtarget->hasG16()">,
1488  AssemblerPredicate<(all_of FeatureG16)>;
1489
1490def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1491  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1492
1493def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1494  AssemblerPredicate<(all_of FeatureIntClamp)>;
1495
1496def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1497  AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1498
1499def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1500  AssemblerPredicate<(all_of FeatureScalarStores)>;
1501
1502def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1503  AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1504
1505def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1506  AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1507
1508def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1509  AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1510
1511def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1512def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1513def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1514                      AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1515def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1516                AssemblerPredicate<(all_of FeatureMovrel)>;
1517
1518def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1519  AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1520
1521def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1522  AssemblerPredicate<(all_of FeatureDLInsts)>;
1523
1524def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1525  AssemblerPredicate<(all_of FeatureDot1Insts)>;
1526
1527def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1528  AssemblerPredicate<(all_of FeatureDot2Insts)>;
1529
1530def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1531  AssemblerPredicate<(all_of FeatureDot3Insts)>;
1532
1533def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1534  AssemblerPredicate<(all_of FeatureDot4Insts)>;
1535
1536def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1537  AssemblerPredicate<(all_of FeatureDot5Insts)>;
1538
1539def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1540  AssemblerPredicate<(all_of FeatureDot6Insts)>;
1541
1542def HasDot7Insts : Predicate<"Subtarget->hasDot7Insts()">,
1543  AssemblerPredicate<(all_of FeatureDot7Insts)>;
1544
1545def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">,
1546  AssemblerPredicate<(all_of FeatureGetWaveIdInst)>;
1547
1548def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1549  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1550
1551def HasSMemRealTime : Predicate<"Subtarget->hasSMemRealTime()">,
1552  AssemblerPredicate<(all_of FeatureSMemRealTime)>;
1553
1554def HasSMemTimeInst : Predicate<"Subtarget->hasSMemTimeInst()">,
1555  AssemblerPredicate<(all_of FeatureSMemTimeInst)>;
1556
1557def HasShaderCyclesRegister : Predicate<"Subtarget->hasShaderCyclesRegister()">,
1558  AssemblerPredicate<(all_of FeatureShaderCyclesRegister)>;
1559
1560def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1561  AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1562
1563def HasMadMacF32Insts : Predicate<"Subtarget->hasMadMacF32Insts()">,
1564  AssemblerPredicate<(all_of FeatureMadMacF32Insts)>;
1565
1566def HasFmaLegacy32 : Predicate<"Subtarget->hasGFX10_3Insts()">,
1567  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1568
1569def HasAtomicFaddRtnInsts : Predicate<"Subtarget->hasAtomicFaddRtnInsts()">,
1570  AssemblerPredicate<(all_of FeatureAtomicFaddRtnInsts)>;
1571def HasAtomicFaddNoRtnInsts : Predicate<"Subtarget->hasAtomicFaddNoRtnInsts()">,
1572  AssemblerPredicate<(all_of FeatureAtomicFaddNoRtnInsts)>;
1573def HasAtomicPkFaddNoRtnInsts
1574  : Predicate<"Subtarget->hasAtomicPkFaddNoRtnInsts()">,
1575  AssemblerPredicate<(all_of FeatureAtomicPkFaddNoRtnInsts)>;
1576
1577def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
1578  AssemblerPredicate<(all_of FeatureDsSrc2Insts)>;
1579
1580def EnableLateCFGStructurize : Predicate<
1581  "EnableLateStructurizeCFG">;
1582
1583def EnableFlatScratch : Predicate<"Subtarget->enableFlatScratch()">;
1584
1585def DisableFlatScratch : Predicate<"!Subtarget->enableFlatScratch()">;
1586
1587def HasUnalignedAccessMode : Predicate<"Subtarget->hasUnalignedAccessMode()">,
1588  AssemblerPredicate<(all_of FeatureUnalignedAccessMode)>;
1589
1590// Include AMDGPU TD files
1591include "SISchedule.td"
1592include "GCNProcessors.td"
1593include "AMDGPUInstrInfo.td"
1594include "SIRegisterInfo.td"
1595include "AMDGPURegisterBanks.td"
1596include "AMDGPUInstructions.td"
1597include "SIInstrInfo.td"
1598include "AMDGPUCallingConv.td"
1599include "AMDGPUSearchableTables.td"
1600