1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13class BoolToList<bit Value> {
14  list<int> ret = !if(Value, [1]<int>, []<int>);
15}
16
17//===------------------------------------------------------------===//
18// Subtarget Features (device properties)
19//===------------------------------------------------------------===//
20
21def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
22  "FastFMAF32",
23  "true",
24  "Assuming f32 fma is at least as fast as mul + add"
25>;
26
27def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
28  "MIMG_R128",
29  "true",
30  "Support 128-bit texture resources"
31>;
32
33def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
34  "HalfRate64Ops",
35  "true",
36  "Most fp64 instructions are half rate instead of quarter"
37>;
38
39def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
40  "FlatAddressSpace",
41  "true",
42  "Support flat address space"
43>;
44
45def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
46  "FlatInstOffsets",
47  "true",
48  "Flat instructions have immediate offset addressing mode"
49>;
50
51def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
52  "FlatGlobalInsts",
53  "true",
54  "Have global_* flat memory instructions"
55>;
56
57def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
58  "FlatScratchInsts",
59  "true",
60  "Have scratch_* flat memory instructions"
61>;
62
63def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
64  "ScalarFlatScratchInsts",
65  "true",
66  "Have s_scratch_* flat memory instructions"
67>;
68
69def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
70  "AddNoCarryInsts",
71  "true",
72  "Have VALU add/sub instructions without carry out"
73>;
74
75def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
76  "UnalignedBufferAccess",
77  "true",
78  "Support unaligned global loads and stores"
79>;
80
81def FeatureTrapHandler: SubtargetFeature<"trap-handler",
82  "TrapHandler",
83  "true",
84  "Trap handler support"
85>;
86
87def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
88  "UnalignedScratchAccess",
89  "true",
90  "Support unaligned scratch loads and stores"
91>;
92
93def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
94  "HasApertureRegs",
95  "true",
96  "Has Memory Aperture Base and Size Registers"
97>;
98
99def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
100  "HasMadMixInsts",
101  "true",
102  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
103>;
104
105def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
106  "HasFmaMixInsts",
107  "true",
108  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
109>;
110
111def FeatureDoesNotSupportXNACK : SubtargetFeature<"no-xnack-support",
112  "DoesNotSupportXNACK",
113  "true",
114  "Hardware does not support XNACK"
115>;
116
117// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
118// XNACK. The current default kernel driver setting is:
119// - graphics ring: XNACK disabled
120// - compute ring: XNACK enabled
121//
122// If XNACK is enabled, the VMEM latency can be worse.
123// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
124def FeatureXNACK : SubtargetFeature<"xnack",
125  "EnableXNACK",
126  "true",
127  "Enable XNACK support"
128>;
129
130def FeatureCuMode : SubtargetFeature<"cumode",
131  "EnableCuMode",
132  "true",
133  "Enable CU wavefront execution mode"
134>;
135
136def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
137  "SGPRInitBug",
138  "true",
139  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
140>;
141
142def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
143  "LDSMisalignedBug",
144  "true",
145  "Some GFX10 bug with misaligned multi-dword LDS access in WGP mode"
146>;
147
148def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
149  "HasVcmpxPermlaneHazard",
150  "true",
151  "TODO: describe me"
152>;
153
154def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
155  "HasVMEMtoScalarWriteHazard",
156  "true",
157  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
158>;
159
160def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
161  "HasSMEMtoVectorWriteHazard",
162  "true",
163  "s_load_dword followed by v_cmp page faults"
164>;
165
166def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
167  "HasInstFwdPrefetchBug",
168  "true",
169  "S_INST_PREFETCH instruction causes shader to hang"
170>;
171
172def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
173  "HasVcmpxExecWARHazard",
174  "true",
175  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
176>;
177
178def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
179  "HasLdsBranchVmemWARHazard",
180  "true",
181  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
182>;
183
184def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
185  "HasNSAtoVMEMBug",
186  "true",
187  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
188>;
189
190def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
191  "HasFlatSegmentOffsetBug",
192  "true",
193  "GFX10 bug, inst_offset ignored in flat segment"
194>;
195
196class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
197  "ldsbankcount"#Value,
198  "LDSBankCount",
199  !cast<string>(Value),
200  "The number of LDS banks per compute unit."
201>;
202
203def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
204def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
205
206def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
207  "GCN3Encoding",
208  "true",
209  "Encoding format for VI"
210>;
211
212def FeatureCIInsts : SubtargetFeature<"ci-insts",
213  "CIInsts",
214  "true",
215  "Additional instructions for CI+"
216>;
217
218def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
219  "GFX8Insts",
220  "true",
221  "Additional instructions for GFX8+"
222>;
223
224def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
225  "GFX9Insts",
226  "true",
227  "Additional instructions for GFX9+"
228>;
229
230def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
231  "GFX10Insts",
232  "true",
233  "Additional instructions for GFX10+"
234>;
235
236def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
237  "GFX7GFX8GFX9Insts",
238  "true",
239  "Instructions shared in GFX7, GFX8, GFX9"
240>;
241
242def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
243  "HasSMemRealTime",
244  "true",
245  "Has s_memrealtime instruction"
246>;
247
248def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
249  "HasInv2PiInlineImm",
250  "true",
251  "Has 1 / (2 * pi) as inline immediate"
252>;
253
254def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
255  "Has16BitInsts",
256  "true",
257  "Has i16/f16 instructions"
258>;
259
260def FeatureVOP3P : SubtargetFeature<"vop3p",
261  "HasVOP3PInsts",
262  "true",
263  "Has VOP3P packed instructions"
264>;
265
266def FeatureMovrel : SubtargetFeature<"movrel",
267  "HasMovrel",
268  "true",
269  "Has v_movrel*_b32 instructions"
270>;
271
272def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
273  "HasVGPRIndexMode",
274  "true",
275  "Has VGPR mode register indexing"
276>;
277
278def FeatureScalarStores : SubtargetFeature<"scalar-stores",
279  "HasScalarStores",
280  "true",
281  "Has store scalar memory instructions"
282>;
283
284def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
285  "HasScalarAtomics",
286  "true",
287  "Has atomic scalar memory instructions"
288>;
289
290def FeatureSDWA : SubtargetFeature<"sdwa",
291  "HasSDWA",
292  "true",
293  "Support SDWA (Sub-DWORD Addressing) extension"
294>;
295
296def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
297  "HasSDWAOmod",
298  "true",
299  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
300>;
301
302def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
303  "HasSDWAScalar",
304  "true",
305  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
306>;
307
308def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
309  "HasSDWASdst",
310  "true",
311  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
312>;
313
314def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
315  "HasSDWAMac",
316  "true",
317  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
318>;
319
320def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
321  "HasSDWAOutModsVOPC",
322  "true",
323  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
324>;
325
326def FeatureDPP : SubtargetFeature<"dpp",
327  "HasDPP",
328  "true",
329  "Support DPP (Data Parallel Primitives) extension"
330>;
331
332// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
333def FeatureDPP8 : SubtargetFeature<"dpp8",
334  "HasDPP8",
335  "true",
336  "Support DPP8 (Data Parallel Primitives) extension"
337>;
338
339def FeatureR128A16 : SubtargetFeature<"r128-a16",
340  "HasR128A16",
341  "true",
342  "Support 16 bit coordindates/gradients/lod/clamp/mip types on gfx9"
343>;
344
345def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
346  "HasNSAEncoding",
347  "true",
348  "Support NSA encoding for image instructions"
349>;
350
351def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
352  "HasIntClamp",
353  "true",
354  "Support clamp for integer destination"
355>;
356
357def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
358  "HasUnpackedD16VMem",
359  "true",
360  "Has unpacked d16 vmem instructions"
361>;
362
363def FeatureDLInsts : SubtargetFeature<"dl-insts",
364  "HasDLInsts",
365  "true",
366  "Has v_fmac_f32 and v_xnor_b32 instructions"
367>;
368
369def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
370  "HasDot1Insts",
371  "true",
372  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
373>;
374
375def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
376  "HasDot2Insts",
377  "true",
378  "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
379>;
380
381def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
382  "HasDot5Insts",
383  "true",
384  "Has v_dot2c_f32_f16 instruction"
385>;
386
387def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
388  "HasDot6Insts",
389  "true",
390  "Has v_dot4c_i32_i8 instruction"
391>;
392
393def FeatureDoesNotSupportSRAMECC : SubtargetFeature<"no-sram-ecc-support",
394  "DoesNotSupportSRAMECC",
395  "true",
396  "Hardware does not support SRAM ECC"
397>;
398
399def FeatureSRAMECC : SubtargetFeature<"sram-ecc",
400  "EnableSRAMECC",
401  "true",
402  "Enable SRAM ECC"
403>;
404
405def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
406  "HasNoSdstCMPX",
407  "true",
408  "V_CMPX does not write VCC/SGPR in addition to EXEC"
409>;
410
411def FeatureVscnt : SubtargetFeature<"vscnt",
412  "HasVscnt",
413  "true",
414  "Has separate store vscnt counter"
415>;
416
417def FeatureRegisterBanking : SubtargetFeature<"register-banking",
418  "HasRegisterBanking",
419  "true",
420  "Has register banking"
421>;
422
423def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
424  "HasVOP3Literal",
425  "true",
426  "Can use one literal in VOP3"
427>;
428
429def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
430  "HasNoDataDepHazard",
431  "true",
432  "Does not need SW waitstates"
433>;
434
435//===------------------------------------------------------------===//
436// Subtarget Features (options and debugging)
437//===------------------------------------------------------------===//
438
439// Denormal handling for fp64 and fp16 is controlled by the same
440// config register when fp16 supported.
441// TODO: Do we need a separate f16 setting when not legal?
442def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
443  "FP64FP16Denormals",
444  "true",
445  "Enable double and half precision denormal handling",
446  [FeatureFP64]
447>;
448
449def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
450  "FP64FP16Denormals",
451  "true",
452  "Enable double and half precision denormal handling",
453  [FeatureFP64, FeatureFP64FP16Denormals]
454>;
455
456def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
457  "FP64FP16Denormals",
458  "true",
459  "Enable half precision denormal handling",
460  [FeatureFP64FP16Denormals]
461>;
462
463def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
464  "FPExceptions",
465  "true",
466  "Enable floating point exceptions"
467>;
468
469class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
470  "max-private-element-size-"#size,
471  "MaxPrivateElementSize",
472  !cast<string>(size),
473  "Maximum private access size may be "#size
474>;
475
476def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
477def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
478def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
479
480def FeatureDumpCode : SubtargetFeature <"DumpCode",
481  "DumpCode",
482  "true",
483  "Dump MachineInstrs in the CodeEmitter"
484>;
485
486def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
487  "DumpCode",
488  "true",
489  "Dump MachineInstrs in the CodeEmitter"
490>;
491
492// XXX - This should probably be removed once enabled by default
493def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
494  "EnableLoadStoreOpt",
495  "true",
496  "Enable SI load/store optimizer pass"
497>;
498
499// Performance debugging feature. Allow using DS instruction immediate
500// offsets even if the base pointer can't be proven to be base. On SI,
501// base pointer values that won't give the same result as a 16-bit add
502// are not safe to fold, but this will override the conservative test
503// for the base pointer.
504def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
505  "unsafe-ds-offset-folding",
506  "EnableUnsafeDSOffsetFolding",
507  "true",
508  "Force using DS instruction immediate offsets on SI"
509>;
510
511def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
512  "EnableSIScheduler",
513  "true",
514  "Enable SI Machine Scheduler"
515>;
516
517def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
518  "EnableDS128",
519  "true",
520  "Use ds_{read|write}_b128"
521>;
522
523// Sparse texture support requires that all result registers are zeroed when
524// PRTStrictNull is set to true. This feature is turned on for all architectures
525// but is enabled as a feature in case there are situations where PRTStrictNull
526// is disabled by the driver.
527def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
528  "EnablePRTStrictNull",
529  "true",
530  "Enable zeroing of result registers for sparse texture fetches"
531>;
532
533// Unless +-flat-for-global is specified, turn on FlatForGlobal for
534// all OS-es on VI and newer hardware to avoid assertion failures due
535// to missing ADDR64 variants of MUBUF instructions.
536// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
537// instructions.
538
539def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
540  "FlatForGlobal",
541  "true",
542  "Force to generate flat instruction for global"
543>;
544
545def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
546  "auto-waitcnt-before-barrier",
547  "AutoWaitcntBeforeBarrier",
548  "true",
549  "Hardware automatically inserts waitcnt before barrier"
550>;
551
552def FeatureCodeObjectV3 : SubtargetFeature <
553  "code-object-v3",
554  "CodeObjectV3",
555  "true",
556  "Generate code object version 3"
557>;
558
559def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
560  "HasTrigReducedRange",
561  "true",
562  "Requires use of fract on arguments to trig instructions"
563>;
564
565// Dummy feature used to disable assembler instructions.
566def FeatureDisable : SubtargetFeature<"",
567  "FeatureDisable","true",
568  "Dummy feature to disable assembler instructions"
569>;
570
571class GCNSubtargetFeatureGeneration <string Value,
572                                     string FeatureName,
573                                     list<SubtargetFeature> Implies> :
574        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
575
576def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
577    "southern-islands",
578  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
579  FeatureWavefrontSize64,
580  FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange,
581  FeatureDoesNotSupportSRAMECC, FeatureDoesNotSupportXNACK]
582>;
583
584def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
585    "sea-islands",
586  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
587  FeatureWavefrontSize64, FeatureFlatAddressSpace,
588  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
589  FeatureGFX7GFX8GFX9Insts, FeatureDoesNotSupportSRAMECC]
590>;
591
592def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
593  "volcanic-islands",
594  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
595   FeatureWavefrontSize64, FeatureFlatAddressSpace,
596   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
597   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
598   FeatureScalarStores, FeatureInv2PiInlineImm,
599   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
600   FeatureIntClamp, FeatureTrigReducedRange, FeatureDoesNotSupportSRAMECC,
601   FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts
602  ]
603>;
604
605def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
606  "gfx9",
607  [FeatureFP64, FeatureLocalMemorySize65536,
608   FeatureWavefrontSize64, FeatureFlatAddressSpace,
609   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
610   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
611   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
612   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
613   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
614   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
615   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
616   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16
617  ]
618>;
619
620def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
621  "gfx10",
622  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
623   FeatureFlatAddressSpace,
624   FeatureCIInsts, Feature16BitInsts,
625   FeatureSMemRealTime, FeatureInv2PiInlineImm,
626   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
627   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
628   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
629   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
630   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
631   FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
632   FeatureVOP3Literal, FeatureDPP8, FeatureNoDataDepHazard,
633   FeatureDoesNotSupportSRAMECC
634  ]
635>;
636
637class FeatureSet<list<SubtargetFeature> Features_> {
638  list<SubtargetFeature> Features = Features_;
639}
640
641def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
642   FeatureFastFMAF32,
643   HalfRate64Ops,
644   FeatureLDSBankCount32,
645   FeatureDoesNotSupportXNACK,
646   FeatureCodeObjectV3]>;
647
648def FeatureISAVersion6_0_1 : FeatureSet<
649  [FeatureSouthernIslands,
650   FeatureLDSBankCount32,
651   FeatureDoesNotSupportXNACK,
652   FeatureCodeObjectV3]>;
653
654def FeatureISAVersion7_0_0 : FeatureSet<
655  [FeatureSeaIslands,
656   FeatureLDSBankCount32,
657   FeatureDoesNotSupportXNACK,
658   FeatureCodeObjectV3]>;
659
660def FeatureISAVersion7_0_1 : FeatureSet<
661  [FeatureSeaIslands,
662   HalfRate64Ops,
663   FeatureLDSBankCount32,
664   FeatureFastFMAF32,
665   FeatureDoesNotSupportXNACK,
666   FeatureCodeObjectV3]>;
667
668def FeatureISAVersion7_0_2 : FeatureSet<
669  [FeatureSeaIslands,
670   FeatureLDSBankCount16,
671   FeatureFastFMAF32,
672   FeatureDoesNotSupportXNACK,
673   FeatureCodeObjectV3]>;
674
675def FeatureISAVersion7_0_3 : FeatureSet<
676  [FeatureSeaIslands,
677   FeatureLDSBankCount16,
678   FeatureDoesNotSupportXNACK,
679   FeatureCodeObjectV3]>;
680
681def FeatureISAVersion7_0_4 : FeatureSet<
682  [FeatureSeaIslands,
683   FeatureLDSBankCount32,
684   FeatureDoesNotSupportXNACK,
685   FeatureCodeObjectV3]>;
686
687def FeatureISAVersion8_0_1 : FeatureSet<
688  [FeatureVolcanicIslands,
689   FeatureFastFMAF32,
690   HalfRate64Ops,
691   FeatureLDSBankCount32,
692   FeatureXNACK,
693   FeatureUnpackedD16VMem,
694   FeatureCodeObjectV3]>;
695
696def FeatureISAVersion8_0_2 : FeatureSet<
697  [FeatureVolcanicIslands,
698   FeatureLDSBankCount32,
699   FeatureSGPRInitBug,
700   FeatureUnpackedD16VMem,
701   FeatureDoesNotSupportXNACK,
702   FeatureCodeObjectV3]>;
703
704def FeatureISAVersion8_0_3 : FeatureSet<
705  [FeatureVolcanicIslands,
706   FeatureLDSBankCount32,
707   FeatureUnpackedD16VMem,
708   FeatureDoesNotSupportXNACK,
709   FeatureCodeObjectV3]>;
710
711def FeatureISAVersion8_1_0 : FeatureSet<
712  [FeatureVolcanicIslands,
713   FeatureLDSBankCount16,
714   FeatureXNACK,
715   FeatureCodeObjectV3]>;
716
717def FeatureISAVersion9_0_0 : FeatureSet<
718  [FeatureGFX9,
719   FeatureMadMixInsts,
720   FeatureLDSBankCount32,
721   FeatureCodeObjectV3,
722   FeatureDoesNotSupportXNACK,
723   FeatureDoesNotSupportSRAMECC]>;
724
725def FeatureISAVersion9_0_2 : FeatureSet<
726  [FeatureGFX9,
727   FeatureMadMixInsts,
728   FeatureLDSBankCount32,
729   FeatureXNACK,
730   FeatureDoesNotSupportSRAMECC,
731   FeatureCodeObjectV3]>;
732
733def FeatureISAVersion9_0_4 : FeatureSet<
734  [FeatureGFX9,
735   FeatureLDSBankCount32,
736   FeatureFmaMixInsts,
737   FeatureDoesNotSupportXNACK,
738   FeatureDoesNotSupportSRAMECC,
739   FeatureCodeObjectV3]>;
740
741def FeatureISAVersion9_0_6 : FeatureSet<
742  [FeatureGFX9,
743   HalfRate64Ops,
744   FeatureFmaMixInsts,
745   FeatureLDSBankCount32,
746   FeatureDLInsts,
747   FeatureDot1Insts,
748   FeatureDot2Insts,
749   FeatureDoesNotSupportXNACK,
750   FeatureCodeObjectV3]>;
751
752def FeatureISAVersion9_0_9 : FeatureSet<
753  [FeatureGFX9,
754   FeatureMadMixInsts,
755   FeatureLDSBankCount32,
756   FeatureXNACK,
757   FeatureCodeObjectV3]>;
758
759// TODO: Organize more features into groups.
760def FeatureGroup {
761  // Bugs present on gfx10.1.
762  list<SubtargetFeature> GFX10_1_Bugs = [
763    FeatureVcmpxPermlaneHazard,
764    FeatureVMEMtoScalarWriteHazard,
765    FeatureSMEMtoVectorWriteHazard,
766    FeatureInstFwdPrefetchBug,
767    FeatureVcmpxExecWARHazard,
768    FeatureLdsBranchVmemWARHazard,
769    FeatureNSAtoVMEMBug,
770    FeatureFlatSegmentOffsetBug
771   ];
772}
773
774def FeatureISAVersion10_1_0 : FeatureSet<
775  !listconcat(FeatureGroup.GFX10_1_Bugs,
776    [FeatureGFX10,
777     FeatureLDSBankCount32,
778     FeatureDLInsts,
779     FeatureNSAEncoding,
780     FeatureWavefrontSize32,
781     FeatureScalarStores,
782     FeatureScalarAtomics,
783     FeatureScalarFlatScratchInsts,
784     FeatureLdsMisalignedBug,
785     FeatureDoesNotSupportXNACK,
786     FeatureCodeObjectV3])>;
787
788def FeatureISAVersion10_1_1 : FeatureSet<
789  !listconcat(FeatureGroup.GFX10_1_Bugs,
790    [FeatureGFX10,
791     FeatureLDSBankCount32,
792     FeatureDLInsts,
793     FeatureDot1Insts,
794     FeatureDot2Insts,
795     FeatureDot5Insts,
796     FeatureDot6Insts,
797     FeatureNSAEncoding,
798     FeatureWavefrontSize32,
799     FeatureScalarStores,
800     FeatureScalarAtomics,
801     FeatureScalarFlatScratchInsts,
802     FeatureDoesNotSupportXNACK,
803     FeatureCodeObjectV3])>;
804
805def FeatureISAVersion10_1_2 : FeatureSet<
806  !listconcat(FeatureGroup.GFX10_1_Bugs,
807    [FeatureGFX10,
808     FeatureLDSBankCount32,
809     FeatureDLInsts,
810     FeatureDot1Insts,
811     FeatureDot2Insts,
812     FeatureDot5Insts,
813     FeatureDot6Insts,
814     FeatureNSAEncoding,
815     FeatureWavefrontSize32,
816     FeatureScalarStores,
817     FeatureScalarAtomics,
818     FeatureScalarFlatScratchInsts,
819     FeatureLdsMisalignedBug,
820     FeatureDoesNotSupportXNACK,
821     FeatureCodeObjectV3])>;
822
823//===----------------------------------------------------------------------===//
824
825def AMDGPUInstrInfo : InstrInfo {
826  let guessInstructionProperties = 1;
827  let noNamedPositionallyEncodedOperands = 1;
828}
829
830def AMDGPUAsmParser : AsmParser {
831  // Some of the R600 registers have the same name, so this crashes.
832  // For example T0_XYZW and T0_XY both have the asm name T0.
833  let ShouldEmitMatchRegisterName = 0;
834}
835
836def AMDGPUAsmWriter : AsmWriter {
837  int PassSubtarget = 1;
838}
839
840def AMDGPUAsmVariants {
841  string Default = "Default";
842  int Default_ID = 0;
843  string VOP3 = "VOP3";
844  int VOP3_ID = 1;
845  string SDWA = "SDWA";
846  int SDWA_ID = 2;
847  string SDWA9 = "SDWA9";
848  int SDWA9_ID = 3;
849  string DPP = "DPP";
850  int DPP_ID = 4;
851  string Disable = "Disable";
852  int Disable_ID = 5;
853}
854
855def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
856  let Variant = AMDGPUAsmVariants.Default_ID;
857  let Name = AMDGPUAsmVariants.Default;
858}
859
860def VOP3AsmParserVariant : AsmParserVariant {
861  let Variant = AMDGPUAsmVariants.VOP3_ID;
862  let Name = AMDGPUAsmVariants.VOP3;
863}
864
865def SDWAAsmParserVariant : AsmParserVariant {
866  let Variant = AMDGPUAsmVariants.SDWA_ID;
867  let Name = AMDGPUAsmVariants.SDWA;
868}
869
870def SDWA9AsmParserVariant : AsmParserVariant {
871  let Variant = AMDGPUAsmVariants.SDWA9_ID;
872  let Name = AMDGPUAsmVariants.SDWA9;
873}
874
875
876def DPPAsmParserVariant : AsmParserVariant {
877  let Variant = AMDGPUAsmVariants.DPP_ID;
878  let Name = AMDGPUAsmVariants.DPP;
879}
880
881def AMDGPU : Target {
882  // Pull in Instruction Info:
883  let InstructionSet = AMDGPUInstrInfo;
884  let AssemblyParsers = [AMDGPUAsmParser];
885  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
886                                VOP3AsmParserVariant,
887                                SDWAAsmParserVariant,
888                                SDWA9AsmParserVariant,
889                                DPPAsmParserVariant];
890  let AssemblyWriters = [AMDGPUAsmWriter];
891  let AllowRegisterRenaming = 1;
892}
893
894// Dummy Instruction itineraries for pseudo instructions
895def ALU_NULL : FuncUnit;
896def NullALU : InstrItinClass;
897
898//===----------------------------------------------------------------------===//
899// Predicate helper class
900//===----------------------------------------------------------------------===//
901
902def isGFX6 :
903  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
904  AssemblerPredicate<"FeatureSouthernIslands">;
905
906def isGFX6GFX7 :
907  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
908            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
909  AssemblerPredicate<"!FeatureGCN3Encoding,!FeatureGFX10Insts">;
910
911def isGFX6GFX7GFX10 :
912  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
913            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
914            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
915  AssemblerPredicate<"!FeatureGCN3Encoding">;
916
917def isGFX7Only :
918  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
919  AssemblerPredicate<"!FeatureGCN3Encoding,FeatureCIInsts,!FeatureGFX10Insts">;
920
921def isGFX7GFX10 :
922  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
923            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
924  AssemblerPredicate<"!FeatureGCN3Encoding,FeatureCIInsts">;
925
926def isGFX7GFX8GFX9 :
927  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
928            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
929            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
930  AssemblerPredicate<"FeatureGFX7GFX8GFX9Insts">;
931
932def isGFX6GFX7GFX8GFX9 :
933  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
934            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
935            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
936            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
937  AssemblerPredicate<"!FeatureGFX10Insts">;
938
939def isGFX7Plus :
940  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
941  AssemblerPredicate<"FeatureCIInsts">;
942
943def isGFX8Plus :
944  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
945  AssemblerPredicate<"FeatureGFX8Insts">;
946
947def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
948                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
949  AssemblerPredicate <"FeatureVolcanicIslands">;
950
951def isGFX9Plus :
952  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
953  AssemblerPredicate<"FeatureGFX9Insts">;
954
955def isGFX9Only : Predicate <
956  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
957  AssemblerPredicate<"FeatureGCN3Encoding,FeatureGFX9Insts">;
958
959def isGFX8GFX9 :
960  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
961            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
962  AssemblerPredicate<"FeatureGFX8Insts,FeatureGCN3Encoding">;
963
964def isGFX10Plus :
965  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
966  AssemblerPredicate<"FeatureGFX10Insts">;
967
968def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
969  AssemblerPredicate<"FeatureFlatAddressSpace">;
970
971def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
972  AssemblerPredicate<"FeatureFlatGlobalInsts">;
973def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
974  AssemblerPredicate<"FeatureFlatScratchInsts">;
975def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
976  AssemblerPredicate<"FeatureScalarFlatScratchInsts">;
977def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
978  AssemblerPredicate<"FeatureGFX9Insts">;
979
980def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
981  AssemblerPredicate<"FeatureUnpackedD16VMem">;
982def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
983  AssemblerPredicate<"!FeatureUnpackedD16VMem">;
984
985def D16PreservesUnusedBits :
986  Predicate<"Subtarget->d16PreservesUnusedBits()">,
987  AssemblerPredicate<"FeatureGFX9Insts,!FeatureSRAMECC">;
988
989def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
990def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
991
992def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
993  AssemblerPredicate<"FeatureGFX9Insts">;
994
995def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
996  AssemblerPredicate<"FeatureAddNoCarryInsts">;
997
998def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
999
1000def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1001  AssemblerPredicate<"Feature16BitInsts">;
1002def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1003  AssemblerPredicate<"FeatureVOP3P">;
1004
1005def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1006  AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
1007
1008def HasSDWA9 :
1009  Predicate<"Subtarget->hasSDWA()">,
1010  AssemblerPredicate<"FeatureGCN3Encoding,FeatureGFX9Insts,FeatureSDWA">;
1011
1012def HasSDWA10 :
1013  Predicate<"Subtarget->hasSDWA()">,
1014  AssemblerPredicate<"!FeatureGCN3Encoding,FeatureGFX10Insts,FeatureSDWA">;
1015
1016def HasDPP : Predicate<"Subtarget->hasDPP()">,
1017  AssemblerPredicate<"FeatureGCN3Encoding,FeatureDPP">;
1018
1019def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1020  AssemblerPredicate<"!FeatureGCN3Encoding,FeatureGFX10Insts,FeatureDPP8">;
1021
1022def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1023  AssemblerPredicate<"FeatureR128A16">;
1024
1025def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1026  AssemblerPredicate<"!FeatureGCN3Encoding,FeatureGFX10Insts,FeatureDPP">;
1027
1028def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1029  AssemblerPredicate<"FeatureIntClamp">;
1030
1031def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1032  AssemblerPredicate<"FeatureMadMixInsts">;
1033
1034def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1035  AssemblerPredicate<"FeatureScalarStores">;
1036
1037def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1038  AssemblerPredicate<"FeatureScalarAtomics">;
1039
1040def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1041  AssemblerPredicate<"FeatureNoSdstCMPX">;
1042
1043def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1044  AssemblerPredicate<"!FeatureNoSdstCMPX">;
1045
1046def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1047def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1048def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1049                      AssemblerPredicate<"FeatureVGPRIndexMode">;
1050def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1051                AssemblerPredicate<"FeatureMovrel">;
1052
1053def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1054  AssemblerPredicate<"FeatureFmaMixInsts">;
1055
1056def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1057  AssemblerPredicate<"FeatureDLInsts">;
1058
1059def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1060  AssemblerPredicate<"FeatureDot1Insts">;
1061
1062def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1063  AssemblerPredicate<"FeatureDot2Insts">;
1064
1065def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1066  AssemblerPredicate<"FeatureDot5Insts">;
1067
1068def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1069  AssemblerPredicate<"FeatureDot6Insts">;
1070
1071def EnableLateCFGStructurize : Predicate<
1072  "EnableLateStructurizeCFG">;
1073
1074// Include AMDGPU TD files
1075include "SISchedule.td"
1076include "GCNProcessors.td"
1077include "AMDGPUInstrInfo.td"
1078include "AMDGPURegisterInfo.td"
1079include "AMDGPURegisterBanks.td"
1080include "AMDGPUInstructions.td"
1081include "SIInstrInfo.td"
1082include "AMDGPUCallingConv.td"
1083include "AMDGPUSearchableTables.td"
1084