1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===------------------------------------------------------------===//
9
10include "llvm/Target/Target.td"
11
12//===------------------------------------------------------------===//
13// Subtarget Features (device properties)
14//===------------------------------------------------------------===//
15
16def FeatureFP64 : SubtargetFeature<"fp64",
17  "FP64",
18  "true",
19  "Enable double precision operations"
20>;
21
22def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
23  "FastFMAF32",
24  "true",
25  "Assuming f32 fma is at least as fast as mul + add"
26>;
27
28def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
29  "HalfRate64Ops",
30  "true",
31  "Most fp64 instructions are half rate instead of quarter"
32>;
33
34def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
35  "R600ALUInst",
36  "false",
37  "Older version of ALU instructions encoding"
38>;
39
40def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
41  "HasVertexCache",
42  "true",
43  "Specify use of dedicated vertex cache"
44>;
45
46def FeatureCaymanISA : SubtargetFeature<"caymanISA",
47  "CaymanISA",
48  "true",
49  "Use Cayman ISA"
50>;
51
52def FeatureCFALUBug : SubtargetFeature<"cfalubug",
53  "CFALUBug",
54  "true",
55  "GPU has CF_ALU bug"
56>;
57
58def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
59  "FlatAddressSpace",
60  "true",
61  "Support flat address space"
62>;
63
64def FeatureXNACK : SubtargetFeature<"xnack",
65  "EnableXNACK",
66  "true",
67  "Enable XNACK support"
68>;
69
70def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
71  "SGPRInitBug",
72  "true",
73  "VI SGPR initilization bug requiring a fixed SGPR allocation size"
74>;
75
76class SubtargetFeatureFetchLimit <string Value> :
77                          SubtargetFeature <"fetch"#Value,
78  "TexVTXClauseSize",
79  Value,
80  "Limit the maximum number of fetches in a clause to "#Value
81>;
82
83def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
84def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
85
86class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
87  "wavefrontsize"#Value,
88  "WavefrontSize",
89  !cast<string>(Value),
90  "The number of threads per wavefront"
91>;
92
93def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
94def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
95def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
96
97class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
98  "ldsbankcount"#Value,
99  "LDSBankCount",
100  !cast<string>(Value),
101  "The number of LDS banks per compute unit."
102>;
103
104def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
105def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
106
107class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping>
108                                 : SubtargetFeature <
109  "isaver"#Major#"."#Minor#"."#Stepping,
110  "IsaVersion",
111  "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
112  "Instruction set version number"
113>;
114
115def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0>;
116def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1>;
117def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0>;
118def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1>;
119def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3>;
120
121class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
122  "localmemorysize"#Value,
123  "LocalMemorySize",
124  !cast<string>(Value),
125  "The size of local memory in bytes"
126>;
127
128def FeatureGCN : SubtargetFeature<"gcn",
129  "IsGCN",
130  "true",
131  "GCN or newer GPU"
132>;
133
134def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",
135  "GCN1Encoding",
136  "true",
137  "Encoding format for SI and CI"
138>;
139
140def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
141  "GCN3Encoding",
142  "true",
143  "Encoding format for VI"
144>;
145
146def FeatureCIInsts : SubtargetFeature<"ci-insts",
147  "CIInsts",
148  "true",
149  "Additional intstructions for CI+"
150>;
151
152//===------------------------------------------------------------===//
153// Subtarget Features (options and debugging)
154//===------------------------------------------------------------===//
155
156// Some instructions do not support denormals despite this flag. Using
157// fp32 denormals also causes instructions to run at the double
158// precision rate for the device.
159def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
160  "FP32Denormals",
161  "true",
162  "Enable single precision denormal handling"
163>;
164
165def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
166  "FP64Denormals",
167  "true",
168  "Enable double precision denormal handling",
169  [FeatureFP64]
170>;
171
172def FeatureEnableHugeScratchBuffer : SubtargetFeature<
173  "huge-scratch-buffer",
174  "EnableHugeScratchBuffer",
175  "true",
176  "Enable scratch buffer sizes greater than 128 GB"
177>;
178
179def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
180  "EnableVGPRSpilling",
181  "true",
182  "Enable spilling of VGPRs to scratch memory"
183>;
184
185def FeatureDumpCode : SubtargetFeature <"DumpCode",
186  "DumpCode",
187  "true",
188  "Dump MachineInstrs in the CodeEmitter"
189>;
190
191def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
192  "DumpCode",
193  "true",
194  "Dump MachineInstrs in the CodeEmitter"
195>;
196
197def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
198  "EnableIRStructurizer",
199  "false",
200  "Disable IR Structurizer"
201>;
202
203def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
204  "EnablePromoteAlloca",
205  "true",
206  "Enable promote alloca pass"
207>;
208
209// XXX - This should probably be removed once enabled by default
210def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
211  "EnableLoadStoreOpt",
212  "true",
213  "Enable SI load/store optimizer pass"
214>;
215
216// Performance debugging feature. Allow using DS instruction immediate
217// offsets even if the base pointer can't be proven to be base. On SI,
218// base pointer values that won't give the same result as a 16-bit add
219// are not safe to fold, but this will override the conservative test
220// for the base pointer.
221def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
222  "unsafe-ds-offset-folding",
223  "EnableUnsafeDSOffsetFolding",
224  "true",
225  "Force using DS instruction immediate offsets on SI"
226>;
227
228def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
229  "EnableIfCvt",
230  "false",
231  "Disable the if conversion pass"
232>;
233
234def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
235  "EnableSIScheduler",
236  "true",
237  "Enable SI Machine Scheduler"
238>;
239
240def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
241  "FlatForGlobal",
242  "true",
243  "Force to generate flat instruction for global"
244>;
245
246// Dummy feature used to disable assembler instructions.
247def FeatureDisable : SubtargetFeature<"",
248  "FeatureDisable","true",
249  "Dummy feature to disable assembler instructions"
250>;
251
252class SubtargetFeatureGeneration <string Value,
253                                  list<SubtargetFeature> Implies> :
254        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
255                          Value#" GPU generation", Implies>;
256
257def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
258def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
259def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
260
261def FeatureR600 : SubtargetFeatureGeneration<"R600",
262  [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]
263>;
264
265def FeatureR700 : SubtargetFeatureGeneration<"R700",
266  [FeatureFetchLimit16, FeatureLocalMemorySize0]
267>;
268
269def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
270  [FeatureFetchLimit16, FeatureLocalMemorySize32768]
271>;
272
273def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
274  [FeatureFetchLimit16, FeatureWavefrontSize64,
275   FeatureLocalMemorySize32768]
276>;
277
278def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
279  [FeatureFP64, FeatureLocalMemorySize32768,
280  FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
281  FeatureLDSBankCount32]
282>;
283
284def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
285  [FeatureFP64, FeatureLocalMemorySize65536,
286  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
287  FeatureGCN1Encoding, FeatureCIInsts]
288>;
289
290def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
291  [FeatureFP64, FeatureLocalMemorySize65536,
292   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
293   FeatureGCN3Encoding, FeatureCIInsts, FeatureLDSBankCount32]
294>;
295
296//===----------------------------------------------------------------------===//
297
298def AMDGPUInstrInfo : InstrInfo {
299  let guessInstructionProperties = 1;
300  let noNamedPositionallyEncodedOperands = 1;
301}
302
303def AMDGPUAsmParser : AsmParser {
304  // Some of the R600 registers have the same name, so this crashes.
305  // For example T0_XYZW and T0_XY both have the asm name T0.
306  let ShouldEmitMatchRegisterName = 0;
307}
308
309def AMDGPU : Target {
310  // Pull in Instruction Info:
311  let InstructionSet = AMDGPUInstrInfo;
312  let AssemblyParsers = [AMDGPUAsmParser];
313}
314
315// Dummy Instruction itineraries for pseudo instructions
316def ALU_NULL : FuncUnit;
317def NullALU : InstrItinClass;
318
319//===----------------------------------------------------------------------===//
320// Predicate helper class
321//===----------------------------------------------------------------------===//
322
323def TruePredicate : Predicate<"true">;
324
325def isSICI : Predicate<
326  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
327  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
328>, AssemblerPredicate<"FeatureGCN1Encoding">;
329
330def isVI : Predicate <
331  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
332  AssemblerPredicate<"FeatureGCN3Encoding">;
333
334def isCIVI : Predicate <
335  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS || "
336  "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS"
337>, AssemblerPredicate<"FeatureCIInsts">;
338
339def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">;
340
341class PredicateControl {
342  Predicate SubtargetPredicate;
343  Predicate SIAssemblerPredicate = isSICI;
344  Predicate VIAssemblerPredicate = isVI;
345  list<Predicate> AssemblerPredicates = [];
346  Predicate AssemblerPredicate = TruePredicate;
347  list<Predicate> OtherPredicates = [];
348  list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
349                                            AssemblerPredicates,
350                                            OtherPredicates);
351}
352
353// Include AMDGPU TD files
354include "R600Schedule.td"
355include "SISchedule.td"
356include "Processors.td"
357include "AMDGPUInstrInfo.td"
358include "AMDGPUIntrinsics.td"
359include "AMDGPURegisterInfo.td"
360include "AMDGPUInstructions.td"
361include "AMDGPUCallingConv.td"
362