1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21
22class BoolToList<bit Value> {
23  list<int> ret = !if(Value, [1]<int>, []<int>);
24}
25
26//===------------------------------------------------------------===//
27// Subtarget Features (device properties)
28//===------------------------------------------------------------===//
29
30def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
31  "FastFMAF32",
32  "true",
33  "Assuming f32 fma is at least as fast as mul + add"
34>;
35
36def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
37  "FastDenormalF32",
38  "true",
39  "Enabling denormals does not cause f32 instructions to run at f64 rates"
40>;
41
42def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
43  "MIMG_R128",
44  "true",
45  "Support 128-bit texture resources"
46>;
47
48def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
49  "HalfRate64Ops",
50  "true",
51  "Most fp64 instructions are half rate instead of quarter"
52>;
53
54def FullRate64Ops : SubtargetFeature<"full-rate-64-ops",
55  "FullRate64Ops",
56  "true",
57  "Most fp64 instructions are full rate"
58>;
59
60def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
61  "FlatAddressSpace",
62  "true",
63  "Support flat address space"
64>;
65
66def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
67  "FlatInstOffsets",
68  "true",
69  "Flat instructions have immediate offset addressing mode"
70>;
71
72def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
73  "FlatGlobalInsts",
74  "true",
75  "Have global_* flat memory instructions"
76>;
77
78def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
79  "FlatScratchInsts",
80  "true",
81  "Have scratch_* flat memory instructions"
82>;
83
84def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
85  "ScalarFlatScratchInsts",
86  "true",
87  "Have s_scratch_* flat memory instructions"
88>;
89
90def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
91  "AddNoCarryInsts",
92  "true",
93  "Have VALU add/sub instructions without carry out"
94>;
95
96def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
97  "UnalignedBufferAccess",
98  "true",
99  "Hardware supports unaligned global loads and stores"
100>;
101
102def FeatureTrapHandler: SubtargetFeature<"trap-handler",
103  "TrapHandler",
104  "true",
105  "Trap handler support"
106>;
107
108def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
109  "UnalignedScratchAccess",
110  "true",
111  "Support unaligned scratch loads and stores"
112>;
113
114def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access",
115  "UnalignedDSAccess",
116  "true",
117  "Hardware supports unaligned local and region loads and stores"
118>;
119
120def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
121  "HasApertureRegs",
122  "true",
123  "Has Memory Aperture Base and Size Registers"
124>;
125
126def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
127  "HasMadMixInsts",
128  "true",
129  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
130>;
131
132def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
133  "HasFmaMixInsts",
134  "true",
135  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
136>;
137
138def FeatureSupportsXNACK : SubtargetFeature<"xnack-support",
139  "SupportsXNACK",
140  "true",
141  "Hardware supports XNACK"
142>;
143
144// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
145// XNACK. The current default kernel driver setting is:
146// - graphics ring: XNACK disabled
147// - compute ring: XNACK enabled
148//
149// If XNACK is enabled, the VMEM latency can be worse.
150// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
151def FeatureXNACK : SubtargetFeature<"xnack",
152  "EnableXNACK",
153  "true",
154  "Enable XNACK support"
155>;
156
157def FeatureTgSplit : SubtargetFeature<"tgsplit",
158  "EnableTgSplit",
159  "true",
160  "Enable threadgroup split execution"
161>;
162
163def FeatureCuMode : SubtargetFeature<"cumode",
164  "EnableCuMode",
165  "true",
166  "Enable CU wavefront execution mode"
167>;
168
169def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
170  "SGPRInitBug",
171  "true",
172  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
173>;
174
175def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
176  "LDSMisalignedBug",
177  "true",
178  "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode"
179>;
180
181def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
182  "HasMFMAInlineLiteralBug",
183  "true",
184  "MFMA cannot use inline literal as SrcC"
185>;
186
187def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
188  "HasVcmpxPermlaneHazard",
189  "true",
190  "TODO: describe me"
191>;
192
193def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
194  "HasVMEMtoScalarWriteHazard",
195  "true",
196  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
197>;
198
199def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
200  "HasSMEMtoVectorWriteHazard",
201  "true",
202  "s_load_dword followed by v_cmp page faults"
203>;
204
205def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
206  "HasInstFwdPrefetchBug",
207  "true",
208  "S_INST_PREFETCH instruction causes shader to hang"
209>;
210
211def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
212  "HasVcmpxExecWARHazard",
213  "true",
214  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
215>;
216
217def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
218  "HasLdsBranchVmemWARHazard",
219  "true",
220  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
221>;
222
223def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
224  "HasNSAtoVMEMBug",
225  "true",
226  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
227>;
228
229def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
230  "HasFlatSegmentOffsetBug",
231  "true",
232  "GFX10 bug where inst_offset is ignored when flat instructions access global memory"
233>;
234
235def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
236  "HasOffset3fBug",
237  "true",
238  "Branch offset of 3f hardware bug"
239>;
240
241def FeatureImageStoreD16Bug : SubtargetFeature<"image-store-d16-bug",
242  "HasImageStoreD16Bug",
243  "true",
244  "Image Store D16 hardware bug"
245>;
246
247def FeatureImageGather4D16Bug : SubtargetFeature<"image-gather4-d16-bug",
248  "HasImageGather4D16Bug",
249  "true",
250  "Image Gather4 D16 hardware bug"
251>;
252
253class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
254  "ldsbankcount"#Value,
255  "LDSBankCount",
256  !cast<string>(Value),
257  "The number of LDS banks per compute unit."
258>;
259
260def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
261def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
262
263def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
264  "GCN3Encoding",
265  "true",
266  "Encoding format for VI"
267>;
268
269def FeatureCIInsts : SubtargetFeature<"ci-insts",
270  "CIInsts",
271  "true",
272  "Additional instructions for CI+"
273>;
274
275def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
276  "GFX8Insts",
277  "true",
278  "Additional instructions for GFX8+"
279>;
280
281def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
282  "GFX9Insts",
283  "true",
284  "Additional instructions for GFX9+"
285>;
286
287def FeatureGFX90AInsts : SubtargetFeature<"gfx90a-insts",
288  "GFX90AInsts",
289  "true",
290  "Additional instructions for GFX90A+"
291>;
292
293def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
294  "GFX10Insts",
295  "true",
296  "Additional instructions for GFX10+"
297>;
298
299def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts",
300  "GFX10_3Insts",
301  "true",
302  "Additional instructions for GFX10.3"
303>;
304
305def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
306  "GFX7GFX8GFX9Insts",
307  "true",
308  "Instructions shared in GFX7, GFX8, GFX9"
309>;
310
311def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
312  "HasSMemRealTime",
313  "true",
314  "Has s_memrealtime instruction"
315>;
316
317def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
318  "HasInv2PiInlineImm",
319  "true",
320  "Has 1 / (2 * pi) as inline immediate"
321>;
322
323def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
324  "Has16BitInsts",
325  "true",
326  "Has i16/f16 instructions"
327>;
328
329def FeatureVOP3P : SubtargetFeature<"vop3p",
330  "HasVOP3PInsts",
331  "true",
332  "Has VOP3P packed instructions"
333>;
334
335def FeatureMovrel : SubtargetFeature<"movrel",
336  "HasMovrel",
337  "true",
338  "Has v_movrel*_b32 instructions"
339>;
340
341def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
342  "HasVGPRIndexMode",
343  "true",
344  "Has VGPR mode register indexing"
345>;
346
347def FeatureScalarStores : SubtargetFeature<"scalar-stores",
348  "HasScalarStores",
349  "true",
350  "Has store scalar memory instructions"
351>;
352
353def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
354  "HasScalarAtomics",
355  "true",
356  "Has atomic scalar memory instructions"
357>;
358
359def FeatureSDWA : SubtargetFeature<"sdwa",
360  "HasSDWA",
361  "true",
362  "Support SDWA (Sub-DWORD Addressing) extension"
363>;
364
365def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
366  "HasSDWAOmod",
367  "true",
368  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
369>;
370
371def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
372  "HasSDWAScalar",
373  "true",
374  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
375>;
376
377def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
378  "HasSDWASdst",
379  "true",
380  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
381>;
382
383def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
384  "HasSDWAMac",
385  "true",
386  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
387>;
388
389def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
390  "HasSDWAOutModsVOPC",
391  "true",
392  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
393>;
394
395def FeatureDPP : SubtargetFeature<"dpp",
396  "HasDPP",
397  "true",
398  "Support DPP (Data Parallel Primitives) extension"
399>;
400
401// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
402def FeatureDPP8 : SubtargetFeature<"dpp8",
403  "HasDPP8",
404  "true",
405  "Support DPP8 (Data Parallel Primitives) extension"
406>;
407
408def Feature64BitDPP : SubtargetFeature<"dpp-64bit",
409  "Has64BitDPP",
410  "true",
411  "Support DPP (Data Parallel Primitives) extension"
412>;
413
414def FeaturePackedFP32Ops : SubtargetFeature<"packed-fp32-ops",
415  "HasPackedFP32Ops",
416  "true",
417  "Support packed fp32 instructions"
418>;
419
420def FeatureR128A16 : SubtargetFeature<"r128-a16",
421  "HasR128A16",
422  "true",
423  "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
424>;
425
426def FeatureGFX10A16 : SubtargetFeature<"a16",
427  "HasGFX10A16",
428  "true",
429  "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
430>;
431
432def FeatureG16 : SubtargetFeature<"g16",
433  "HasG16",
434  "true",
435  "Support G16 for 16-bit gradient image operands"
436>;
437
438def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
439  "HasNSAEncoding",
440  "true",
441  "Support NSA encoding for image instructions"
442>;
443
444def FeatureExtendedImageInsts : SubtargetFeature<"extended-image-insts",
445  "HasExtendedImageInsts",
446  "true",
447  "Support mips != 0, lod != 0, gather4, and get_lod"
448>;
449
450def FeatureGFX10_BEncoding : SubtargetFeature<"gfx10_b-encoding",
451  "GFX10_BEncoding",
452  "true",
453  "Encoding format GFX10_B"
454>;
455
456def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
457  "HasIntClamp",
458  "true",
459  "Support clamp for integer destination"
460>;
461
462def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
463  "HasUnpackedD16VMem",
464  "true",
465  "Has unpacked d16 vmem instructions"
466>;
467
468def FeatureDLInsts : SubtargetFeature<"dl-insts",
469  "HasDLInsts",
470  "true",
471  "Has v_fmac_f32 and v_xnor_b32 instructions"
472>;
473
474def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
475  "HasDot1Insts",
476  "true",
477  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
478>;
479
480def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
481  "HasDot2Insts",
482  "true",
483  "Has v_dot2_i32_i16, v_dot2_u32_u16 instructions"
484>;
485
486def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
487  "HasDot3Insts",
488  "true",
489  "Has v_dot8c_i32_i4 instruction"
490>;
491
492def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
493  "HasDot4Insts",
494  "true",
495  "Has v_dot2c_i32_i16 instruction"
496>;
497
498def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
499  "HasDot5Insts",
500  "true",
501  "Has v_dot2c_f32_f16 instruction"
502>;
503
504def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
505  "HasDot6Insts",
506  "true",
507  "Has v_dot4c_i32_i8 instruction"
508>;
509
510def FeatureDot7Insts : SubtargetFeature<"dot7-insts",
511  "HasDot7Insts",
512  "true",
513  "Has v_dot2_f32_f16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
514>;
515
516def FeatureMAIInsts : SubtargetFeature<"mai-insts",
517  "HasMAIInsts",
518  "true",
519  "Has mAI instructions"
520>;
521
522def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
523  "HasPkFmacF16Inst",
524  "true",
525  "Has v_pk_fmac_f16 instruction"
526>;
527
528def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
529  "HasAtomicFaddInsts",
530  "true",
531  "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
532  "global_atomic_pk_add_f16 instructions",
533  [FeatureFlatGlobalInsts]
534>;
535
536def FeatureSupportsSRAMECC : SubtargetFeature<"sramecc-support",
537  "SupportsSRAMECC",
538  "true",
539  "Hardware supports SRAMECC"
540>;
541
542def FeatureSRAMECC : SubtargetFeature<"sramecc",
543  "EnableSRAMECC",
544  "true",
545  "Enable SRAMECC"
546>;
547
548def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
549  "HasNoSdstCMPX",
550  "true",
551  "V_CMPX does not write VCC/SGPR in addition to EXEC"
552>;
553
554def FeatureVscnt : SubtargetFeature<"vscnt",
555  "HasVscnt",
556  "true",
557  "Has separate store vscnt counter"
558>;
559
560def FeatureGetWaveIdInst : SubtargetFeature<"get-wave-id-inst",
561  "HasGetWaveIdInst",
562  "true",
563  "Has s_get_waveid_in_workgroup instruction"
564>;
565
566def FeatureSMemTimeInst : SubtargetFeature<"s-memtime-inst",
567  "HasSMemTimeInst",
568  "true",
569  "Has s_memtime instruction"
570>;
571
572def FeatureShaderCyclesRegister : SubtargetFeature<"shader-cycles-register",
573  "HasShaderCyclesRegister",
574  "true",
575  "Has SHADER_CYCLES hardware register"
576>;
577
578def FeatureMadMacF32Insts : SubtargetFeature<"mad-mac-f32-insts",
579  "HasMadMacF32Insts",
580  "true",
581  "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions"
582>;
583
584def FeatureDsSrc2Insts : SubtargetFeature<"ds-src2-insts",
585  "HasDsSrc2Insts",
586  "true",
587  "Has ds_*_src2 instructions"
588>;
589
590def FeatureRegisterBanking : SubtargetFeature<"register-banking",
591  "HasRegisterBanking",
592  "true",
593  "Has register banking"
594>;
595
596def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
597  "HasVOP3Literal",
598  "true",
599  "Can use one literal in VOP3"
600>;
601
602def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
603  "HasNoDataDepHazard",
604  "true",
605  "Does not need SW waitstates"
606>;
607
608//===------------------------------------------------------------===//
609// Subtarget Features (options and debugging)
610//===------------------------------------------------------------===//
611
612class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
613  "max-private-element-size-"#size,
614  "MaxPrivateElementSize",
615  !cast<string>(size),
616  "Maximum private access size may be "#size
617>;
618
619def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
620def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
621def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
622
623def FeatureDumpCode : SubtargetFeature <"DumpCode",
624  "DumpCode",
625  "true",
626  "Dump MachineInstrs in the CodeEmitter"
627>;
628
629def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
630  "DumpCode",
631  "true",
632  "Dump MachineInstrs in the CodeEmitter"
633>;
634
635// XXX - This should probably be removed once enabled by default
636def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
637  "EnableLoadStoreOpt",
638  "true",
639  "Enable SI load/store optimizer pass"
640>;
641
642// Performance debugging feature. Allow using DS instruction immediate
643// offsets even if the base pointer can't be proven to be base. On SI,
644// base pointer values that won't give the same result as a 16-bit add
645// are not safe to fold, but this will override the conservative test
646// for the base pointer.
647def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
648  "unsafe-ds-offset-folding",
649  "EnableUnsafeDSOffsetFolding",
650  "true",
651  "Force using DS instruction immediate offsets on SI"
652>;
653
654def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
655  "EnableSIScheduler",
656  "true",
657  "Enable SI Machine Scheduler"
658>;
659
660def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
661  "EnableDS128",
662  "true",
663  "Use ds_{read|write}_b128"
664>;
665
666// Sparse texture support requires that all result registers are zeroed when
667// PRTStrictNull is set to true. This feature is turned on for all architectures
668// but is enabled as a feature in case there are situations where PRTStrictNull
669// is disabled by the driver.
670def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
671  "EnablePRTStrictNull",
672  "true",
673  "Enable zeroing of result registers for sparse texture fetches"
674>;
675
676// Unless +-flat-for-global is specified, turn on FlatForGlobal for
677// all OS-es on VI and newer hardware to avoid assertion failures due
678// to missing ADDR64 variants of MUBUF instructions.
679// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
680// instructions.
681
682def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
683  "FlatForGlobal",
684  "true",
685  "Force to generate flat instruction for global"
686>;
687
688def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
689  "auto-waitcnt-before-barrier",
690  "AutoWaitcntBeforeBarrier",
691  "true",
692  "Hardware automatically inserts waitcnt before barrier"
693>;
694
695def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
696  "HasTrigReducedRange",
697  "true",
698  "Requires use of fract on arguments to trig instructions"
699>;
700
701// Alignment enforcement is controlled by a configuration register:
702// SH_MEM_CONFIG.alignment_mode
703def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode",
704  "UnalignedAccessMode",
705  "true",
706  "Enable unaligned global, local and region loads and stores if the hardware"
707  " supports it"
708>;
709
710def FeaturePackedTID : SubtargetFeature<"packed-tid",
711  "HasPackedTID",
712  "true",
713  "Workitem IDs are packed into v0 at kernel launch"
714>;
715
716// Dummy feature used to disable assembler instructions.
717def FeatureDisable : SubtargetFeature<"",
718  "FeatureDisable","true",
719  "Dummy feature to disable assembler instructions"
720>;
721
722class GCNSubtargetFeatureGeneration <string Value,
723                                     string FeatureName,
724                                     list<SubtargetFeature> Implies> :
725        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
726
727def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
728    "southern-islands",
729  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
730  FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,
731  FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
732  FeatureTrigReducedRange, FeatureExtendedImageInsts
733  ]
734>;
735
736def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
737    "sea-islands",
738  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
739  FeatureWavefrontSize64, FeatureFlatAddressSpace,
740  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
741  FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
742  FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureUnalignedBufferAccess
743  ]
744>;
745
746def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
747  "volcanic-islands",
748  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
749   FeatureWavefrontSize64, FeatureFlatAddressSpace,
750   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
751   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
752   FeatureScalarStores, FeatureInv2PiInlineImm,
753   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
754   FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
755   FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
756   FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureFastDenormalF32,
757   FeatureUnalignedBufferAccess
758  ]
759>;
760
761def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
762  "gfx9",
763  [FeatureFP64, FeatureLocalMemorySize65536,
764   FeatureWavefrontSize64, FeatureFlatAddressSpace,
765   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
766   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
767   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
768   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
769   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
770   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
771   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
772   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
773   FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureSupportsXNACK,
774   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess
775  ]
776>;
777
778def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
779  "gfx10",
780  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
781   FeatureFlatAddressSpace,
782   FeatureCIInsts, Feature16BitInsts,
783   FeatureSMemRealTime, FeatureInv2PiInlineImm,
784   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
785   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
786   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
787   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
788   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
789   FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
790   FeatureVOP3Literal, FeatureDPP8, FeatureExtendedImageInsts,
791   FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
792   FeatureGFX10A16, FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureG16,
793   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess
794  ]
795>;
796
797class FeatureSet<list<SubtargetFeature> Features_> {
798  list<SubtargetFeature> Features = Features_;
799}
800
801def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
802   FeatureFastFMAF32,
803   HalfRate64Ops,
804   FeatureLDSBankCount32]>;
805
806def FeatureISAVersion6_0_1 : FeatureSet<
807  [FeatureSouthernIslands,
808   FeatureLDSBankCount32]>;
809
810def FeatureISAVersion6_0_2 : FeatureSet<
811  [FeatureSouthernIslands,
812   FeatureLDSBankCount32]>;
813
814def FeatureISAVersion7_0_0 : FeatureSet<
815  [FeatureSeaIslands,
816   FeatureLDSBankCount32]>;
817
818def FeatureISAVersion7_0_1 : FeatureSet<
819  [FeatureSeaIslands,
820   HalfRate64Ops,
821   FeatureLDSBankCount32,
822   FeatureFastFMAF32]>;
823
824def FeatureISAVersion7_0_2 : FeatureSet<
825  [FeatureSeaIslands,
826   FeatureLDSBankCount16,
827   FeatureFastFMAF32]>;
828
829def FeatureISAVersion7_0_3 : FeatureSet<
830  [FeatureSeaIslands,
831   FeatureLDSBankCount16]>;
832
833def FeatureISAVersion7_0_4 : FeatureSet<
834  [FeatureSeaIslands,
835   FeatureLDSBankCount32]>;
836
837def FeatureISAVersion7_0_5 : FeatureSet<
838  [FeatureSeaIslands,
839   FeatureLDSBankCount16]>;
840
841def FeatureISAVersion8_0_1 : FeatureSet<
842  [FeatureVolcanicIslands,
843   FeatureFastFMAF32,
844   HalfRate64Ops,
845   FeatureLDSBankCount32,
846   FeatureSupportsXNACK,
847   FeatureUnpackedD16VMem]>;
848
849def FeatureISAVersion8_0_2 : FeatureSet<
850  [FeatureVolcanicIslands,
851   FeatureLDSBankCount32,
852   FeatureSGPRInitBug,
853   FeatureUnpackedD16VMem]>;
854
855def FeatureISAVersion8_0_3 : FeatureSet<
856  [FeatureVolcanicIslands,
857   FeatureLDSBankCount32,
858   FeatureUnpackedD16VMem]>;
859
860def FeatureISAVersion8_0_5 : FeatureSet<
861  [FeatureVolcanicIslands,
862   FeatureLDSBankCount32,
863   FeatureSGPRInitBug,
864   FeatureUnpackedD16VMem]>;
865
866def FeatureISAVersion8_1_0 : FeatureSet<
867  [FeatureVolcanicIslands,
868   FeatureLDSBankCount16,
869   FeatureSupportsXNACK,
870   FeatureImageStoreD16Bug,
871   FeatureImageGather4D16Bug]>;
872
873def FeatureISAVersion9_0_0 : FeatureSet<
874  [FeatureGFX9,
875   FeatureMadMixInsts,
876   FeatureLDSBankCount32,
877   FeatureDsSrc2Insts,
878   FeatureExtendedImageInsts,
879   FeatureMadMacF32Insts,
880   FeatureImageGather4D16Bug]>;
881
882def FeatureISAVersion9_0_2 : FeatureSet<
883  [FeatureGFX9,
884   FeatureMadMixInsts,
885   FeatureLDSBankCount32,
886   FeatureDsSrc2Insts,
887   FeatureExtendedImageInsts,
888   FeatureMadMacF32Insts,
889   FeatureImageGather4D16Bug]>;
890
891def FeatureISAVersion9_0_4 : FeatureSet<
892  [FeatureGFX9,
893   FeatureLDSBankCount32,
894   FeatureDsSrc2Insts,
895   FeatureExtendedImageInsts,
896   FeatureMadMacF32Insts,
897   FeatureFmaMixInsts,
898   FeatureImageGather4D16Bug]>;
899
900def FeatureISAVersion9_0_6 : FeatureSet<
901  [FeatureGFX9,
902   HalfRate64Ops,
903   FeatureFmaMixInsts,
904   FeatureLDSBankCount32,
905   FeatureDsSrc2Insts,
906   FeatureExtendedImageInsts,
907   FeatureMadMacF32Insts,
908   FeatureDLInsts,
909   FeatureDot1Insts,
910   FeatureDot2Insts,
911   FeatureDot7Insts,
912   FeatureSupportsSRAMECC,
913   FeatureImageGather4D16Bug]>;
914
915def FeatureISAVersion9_0_8 : FeatureSet<
916  [FeatureGFX9,
917   HalfRate64Ops,
918   FeatureFmaMixInsts,
919   FeatureLDSBankCount32,
920   FeatureDsSrc2Insts,
921   FeatureExtendedImageInsts,
922   FeatureMadMacF32Insts,
923   FeatureDLInsts,
924   FeatureDot1Insts,
925   FeatureDot2Insts,
926   FeatureDot3Insts,
927   FeatureDot4Insts,
928   FeatureDot5Insts,
929   FeatureDot6Insts,
930   FeatureDot7Insts,
931   FeatureMAIInsts,
932   FeaturePkFmacF16Inst,
933   FeatureAtomicFaddInsts,
934   FeatureSupportsSRAMECC,
935   FeatureMFMAInlineLiteralBug,
936   FeatureImageGather4D16Bug]>;
937
938def FeatureISAVersion9_0_9 : FeatureSet<
939  [FeatureGFX9,
940   FeatureMadMixInsts,
941   FeatureLDSBankCount32,
942   FeatureDsSrc2Insts,
943   FeatureExtendedImageInsts,
944   FeatureMadMacF32Insts,
945   FeatureImageGather4D16Bug]>;
946
947def FeatureISAVersion9_0_A : FeatureSet<
948  [FeatureGFX9,
949   FeatureGFX90AInsts,
950   FeatureFmaMixInsts,
951   FeatureLDSBankCount32,
952   FeatureDLInsts,
953   FeatureDot1Insts,
954   FeatureDot2Insts,
955   FeatureDot3Insts,
956   FeatureDot4Insts,
957   FeatureDot5Insts,
958   FeatureDot6Insts,
959   FeatureDot7Insts,
960   Feature64BitDPP,
961   FeaturePackedFP32Ops,
962   FeatureMAIInsts,
963   FeaturePkFmacF16Inst,
964   FeatureAtomicFaddInsts,
965   FeatureMadMacF32Insts,
966   FeatureSupportsSRAMECC,
967   FeaturePackedTID,
968   FullRate64Ops]>;
969
970def FeatureISAVersion9_0_C : FeatureSet<
971  [FeatureGFX9,
972   FeatureMadMixInsts,
973   FeatureLDSBankCount32,
974   FeatureDsSrc2Insts,
975   FeatureExtendedImageInsts,
976   FeatureMadMacF32Insts,
977   FeatureImageGather4D16Bug]>;
978
979// TODO: Organize more features into groups.
980def FeatureGroup {
981  // Bugs present on gfx10.1.
982  list<SubtargetFeature> GFX10_1_Bugs = [
983    FeatureVcmpxPermlaneHazard,
984    FeatureVMEMtoScalarWriteHazard,
985    FeatureSMEMtoVectorWriteHazard,
986    FeatureInstFwdPrefetchBug,
987    FeatureVcmpxExecWARHazard,
988    FeatureLdsBranchVmemWARHazard,
989    FeatureNSAtoVMEMBug,
990    FeatureOffset3fBug,
991    FeatureFlatSegmentOffsetBug
992   ];
993}
994
995def FeatureISAVersion10_1_0 : FeatureSet<
996  !listconcat(FeatureGroup.GFX10_1_Bugs,
997    [FeatureGFX10,
998     FeatureLDSBankCount32,
999     FeatureDLInsts,
1000     FeatureNSAEncoding,
1001     FeatureWavefrontSize32,
1002     FeatureScalarStores,
1003     FeatureScalarAtomics,
1004     FeatureScalarFlatScratchInsts,
1005     FeatureGetWaveIdInst,
1006     FeatureMadMacF32Insts,
1007     FeatureDsSrc2Insts,
1008     FeatureLdsMisalignedBug,
1009     FeatureSupportsXNACK])>;
1010
1011def FeatureISAVersion10_1_1 : FeatureSet<
1012  !listconcat(FeatureGroup.GFX10_1_Bugs,
1013    [FeatureGFX10,
1014     FeatureLDSBankCount32,
1015     FeatureDLInsts,
1016     FeatureDot1Insts,
1017     FeatureDot2Insts,
1018     FeatureDot5Insts,
1019     FeatureDot6Insts,
1020     FeatureDot7Insts,
1021     FeatureNSAEncoding,
1022     FeatureWavefrontSize32,
1023     FeatureScalarStores,
1024     FeatureScalarAtomics,
1025     FeatureScalarFlatScratchInsts,
1026     FeatureGetWaveIdInst,
1027     FeatureMadMacF32Insts,
1028     FeatureDsSrc2Insts,
1029     FeatureLdsMisalignedBug,
1030     FeatureSupportsXNACK])>;
1031
1032def FeatureISAVersion10_1_2 : FeatureSet<
1033  !listconcat(FeatureGroup.GFX10_1_Bugs,
1034    [FeatureGFX10,
1035     FeatureLDSBankCount32,
1036     FeatureDLInsts,
1037     FeatureDot1Insts,
1038     FeatureDot2Insts,
1039     FeatureDot5Insts,
1040     FeatureDot6Insts,
1041     FeatureDot7Insts,
1042     FeatureNSAEncoding,
1043     FeatureWavefrontSize32,
1044     FeatureScalarStores,
1045     FeatureScalarAtomics,
1046     FeatureScalarFlatScratchInsts,
1047     FeatureGetWaveIdInst,
1048     FeatureMadMacF32Insts,
1049     FeatureDsSrc2Insts,
1050     FeatureLdsMisalignedBug,
1051     FeatureSupportsXNACK])>;
1052
1053def FeatureISAVersion10_3_0 : FeatureSet<
1054  [FeatureGFX10,
1055   FeatureGFX10_BEncoding,
1056   FeatureGFX10_3Insts,
1057   FeatureLDSBankCount32,
1058   FeatureDLInsts,
1059   FeatureDot1Insts,
1060   FeatureDot2Insts,
1061   FeatureDot5Insts,
1062   FeatureDot6Insts,
1063   FeatureDot7Insts,
1064   FeatureNSAEncoding,
1065   FeatureWavefrontSize32,
1066   FeatureShaderCyclesRegister]>;
1067
1068//===----------------------------------------------------------------------===//
1069
1070def AMDGPUInstrInfo : InstrInfo {
1071  let guessInstructionProperties = 1;
1072  let noNamedPositionallyEncodedOperands = 1;
1073}
1074
1075def AMDGPUAsmParser : AsmParser {
1076  // Some of the R600 registers have the same name, so this crashes.
1077  // For example T0_XYZW and T0_XY both have the asm name T0.
1078  let ShouldEmitMatchRegisterName = 0;
1079}
1080
1081def AMDGPUAsmWriter : AsmWriter {
1082  int PassSubtarget = 1;
1083}
1084
1085def AMDGPUAsmVariants {
1086  string Default = "Default";
1087  int Default_ID = 0;
1088  string VOP3 = "VOP3";
1089  int VOP3_ID = 1;
1090  string SDWA = "SDWA";
1091  int SDWA_ID = 2;
1092  string SDWA9 = "SDWA9";
1093  int SDWA9_ID = 3;
1094  string DPP = "DPP";
1095  int DPP_ID = 4;
1096  string Disable = "Disable";
1097  int Disable_ID = 5;
1098}
1099
1100def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
1101  let Variant = AMDGPUAsmVariants.Default_ID;
1102  let Name = AMDGPUAsmVariants.Default;
1103}
1104
1105def VOP3AsmParserVariant : AsmParserVariant {
1106  let Variant = AMDGPUAsmVariants.VOP3_ID;
1107  let Name = AMDGPUAsmVariants.VOP3;
1108}
1109
1110def SDWAAsmParserVariant : AsmParserVariant {
1111  let Variant = AMDGPUAsmVariants.SDWA_ID;
1112  let Name = AMDGPUAsmVariants.SDWA;
1113}
1114
1115def SDWA9AsmParserVariant : AsmParserVariant {
1116  let Variant = AMDGPUAsmVariants.SDWA9_ID;
1117  let Name = AMDGPUAsmVariants.SDWA9;
1118}
1119
1120
1121def DPPAsmParserVariant : AsmParserVariant {
1122  let Variant = AMDGPUAsmVariants.DPP_ID;
1123  let Name = AMDGPUAsmVariants.DPP;
1124}
1125
1126def AMDGPU : Target {
1127  // Pull in Instruction Info:
1128  let InstructionSet = AMDGPUInstrInfo;
1129  let AssemblyParsers = [AMDGPUAsmParser];
1130  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
1131                                VOP3AsmParserVariant,
1132                                SDWAAsmParserVariant,
1133                                SDWA9AsmParserVariant,
1134                                DPPAsmParserVariant];
1135  let AssemblyWriters = [AMDGPUAsmWriter];
1136  let AllowRegisterRenaming = 1;
1137}
1138
1139// Dummy Instruction itineraries for pseudo instructions
1140def ALU_NULL : FuncUnit;
1141def NullALU : InstrItinClass;
1142
1143//===----------------------------------------------------------------------===//
1144// Predicate helper class
1145//===----------------------------------------------------------------------===//
1146
1147def isGFX6 :
1148  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1149  AssemblerPredicate<(all_of FeatureSouthernIslands)>;
1150
1151def isGFX6GFX7 :
1152  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1153            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1154  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
1155
1156def isGFX6GFX7GFX10 :
1157  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1158            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1159            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1160  AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
1161
1162def isGFX7Only :
1163  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1164  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
1165
1166def isGFX7GFX10 :
1167  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1168            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1169  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
1170
1171def isGFX7GFX8GFX9 :
1172  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1173            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1174            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1175  AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
1176
1177def isGFX6GFX7GFX8GFX9 :
1178  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1179            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1180            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1181            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1182  AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
1183
1184def isGFX6GFX7GFX8GFX9NotGFX90A :
1185  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1186            "(Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1187            " Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1188            " Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1189            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1190  AssemblerPredicate<(all_of (not FeatureGFX10Insts), (not FeatureGFX90AInsts))>;
1191
1192def isGFX7Plus :
1193  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1194  AssemblerPredicate<(all_of FeatureCIInsts)>;
1195
1196def isGFX8Plus :
1197  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1198  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1199
1200def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1201                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1202  AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1203
1204def isGFX9Plus :
1205  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1206  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1207
1208def isGFX9Only : Predicate <
1209  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1210  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1211
1212def isGCN3ExcludingGFX90A :
1213  Predicate<"Subtarget->isGCN3Encoding() && !Subtarget->hasGFX90AInsts()">,
1214  AssemblerPredicate<(all_of FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1215
1216def isGFX90APlus :
1217  Predicate<"Subtarget->hasGFX90AInsts()">,
1218  AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1219
1220def isNotGFX90APlus :
1221  Predicate<"!Subtarget->hasGFX90AInsts()">,
1222  AssemblerPredicate<(all_of (not FeatureGFX90AInsts))>;
1223
1224def isGFX8GFX9NotGFX90A :
1225  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1226            "(Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1227            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1228  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1229
1230def isGFX90AOnly :
1231  Predicate<"Subtarget->hasGFX90AInsts()">,
1232  AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1233
1234def isGFX908orGFX90A :
1235  Predicate<"Subtarget->hasMAIInsts()">,
1236  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1237
1238def isGFX8GFX9 :
1239  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1240            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1241  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1242
1243def isGFX10Plus :
1244  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1245  AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1246
1247def isGFX10Before1030 :
1248  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 &&"
1249            "!Subtarget->hasGFX10_3Insts()">,
1250  AssemblerPredicate<(all_of FeatureGFX10Insts,(not FeatureGFX10_3Insts))>;
1251
1252def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1253  AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1254
1255def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1256  AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1257def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1258  AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1259def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1260  AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1261def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1262  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1263
1264def HasFlatScratchSTMode : Predicate<"Subtarget->hasFlatScratchSTMode()">,
1265  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1266
1267def HasGFX10_BEncoding : Predicate<"Subtarget->hasGFX10_BEncoding()">,
1268  AssemblerPredicate<(all_of FeatureGFX10_BEncoding)>;
1269
1270def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1271  AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1272def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1273  AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1274
1275def D16PreservesUnusedBits :
1276  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1277  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1278
1279def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1280def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1281
1282def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1283  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1284
1285def HasLDSFPAtomics : Predicate<"Subtarget->hasLDSFPAtomics()">,
1286  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1287
1288def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1289  AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1290
1291def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1292
1293def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1294  AssemblerPredicate<(all_of Feature16BitInsts)>;
1295def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1296  AssemblerPredicate<(all_of FeatureVOP3P)>;
1297
1298def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
1299def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
1300
1301def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1302  AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1303
1304def HasSDWA9 :
1305  Predicate<"Subtarget->hasSDWA()">,
1306  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1307
1308def HasSDWA10 :
1309  Predicate<"Subtarget->hasSDWA()">,
1310  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1311
1312def HasDPP : Predicate<"Subtarget->hasDPP()">,
1313  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1314
1315def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1316  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1317
1318def Has64BitDPP : Predicate<"Subtarget->has64BitDPP()">,
1319  AssemblerPredicate<(all_of Feature64BitDPP)>;
1320
1321def HasPackedFP32Ops : Predicate<"Subtarget->hasPackedFP32Ops()">,
1322  AssemblerPredicate<(all_of FeaturePackedFP32Ops)>;
1323
1324def HasFmaakFmamkF32Insts :
1325  Predicate<"Subtarget->hasFmaakFmamkF32Insts()">,
1326  AssemblerPredicate<(any_of FeatureGFX10Insts)>;
1327
1328def HasExtendedImageInsts : Predicate<"Subtarget->hasExtendedImageInsts()">,
1329  AssemblerPredicate<(all_of FeatureExtendedImageInsts)>;
1330
1331def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1332  AssemblerPredicate<(all_of FeatureR128A16)>;
1333
1334def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1335  AssemblerPredicate<(all_of FeatureGFX10A16)>;
1336
1337def HasG16 : Predicate<"Subtarget->hasG16()">,
1338  AssemblerPredicate<(all_of FeatureG16)>;
1339
1340def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1341  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1342
1343def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1344  AssemblerPredicate<(all_of FeatureIntClamp)>;
1345
1346def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1347  AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1348
1349def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1350  AssemblerPredicate<(all_of FeatureScalarStores)>;
1351
1352def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1353  AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1354
1355def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1356  AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1357
1358def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1359  AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1360
1361def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1362def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1363def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1364                      AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1365def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1366                AssemblerPredicate<(all_of FeatureMovrel)>;
1367
1368def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1369  AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1370
1371def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1372  AssemblerPredicate<(all_of FeatureDLInsts)>;
1373
1374def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1375  AssemblerPredicate<(all_of FeatureDot1Insts)>;
1376
1377def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1378  AssemblerPredicate<(all_of FeatureDot2Insts)>;
1379
1380def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1381  AssemblerPredicate<(all_of FeatureDot3Insts)>;
1382
1383def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1384  AssemblerPredicate<(all_of FeatureDot4Insts)>;
1385
1386def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1387  AssemblerPredicate<(all_of FeatureDot5Insts)>;
1388
1389def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1390  AssemblerPredicate<(all_of FeatureDot6Insts)>;
1391
1392def HasDot7Insts : Predicate<"Subtarget->hasDot7Insts()">,
1393  AssemblerPredicate<(all_of FeatureDot7Insts)>;
1394
1395def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">,
1396  AssemblerPredicate<(all_of FeatureGetWaveIdInst)>;
1397
1398def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1399  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1400
1401def HasSMemRealTime : Predicate<"Subtarget->hasSMemRealTime()">,
1402  AssemblerPredicate<(all_of FeatureSMemRealTime)>;
1403
1404def HasSMemTimeInst : Predicate<"Subtarget->hasSMemTimeInst()">,
1405  AssemblerPredicate<(all_of FeatureSMemTimeInst)>;
1406
1407def HasShaderCyclesRegister : Predicate<"Subtarget->hasShaderCyclesRegister()">,
1408  AssemblerPredicate<(all_of FeatureShaderCyclesRegister)>;
1409
1410def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1411  AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1412
1413def HasMadMacF32Insts : Predicate<"Subtarget->hasMadMacF32Insts()">,
1414  AssemblerPredicate<(all_of FeatureMadMacF32Insts)>;
1415
1416def HasFmaLegacy32 : Predicate<"Subtarget->hasGFX10_3Insts()">,
1417  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1418
1419def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1420  AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>;
1421
1422def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
1423  AssemblerPredicate<(all_of FeatureDsSrc2Insts)>;
1424
1425def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">,
1426  AssemblerPredicate<(all_of FeatureOffset3fBug)>;
1427
1428def EnableLateCFGStructurize : Predicate<
1429  "EnableLateStructurizeCFG">;
1430
1431def EnableFlatScratch : Predicate<"Subtarget->enableFlatScratch()">;
1432
1433def DisableFlatScratch : Predicate<"!Subtarget->enableFlatScratch()">;
1434
1435def HasUnalignedAccessMode : Predicate<"Subtarget->hasUnalignedAccessMode()">,
1436  AssemblerPredicate<(all_of FeatureUnalignedAccessMode)>;
1437
1438// Include AMDGPU TD files
1439include "SISchedule.td"
1440include "GCNProcessors.td"
1441include "AMDGPUInstrInfo.td"
1442include "SIRegisterInfo.td"
1443include "AMDGPURegisterBanks.td"
1444include "AMDGPUInstructions.td"
1445include "SIInstrInfo.td"
1446include "AMDGPUCallingConv.td"
1447include "AMDGPUSearchableTables.td"
1448