1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21
22class BoolToList<bit Value> {
23  list<int> ret = !if(Value, [1]<int>, []<int>);
24}
25
26//===------------------------------------------------------------===//
27// Subtarget Features (device properties)
28//===------------------------------------------------------------===//
29
30def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
31  "FastFMAF32",
32  "true",
33  "Assuming f32 fma is at least as fast as mul + add"
34>;
35
36def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
37  "MIMG_R128",
38  "true",
39  "Support 128-bit texture resources"
40>;
41
42def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
43  "HalfRate64Ops",
44  "true",
45  "Most fp64 instructions are half rate instead of quarter"
46>;
47
48def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
49  "FlatAddressSpace",
50  "true",
51  "Support flat address space"
52>;
53
54def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
55  "FlatInstOffsets",
56  "true",
57  "Flat instructions have immediate offset addressing mode"
58>;
59
60def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
61  "FlatGlobalInsts",
62  "true",
63  "Have global_* flat memory instructions"
64>;
65
66def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
67  "FlatScratchInsts",
68  "true",
69  "Have scratch_* flat memory instructions"
70>;
71
72def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
73  "ScalarFlatScratchInsts",
74  "true",
75  "Have s_scratch_* flat memory instructions"
76>;
77
78def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
79  "AddNoCarryInsts",
80  "true",
81  "Have VALU add/sub instructions without carry out"
82>;
83
84def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
85  "UnalignedBufferAccess",
86  "true",
87  "Support unaligned global loads and stores"
88>;
89
90def FeatureTrapHandler: SubtargetFeature<"trap-handler",
91  "TrapHandler",
92  "true",
93  "Trap handler support"
94>;
95
96def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
97  "UnalignedScratchAccess",
98  "true",
99  "Support unaligned scratch loads and stores"
100>;
101
102def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
103  "HasApertureRegs",
104  "true",
105  "Has Memory Aperture Base and Size Registers"
106>;
107
108def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
109  "HasMadMixInsts",
110  "true",
111  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
112>;
113
114def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
115  "HasFmaMixInsts",
116  "true",
117  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
118>;
119
120def FeatureDoesNotSupportXNACK : SubtargetFeature<"no-xnack-support",
121  "DoesNotSupportXNACK",
122  "true",
123  "Hardware does not support XNACK"
124>;
125
126// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
127// XNACK. The current default kernel driver setting is:
128// - graphics ring: XNACK disabled
129// - compute ring: XNACK enabled
130//
131// If XNACK is enabled, the VMEM latency can be worse.
132// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
133def FeatureXNACK : SubtargetFeature<"xnack",
134  "EnableXNACK",
135  "true",
136  "Enable XNACK support"
137>;
138
139def FeatureCuMode : SubtargetFeature<"cumode",
140  "EnableCuMode",
141  "true",
142  "Enable CU wavefront execution mode"
143>;
144
145def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
146  "SGPRInitBug",
147  "true",
148  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
149>;
150
151def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
152  "LDSMisalignedBug",
153  "true",
154  "Some GFX10 bug with misaligned multi-dword LDS access in WGP mode"
155>;
156
157def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
158  "HasVcmpxPermlaneHazard",
159  "true",
160  "TODO: describe me"
161>;
162
163def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
164  "HasVMEMtoScalarWriteHazard",
165  "true",
166  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
167>;
168
169def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
170  "HasSMEMtoVectorWriteHazard",
171  "true",
172  "s_load_dword followed by v_cmp page faults"
173>;
174
175def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
176  "HasInstFwdPrefetchBug",
177  "true",
178  "S_INST_PREFETCH instruction causes shader to hang"
179>;
180
181def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
182  "HasVcmpxExecWARHazard",
183  "true",
184  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
185>;
186
187def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
188  "HasLdsBranchVmemWARHazard",
189  "true",
190  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
191>;
192
193def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
194  "HasNSAtoVMEMBug",
195  "true",
196  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
197>;
198
199def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
200  "HasFlatSegmentOffsetBug",
201  "true",
202  "GFX10 bug, inst_offset ignored in flat segment"
203>;
204
205def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
206  "HasOffset3fBug",
207  "true",
208  "Branch offset of 3f hardware bug"
209>;
210
211class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
212  "ldsbankcount"#Value,
213  "LDSBankCount",
214  !cast<string>(Value),
215  "The number of LDS banks per compute unit."
216>;
217
218def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
219def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
220
221def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
222  "GCN3Encoding",
223  "true",
224  "Encoding format for VI"
225>;
226
227def FeatureCIInsts : SubtargetFeature<"ci-insts",
228  "CIInsts",
229  "true",
230  "Additional instructions for CI+"
231>;
232
233def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
234  "GFX8Insts",
235  "true",
236  "Additional instructions for GFX8+"
237>;
238
239def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
240  "GFX9Insts",
241  "true",
242  "Additional instructions for GFX9+"
243>;
244
245def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
246  "GFX10Insts",
247  "true",
248  "Additional instructions for GFX10+"
249>;
250
251def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
252  "GFX7GFX8GFX9Insts",
253  "true",
254  "Instructions shared in GFX7, GFX8, GFX9"
255>;
256
257def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
258  "HasSMemRealTime",
259  "true",
260  "Has s_memrealtime instruction"
261>;
262
263def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
264  "HasInv2PiInlineImm",
265  "true",
266  "Has 1 / (2 * pi) as inline immediate"
267>;
268
269def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
270  "Has16BitInsts",
271  "true",
272  "Has i16/f16 instructions"
273>;
274
275def FeatureVOP3P : SubtargetFeature<"vop3p",
276  "HasVOP3PInsts",
277  "true",
278  "Has VOP3P packed instructions"
279>;
280
281def FeatureMovrel : SubtargetFeature<"movrel",
282  "HasMovrel",
283  "true",
284  "Has v_movrel*_b32 instructions"
285>;
286
287def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
288  "HasVGPRIndexMode",
289  "true",
290  "Has VGPR mode register indexing"
291>;
292
293def FeatureScalarStores : SubtargetFeature<"scalar-stores",
294  "HasScalarStores",
295  "true",
296  "Has store scalar memory instructions"
297>;
298
299def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
300  "HasScalarAtomics",
301  "true",
302  "Has atomic scalar memory instructions"
303>;
304
305def FeatureSDWA : SubtargetFeature<"sdwa",
306  "HasSDWA",
307  "true",
308  "Support SDWA (Sub-DWORD Addressing) extension"
309>;
310
311def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
312  "HasSDWAOmod",
313  "true",
314  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
315>;
316
317def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
318  "HasSDWAScalar",
319  "true",
320  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
321>;
322
323def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
324  "HasSDWASdst",
325  "true",
326  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
327>;
328
329def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
330  "HasSDWAMac",
331  "true",
332  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
333>;
334
335def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
336  "HasSDWAOutModsVOPC",
337  "true",
338  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
339>;
340
341def FeatureDPP : SubtargetFeature<"dpp",
342  "HasDPP",
343  "true",
344  "Support DPP (Data Parallel Primitives) extension"
345>;
346
347// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
348def FeatureDPP8 : SubtargetFeature<"dpp8",
349  "HasDPP8",
350  "true",
351  "Support DPP8 (Data Parallel Primitives) extension"
352>;
353
354def FeatureR128A16 : SubtargetFeature<"r128-a16",
355  "HasR128A16",
356  "true",
357  "Support 16 bit coordindates/gradients/lod/clamp/mip types on gfx9"
358>;
359
360def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
361  "HasNSAEncoding",
362  "true",
363  "Support NSA encoding for image instructions"
364>;
365
366def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
367  "HasIntClamp",
368  "true",
369  "Support clamp for integer destination"
370>;
371
372def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
373  "HasUnpackedD16VMem",
374  "true",
375  "Has unpacked d16 vmem instructions"
376>;
377
378def FeatureDLInsts : SubtargetFeature<"dl-insts",
379  "HasDLInsts",
380  "true",
381  "Has v_fmac_f32 and v_xnor_b32 instructions"
382>;
383
384def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
385  "HasDot1Insts",
386  "true",
387  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
388>;
389
390def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
391  "HasDot2Insts",
392  "true",
393  "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
394>;
395
396def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
397  "HasDot3Insts",
398  "true",
399  "Has v_dot8c_i32_i4 instruction"
400>;
401
402def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
403  "HasDot4Insts",
404  "true",
405  "Has v_dot2c_i32_i16 instruction"
406>;
407
408def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
409  "HasDot5Insts",
410  "true",
411  "Has v_dot2c_f32_f16 instruction"
412>;
413
414def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
415  "HasDot6Insts",
416  "true",
417  "Has v_dot4c_i32_i8 instruction"
418>;
419
420def FeatureMAIInsts : SubtargetFeature<"mai-insts",
421  "HasMAIInsts",
422  "true",
423  "Has mAI instructions"
424>;
425
426def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
427  "HasPkFmacF16Inst",
428  "true",
429  "Has v_pk_fmac_f16 instruction"
430>;
431
432def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
433  "HasAtomicFaddInsts",
434  "true",
435  "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
436  "global_atomic_pk_add_f16 instructions"
437>;
438
439def FeatureDoesNotSupportSRAMECC : SubtargetFeature<"no-sram-ecc-support",
440  "DoesNotSupportSRAMECC",
441  "true",
442  "Hardware does not support SRAM ECC"
443>;
444
445def FeatureSRAMECC : SubtargetFeature<"sram-ecc",
446  "EnableSRAMECC",
447  "true",
448  "Enable SRAM ECC"
449>;
450
451def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
452  "HasNoSdstCMPX",
453  "true",
454  "V_CMPX does not write VCC/SGPR in addition to EXEC"
455>;
456
457def FeatureVscnt : SubtargetFeature<"vscnt",
458  "HasVscnt",
459  "true",
460  "Has separate store vscnt counter"
461>;
462
463def FeatureRegisterBanking : SubtargetFeature<"register-banking",
464  "HasRegisterBanking",
465  "true",
466  "Has register banking"
467>;
468
469def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
470  "HasVOP3Literal",
471  "true",
472  "Can use one literal in VOP3"
473>;
474
475def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
476  "HasNoDataDepHazard",
477  "true",
478  "Does not need SW waitstates"
479>;
480
481//===------------------------------------------------------------===//
482// Subtarget Features (options and debugging)
483//===------------------------------------------------------------===//
484
485// Denormal handling for fp64 and fp16 is controlled by the same
486// config register when fp16 supported.
487// TODO: Do we need a separate f16 setting when not legal?
488def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
489  "FP64FP16Denormals",
490  "true",
491  "Enable double and half precision denormal handling",
492  [FeatureFP64]
493>;
494
495def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
496  "FP64FP16Denormals",
497  "true",
498  "Enable double and half precision denormal handling",
499  [FeatureFP64, FeatureFP64FP16Denormals]
500>;
501
502def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
503  "FP64FP16Denormals",
504  "true",
505  "Enable half precision denormal handling",
506  [FeatureFP64FP16Denormals]
507>;
508
509def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
510  "FPExceptions",
511  "true",
512  "Enable floating point exceptions"
513>;
514
515class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
516  "max-private-element-size-"#size,
517  "MaxPrivateElementSize",
518  !cast<string>(size),
519  "Maximum private access size may be "#size
520>;
521
522def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
523def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
524def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
525
526def FeatureDumpCode : SubtargetFeature <"DumpCode",
527  "DumpCode",
528  "true",
529  "Dump MachineInstrs in the CodeEmitter"
530>;
531
532def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
533  "DumpCode",
534  "true",
535  "Dump MachineInstrs in the CodeEmitter"
536>;
537
538// XXX - This should probably be removed once enabled by default
539def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
540  "EnableLoadStoreOpt",
541  "true",
542  "Enable SI load/store optimizer pass"
543>;
544
545// Performance debugging feature. Allow using DS instruction immediate
546// offsets even if the base pointer can't be proven to be base. On SI,
547// base pointer values that won't give the same result as a 16-bit add
548// are not safe to fold, but this will override the conservative test
549// for the base pointer.
550def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
551  "unsafe-ds-offset-folding",
552  "EnableUnsafeDSOffsetFolding",
553  "true",
554  "Force using DS instruction immediate offsets on SI"
555>;
556
557def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
558  "EnableSIScheduler",
559  "true",
560  "Enable SI Machine Scheduler"
561>;
562
563def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
564  "EnableDS128",
565  "true",
566  "Use ds_{read|write}_b128"
567>;
568
569// Sparse texture support requires that all result registers are zeroed when
570// PRTStrictNull is set to true. This feature is turned on for all architectures
571// but is enabled as a feature in case there are situations where PRTStrictNull
572// is disabled by the driver.
573def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
574  "EnablePRTStrictNull",
575  "true",
576  "Enable zeroing of result registers for sparse texture fetches"
577>;
578
579// Unless +-flat-for-global is specified, turn on FlatForGlobal for
580// all OS-es on VI and newer hardware to avoid assertion failures due
581// to missing ADDR64 variants of MUBUF instructions.
582// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
583// instructions.
584
585def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
586  "FlatForGlobal",
587  "true",
588  "Force to generate flat instruction for global"
589>;
590
591def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
592  "auto-waitcnt-before-barrier",
593  "AutoWaitcntBeforeBarrier",
594  "true",
595  "Hardware automatically inserts waitcnt before barrier"
596>;
597
598def FeatureCodeObjectV3 : SubtargetFeature <
599  "code-object-v3",
600  "CodeObjectV3",
601  "true",
602  "Generate code object version 3"
603>;
604
605def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
606  "HasTrigReducedRange",
607  "true",
608  "Requires use of fract on arguments to trig instructions"
609>;
610
611// Dummy feature used to disable assembler instructions.
612def FeatureDisable : SubtargetFeature<"",
613  "FeatureDisable","true",
614  "Dummy feature to disable assembler instructions"
615>;
616
617class GCNSubtargetFeatureGeneration <string Value,
618                                     string FeatureName,
619                                     list<SubtargetFeature> Implies> :
620        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
621
622def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
623    "southern-islands",
624  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
625  FeatureWavefrontSize64,
626  FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange,
627  FeatureDoesNotSupportSRAMECC, FeatureDoesNotSupportXNACK]
628>;
629
630def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
631    "sea-islands",
632  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
633  FeatureWavefrontSize64, FeatureFlatAddressSpace,
634  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
635  FeatureGFX7GFX8GFX9Insts, FeatureDoesNotSupportSRAMECC]
636>;
637
638def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
639  "volcanic-islands",
640  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
641   FeatureWavefrontSize64, FeatureFlatAddressSpace,
642   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
643   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
644   FeatureScalarStores, FeatureInv2PiInlineImm,
645   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
646   FeatureIntClamp, FeatureTrigReducedRange, FeatureDoesNotSupportSRAMECC,
647   FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts
648  ]
649>;
650
651def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
652  "gfx9",
653  [FeatureFP64, FeatureLocalMemorySize65536,
654   FeatureWavefrontSize64, FeatureFlatAddressSpace,
655   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
656   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
657   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
658   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
659   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
660   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
661   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
662   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16
663  ]
664>;
665
666def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
667  "gfx10",
668  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
669   FeatureFlatAddressSpace,
670   FeatureCIInsts, Feature16BitInsts,
671   FeatureSMemRealTime, FeatureInv2PiInlineImm,
672   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
673   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
674   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
675   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
676   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
677   FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
678   FeatureVOP3Literal, FeatureDPP8,
679   FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureDoesNotSupportSRAMECC
680  ]
681>;
682
683class FeatureSet<list<SubtargetFeature> Features_> {
684  list<SubtargetFeature> Features = Features_;
685}
686
687def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
688   FeatureFastFMAF32,
689   HalfRate64Ops,
690   FeatureLDSBankCount32,
691   FeatureDoesNotSupportXNACK,
692   FeatureCodeObjectV3]>;
693
694def FeatureISAVersion6_0_1 : FeatureSet<
695  [FeatureSouthernIslands,
696   FeatureLDSBankCount32,
697   FeatureDoesNotSupportXNACK,
698   FeatureCodeObjectV3]>;
699
700def FeatureISAVersion7_0_0 : FeatureSet<
701  [FeatureSeaIslands,
702   FeatureLDSBankCount32,
703   FeatureDoesNotSupportXNACK,
704   FeatureCodeObjectV3]>;
705
706def FeatureISAVersion7_0_1 : FeatureSet<
707  [FeatureSeaIslands,
708   HalfRate64Ops,
709   FeatureLDSBankCount32,
710   FeatureFastFMAF32,
711   FeatureDoesNotSupportXNACK,
712   FeatureCodeObjectV3]>;
713
714def FeatureISAVersion7_0_2 : FeatureSet<
715  [FeatureSeaIslands,
716   FeatureLDSBankCount16,
717   FeatureFastFMAF32,
718   FeatureDoesNotSupportXNACK,
719   FeatureCodeObjectV3]>;
720
721def FeatureISAVersion7_0_3 : FeatureSet<
722  [FeatureSeaIslands,
723   FeatureLDSBankCount16,
724   FeatureDoesNotSupportXNACK,
725   FeatureCodeObjectV3]>;
726
727def FeatureISAVersion7_0_4 : FeatureSet<
728  [FeatureSeaIslands,
729   FeatureLDSBankCount32,
730   FeatureDoesNotSupportXNACK,
731   FeatureCodeObjectV3]>;
732
733def FeatureISAVersion8_0_1 : FeatureSet<
734  [FeatureVolcanicIslands,
735   FeatureFastFMAF32,
736   HalfRate64Ops,
737   FeatureLDSBankCount32,
738   FeatureXNACK,
739   FeatureUnpackedD16VMem,
740   FeatureCodeObjectV3]>;
741
742def FeatureISAVersion8_0_2 : FeatureSet<
743  [FeatureVolcanicIslands,
744   FeatureLDSBankCount32,
745   FeatureSGPRInitBug,
746   FeatureUnpackedD16VMem,
747   FeatureDoesNotSupportXNACK,
748   FeatureCodeObjectV3]>;
749
750def FeatureISAVersion8_0_3 : FeatureSet<
751  [FeatureVolcanicIslands,
752   FeatureLDSBankCount32,
753   FeatureUnpackedD16VMem,
754   FeatureDoesNotSupportXNACK,
755   FeatureCodeObjectV3]>;
756
757def FeatureISAVersion8_1_0 : FeatureSet<
758  [FeatureVolcanicIslands,
759   FeatureLDSBankCount16,
760   FeatureXNACK,
761   FeatureCodeObjectV3]>;
762
763def FeatureISAVersion9_0_0 : FeatureSet<
764  [FeatureGFX9,
765   FeatureMadMixInsts,
766   FeatureLDSBankCount32,
767   FeatureCodeObjectV3,
768   FeatureDoesNotSupportXNACK,
769   FeatureDoesNotSupportSRAMECC]>;
770
771def FeatureISAVersion9_0_2 : FeatureSet<
772  [FeatureGFX9,
773   FeatureMadMixInsts,
774   FeatureLDSBankCount32,
775   FeatureXNACK,
776   FeatureDoesNotSupportSRAMECC,
777   FeatureCodeObjectV3]>;
778
779def FeatureISAVersion9_0_4 : FeatureSet<
780  [FeatureGFX9,
781   FeatureLDSBankCount32,
782   FeatureFmaMixInsts,
783   FeatureDoesNotSupportXNACK,
784   FeatureDoesNotSupportSRAMECC,
785   FeatureCodeObjectV3]>;
786
787def FeatureISAVersion9_0_6 : FeatureSet<
788  [FeatureGFX9,
789   HalfRate64Ops,
790   FeatureFmaMixInsts,
791   FeatureLDSBankCount32,
792   FeatureDLInsts,
793   FeatureDot1Insts,
794   FeatureDot2Insts,
795   FeatureDoesNotSupportXNACK,
796   FeatureCodeObjectV3]>;
797
798def FeatureISAVersion9_0_8 : FeatureSet<
799  [FeatureGFX9,
800   HalfRate64Ops,
801   FeatureFmaMixInsts,
802   FeatureLDSBankCount32,
803   FeatureDLInsts,
804   FeatureDot1Insts,
805   FeatureDot2Insts,
806   FeatureDot3Insts,
807   FeatureDot4Insts,
808   FeatureDot5Insts,
809   FeatureDot6Insts,
810   FeatureMAIInsts,
811   FeaturePkFmacF16Inst,
812   FeatureAtomicFaddInsts,
813   FeatureSRAMECC,
814   FeatureCodeObjectV3]>;
815
816def FeatureISAVersion9_0_9 : FeatureSet<
817  [FeatureGFX9,
818   FeatureMadMixInsts,
819   FeatureLDSBankCount32,
820   FeatureXNACK,
821   FeatureCodeObjectV3]>;
822
823// TODO: Organize more features into groups.
824def FeatureGroup {
825  // Bugs present on gfx10.1.
826  list<SubtargetFeature> GFX10_1_Bugs = [
827    FeatureVcmpxPermlaneHazard,
828    FeatureVMEMtoScalarWriteHazard,
829    FeatureSMEMtoVectorWriteHazard,
830    FeatureInstFwdPrefetchBug,
831    FeatureVcmpxExecWARHazard,
832    FeatureLdsBranchVmemWARHazard,
833    FeatureNSAtoVMEMBug,
834    FeatureOffset3fBug,
835    FeatureFlatSegmentOffsetBug
836   ];
837}
838
839def FeatureISAVersion10_1_0 : FeatureSet<
840  !listconcat(FeatureGroup.GFX10_1_Bugs,
841    [FeatureGFX10,
842     FeatureLDSBankCount32,
843     FeatureDLInsts,
844     FeatureNSAEncoding,
845     FeatureWavefrontSize32,
846     FeatureScalarStores,
847     FeatureScalarAtomics,
848     FeatureScalarFlatScratchInsts,
849     FeatureLdsMisalignedBug,
850     FeatureDoesNotSupportXNACK,
851     FeatureCodeObjectV3])>;
852
853def FeatureISAVersion10_1_1 : FeatureSet<
854  !listconcat(FeatureGroup.GFX10_1_Bugs,
855    [FeatureGFX10,
856     FeatureLDSBankCount32,
857     FeatureDLInsts,
858     FeatureDot1Insts,
859     FeatureDot2Insts,
860     FeatureDot5Insts,
861     FeatureDot6Insts,
862     FeatureNSAEncoding,
863     FeatureWavefrontSize32,
864     FeatureScalarStores,
865     FeatureScalarAtomics,
866     FeatureScalarFlatScratchInsts,
867     FeatureDoesNotSupportXNACK,
868     FeatureCodeObjectV3])>;
869
870def FeatureISAVersion10_1_2 : FeatureSet<
871  !listconcat(FeatureGroup.GFX10_1_Bugs,
872    [FeatureGFX10,
873     FeatureLDSBankCount32,
874     FeatureDLInsts,
875     FeatureDot1Insts,
876     FeatureDot2Insts,
877     FeatureDot5Insts,
878     FeatureDot6Insts,
879     FeatureNSAEncoding,
880     FeatureWavefrontSize32,
881     FeatureScalarStores,
882     FeatureScalarAtomics,
883     FeatureScalarFlatScratchInsts,
884     FeatureLdsMisalignedBug,
885     FeatureDoesNotSupportXNACK,
886     FeatureCodeObjectV3])>;
887
888//===----------------------------------------------------------------------===//
889
890def AMDGPUInstrInfo : InstrInfo {
891  let guessInstructionProperties = 1;
892  let noNamedPositionallyEncodedOperands = 1;
893}
894
895def AMDGPUAsmParser : AsmParser {
896  // Some of the R600 registers have the same name, so this crashes.
897  // For example T0_XYZW and T0_XY both have the asm name T0.
898  let ShouldEmitMatchRegisterName = 0;
899}
900
901def AMDGPUAsmWriter : AsmWriter {
902  int PassSubtarget = 1;
903}
904
905def AMDGPUAsmVariants {
906  string Default = "Default";
907  int Default_ID = 0;
908  string VOP3 = "VOP3";
909  int VOP3_ID = 1;
910  string SDWA = "SDWA";
911  int SDWA_ID = 2;
912  string SDWA9 = "SDWA9";
913  int SDWA9_ID = 3;
914  string DPP = "DPP";
915  int DPP_ID = 4;
916  string Disable = "Disable";
917  int Disable_ID = 5;
918}
919
920def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
921  let Variant = AMDGPUAsmVariants.Default_ID;
922  let Name = AMDGPUAsmVariants.Default;
923}
924
925def VOP3AsmParserVariant : AsmParserVariant {
926  let Variant = AMDGPUAsmVariants.VOP3_ID;
927  let Name = AMDGPUAsmVariants.VOP3;
928}
929
930def SDWAAsmParserVariant : AsmParserVariant {
931  let Variant = AMDGPUAsmVariants.SDWA_ID;
932  let Name = AMDGPUAsmVariants.SDWA;
933}
934
935def SDWA9AsmParserVariant : AsmParserVariant {
936  let Variant = AMDGPUAsmVariants.SDWA9_ID;
937  let Name = AMDGPUAsmVariants.SDWA9;
938}
939
940
941def DPPAsmParserVariant : AsmParserVariant {
942  let Variant = AMDGPUAsmVariants.DPP_ID;
943  let Name = AMDGPUAsmVariants.DPP;
944}
945
946def AMDGPU : Target {
947  // Pull in Instruction Info:
948  let InstructionSet = AMDGPUInstrInfo;
949  let AssemblyParsers = [AMDGPUAsmParser];
950  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
951                                VOP3AsmParserVariant,
952                                SDWAAsmParserVariant,
953                                SDWA9AsmParserVariant,
954                                DPPAsmParserVariant];
955  let AssemblyWriters = [AMDGPUAsmWriter];
956  let AllowRegisterRenaming = 1;
957}
958
959// Dummy Instruction itineraries for pseudo instructions
960def ALU_NULL : FuncUnit;
961def NullALU : InstrItinClass;
962
963//===----------------------------------------------------------------------===//
964// Predicate helper class
965//===----------------------------------------------------------------------===//
966
967def isGFX6 :
968  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
969  AssemblerPredicate<"FeatureSouthernIslands">;
970
971def isGFX6GFX7 :
972  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
973            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
974  AssemblerPredicate<"!FeatureGCN3Encoding,!FeatureGFX10Insts">;
975
976def isGFX6GFX7GFX10 :
977  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
978            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
979            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
980  AssemblerPredicate<"!FeatureGCN3Encoding">;
981
982def isGFX7Only :
983  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
984  AssemblerPredicate<"!FeatureGCN3Encoding,FeatureCIInsts,!FeatureGFX10Insts">;
985
986def isGFX7GFX10 :
987  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
988            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
989  AssemblerPredicate<"!FeatureGCN3Encoding,FeatureCIInsts">;
990
991def isGFX7GFX8GFX9 :
992  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
993            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
994            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
995  AssemblerPredicate<"FeatureGFX7GFX8GFX9Insts">;
996
997def isGFX6GFX7GFX8GFX9 :
998  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
999            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1000            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1001            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1002  AssemblerPredicate<"!FeatureGFX10Insts">;
1003
1004def isGFX7Plus :
1005  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1006  AssemblerPredicate<"FeatureCIInsts">;
1007
1008def isGFX8Plus :
1009  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1010  AssemblerPredicate<"FeatureGFX8Insts">;
1011
1012def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1013                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1014  AssemblerPredicate <"FeatureVolcanicIslands">;
1015
1016def isGFX9Plus :
1017  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1018  AssemblerPredicate<"FeatureGFX9Insts">;
1019
1020def isGFX9Only : Predicate <
1021  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1022  AssemblerPredicate<"FeatureGCN3Encoding,FeatureGFX9Insts">;
1023
1024def isGFX8GFX9 :
1025  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1026            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1027  AssemblerPredicate<"FeatureGFX8Insts,FeatureGCN3Encoding">;
1028
1029def isGFX10Plus :
1030  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1031  AssemblerPredicate<"FeatureGFX10Insts">;
1032
1033def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1034  AssemblerPredicate<"FeatureFlatAddressSpace">;
1035
1036def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1037  AssemblerPredicate<"FeatureFlatGlobalInsts">;
1038def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1039  AssemblerPredicate<"FeatureFlatScratchInsts">;
1040def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1041  AssemblerPredicate<"FeatureScalarFlatScratchInsts">;
1042def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1043  AssemblerPredicate<"FeatureGFX9Insts">;
1044
1045def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1046  AssemblerPredicate<"FeatureUnpackedD16VMem">;
1047def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1048  AssemblerPredicate<"!FeatureUnpackedD16VMem">;
1049
1050def D16PreservesUnusedBits :
1051  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1052  AssemblerPredicate<"FeatureGFX9Insts,!FeatureSRAMECC">;
1053
1054def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1055def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1056
1057def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1058  AssemblerPredicate<"FeatureGFX9Insts">;
1059
1060def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1061  AssemblerPredicate<"FeatureAddNoCarryInsts">;
1062
1063def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1064
1065def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1066  AssemblerPredicate<"Feature16BitInsts">;
1067def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1068  AssemblerPredicate<"FeatureVOP3P">;
1069
1070def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1071  AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
1072
1073def HasSDWA9 :
1074  Predicate<"Subtarget->hasSDWA()">,
1075  AssemblerPredicate<"FeatureGCN3Encoding,FeatureGFX9Insts,FeatureSDWA">;
1076
1077def HasSDWA10 :
1078  Predicate<"Subtarget->hasSDWA()">,
1079  AssemblerPredicate<"!FeatureGCN3Encoding,FeatureGFX10Insts,FeatureSDWA">;
1080
1081def HasDPP : Predicate<"Subtarget->hasDPP()">,
1082  AssemblerPredicate<"FeatureGCN3Encoding,FeatureDPP">;
1083
1084def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1085  AssemblerPredicate<"!FeatureGCN3Encoding,FeatureGFX10Insts,FeatureDPP8">;
1086
1087def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1088  AssemblerPredicate<"FeatureR128A16">;
1089
1090def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1091  AssemblerPredicate<"!FeatureGCN3Encoding,FeatureGFX10Insts,FeatureDPP">;
1092
1093def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1094  AssemblerPredicate<"FeatureIntClamp">;
1095
1096def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1097  AssemblerPredicate<"FeatureMadMixInsts">;
1098
1099def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1100  AssemblerPredicate<"FeatureScalarStores">;
1101
1102def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1103  AssemblerPredicate<"FeatureScalarAtomics">;
1104
1105def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1106  AssemblerPredicate<"FeatureNoSdstCMPX">;
1107
1108def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1109  AssemblerPredicate<"!FeatureNoSdstCMPX">;
1110
1111def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1112def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1113def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1114                      AssemblerPredicate<"FeatureVGPRIndexMode">;
1115def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1116                AssemblerPredicate<"FeatureMovrel">;
1117
1118def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1119  AssemblerPredicate<"FeatureFmaMixInsts">;
1120
1121def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1122  AssemblerPredicate<"FeatureDLInsts">;
1123
1124def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1125  AssemblerPredicate<"FeatureDot1Insts">;
1126
1127def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1128  AssemblerPredicate<"FeatureDot2Insts">;
1129
1130def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1131  AssemblerPredicate<"FeatureDot3Insts">;
1132
1133def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1134  AssemblerPredicate<"FeatureDot4Insts">;
1135
1136def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1137  AssemblerPredicate<"FeatureDot5Insts">;
1138
1139def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1140  AssemblerPredicate<"FeatureDot6Insts">;
1141
1142def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1143  AssemblerPredicate<"FeatureMAIInsts">;
1144
1145def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1146  AssemblerPredicate<"FeaturePkFmacF16Inst">;
1147
1148def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1149  AssemblerPredicate<"FeatureAtomicFaddInsts">;
1150
1151def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">,
1152  AssemblerPredicate<"FeatureOffset3fBug">;
1153
1154def EnableLateCFGStructurize : Predicate<
1155  "EnableLateStructurizeCFG">;
1156
1157// Include AMDGPU TD files
1158include "SISchedule.td"
1159include "GCNProcessors.td"
1160include "AMDGPUInstrInfo.td"
1161include "AMDGPURegisterInfo.td"
1162include "AMDGPURegisterBanks.td"
1163include "AMDGPUInstructions.td"
1164include "SIInstrInfo.td"
1165include "AMDGPUCallingConv.td"
1166include "AMDGPUSearchableTables.td"
1167