1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21class BoolToList<bit Value> {
22  list<int> ret = !if(Value, [1]<int>, []<int>);
23}
24
25//===------------------------------------------------------------===//
26// Subtarget Features (device properties)
27//===------------------------------------------------------------===//
28
29def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
30  "FastFMAF32",
31  "true",
32  "Assuming f32 fma is at least as fast as mul + add"
33>;
34
35def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
36  "FastDenormalF32",
37  "true",
38  "Enabling denormals does not cause f32 instructions to run at f64 rates"
39>;
40
41def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
42  "MIMG_R128",
43  "true",
44  "Support 128-bit texture resources"
45>;
46
47def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
48  "HalfRate64Ops",
49  "true",
50  "Most fp64 instructions are half rate instead of quarter"
51>;
52
53def FullRate64Ops : SubtargetFeature<"full-rate-64-ops",
54  "FullRate64Ops",
55  "true",
56  "Most fp64 instructions are full rate"
57>;
58
59def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
60  "FlatAddressSpace",
61  "true",
62  "Support flat address space"
63>;
64
65def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
66  "FlatInstOffsets",
67  "true",
68  "Flat instructions have immediate offset addressing mode"
69>;
70
71def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
72  "FlatGlobalInsts",
73  "true",
74  "Have global_* flat memory instructions"
75>;
76
77def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
78  "FlatScratchInsts",
79  "true",
80  "Have scratch_* flat memory instructions"
81>;
82
83def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
84  "ScalarFlatScratchInsts",
85  "true",
86  "Have s_scratch_* flat memory instructions"
87>;
88
89def FeatureEnableFlatScratch : SubtargetFeature<"enable-flat-scratch",
90  "EnableFlatScratch",
91  "true",
92  "Use scratch_* flat memory instructions to access scratch"
93>;
94
95def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
96  "AddNoCarryInsts",
97  "true",
98  "Have VALU add/sub instructions without carry out"
99>;
100
101def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
102  "UnalignedBufferAccess",
103  "true",
104  "Hardware supports unaligned global loads and stores"
105>;
106
107def FeatureTrapHandler: SubtargetFeature<"trap-handler",
108  "TrapHandler",
109  "true",
110  "Trap handler support"
111>;
112
113def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
114  "UnalignedScratchAccess",
115  "true",
116  "Support unaligned scratch loads and stores"
117>;
118
119def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access",
120  "UnalignedDSAccess",
121  "true",
122  "Hardware supports unaligned local and region loads and stores"
123>;
124
125def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
126  "HasApertureRegs",
127  "true",
128  "Has Memory Aperture Base and Size Registers"
129>;
130
131def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
132  "HasMadMixInsts",
133  "true",
134  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
135>;
136
137def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
138  "HasFmaMixInsts",
139  "true",
140  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
141>;
142
143def FeatureSupportsXNACK : SubtargetFeature<"xnack-support",
144  "SupportsXNACK",
145  "true",
146  "Hardware supports XNACK"
147>;
148
149// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
150// XNACK. The current default kernel driver setting is:
151// - graphics ring: XNACK disabled
152// - compute ring: XNACK enabled
153//
154// If XNACK is enabled, the VMEM latency can be worse.
155// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
156def FeatureXNACK : SubtargetFeature<"xnack",
157  "EnableXNACK",
158  "true",
159  "Enable XNACK support"
160>;
161
162def FeatureTgSplit : SubtargetFeature<"tgsplit",
163  "EnableTgSplit",
164  "true",
165  "Enable threadgroup split execution"
166>;
167
168def FeatureCuMode : SubtargetFeature<"cumode",
169  "EnableCuMode",
170  "true",
171  "Enable CU wavefront execution mode"
172>;
173
174def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
175  "SGPRInitBug",
176  "true",
177  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
178>;
179
180def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
181  "LDSMisalignedBug",
182  "true",
183  "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode"
184>;
185
186def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
187  "HasMFMAInlineLiteralBug",
188  "true",
189  "MFMA cannot use inline literal as SrcC"
190>;
191
192def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
193  "HasVcmpxPermlaneHazard",
194  "true",
195  "TODO: describe me"
196>;
197
198def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
199  "HasVMEMtoScalarWriteHazard",
200  "true",
201  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
202>;
203
204def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
205  "HasSMEMtoVectorWriteHazard",
206  "true",
207  "s_load_dword followed by v_cmp page faults"
208>;
209
210def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
211  "HasInstFwdPrefetchBug",
212  "true",
213  "S_INST_PREFETCH instruction causes shader to hang"
214>;
215
216def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
217  "HasVcmpxExecWARHazard",
218  "true",
219  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
220>;
221
222def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
223  "HasLdsBranchVmemWARHazard",
224  "true",
225  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
226>;
227
228def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
229  "HasNSAtoVMEMBug",
230  "true",
231  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
232>;
233
234def FeatureNSAClauseBug : SubtargetFeature<"nsa-clause-bug",
235  "HasNSAClauseBug",
236  "true",
237  "MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
238>;
239
240def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
241  "HasFlatSegmentOffsetBug",
242  "true",
243  "GFX10 bug where inst_offset is ignored when flat instructions access global memory"
244>;
245
246def FeatureNegativeScratchOffsetBug : SubtargetFeature<"negative-scratch-offset-bug",
247  "NegativeScratchOffsetBug",
248  "true",
249  "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9"
250>;
251
252def FeatureNegativeUnalignedScratchOffsetBug : SubtargetFeature<"negative-unaligned-scratch-offset-bug",
253  "NegativeUnalignedScratchOffsetBug",
254  "true",
255  "Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10"
256>;
257
258def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
259  "HasOffset3fBug",
260  "true",
261  "Branch offset of 3f hardware bug"
262>;
263
264def FeatureImageStoreD16Bug : SubtargetFeature<"image-store-d16-bug",
265  "HasImageStoreD16Bug",
266  "true",
267  "Image Store D16 hardware bug"
268>;
269
270def FeatureImageGather4D16Bug : SubtargetFeature<"image-gather4-d16-bug",
271  "HasImageGather4D16Bug",
272  "true",
273  "Image Gather4 D16 hardware bug"
274>;
275
276class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
277  "ldsbankcount"#Value,
278  "LDSBankCount",
279  !cast<string>(Value),
280  "The number of LDS banks per compute unit."
281>;
282
283def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
284def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
285
286def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
287  "GCN3Encoding",
288  "true",
289  "Encoding format for VI"
290>;
291
292def FeatureCIInsts : SubtargetFeature<"ci-insts",
293  "CIInsts",
294  "true",
295  "Additional instructions for CI+"
296>;
297
298def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
299  "GFX8Insts",
300  "true",
301  "Additional instructions for GFX8+"
302>;
303
304def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
305  "GFX9Insts",
306  "true",
307  "Additional instructions for GFX9+"
308>;
309
310def FeatureGFX90AInsts : SubtargetFeature<"gfx90a-insts",
311  "GFX90AInsts",
312  "true",
313  "Additional instructions for GFX90A+"
314>;
315
316def FeatureGFX940Insts : SubtargetFeature<"gfx940-insts",
317  "GFX940Insts",
318  "true",
319  "Additional instructions for GFX940+"
320>;
321
322def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
323  "GFX10Insts",
324  "true",
325  "Additional instructions for GFX10+"
326>;
327
328def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts",
329  "GFX10_3Insts",
330  "true",
331  "Additional instructions for GFX10.3"
332>;
333
334def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
335  "GFX7GFX8GFX9Insts",
336  "true",
337  "Instructions shared in GFX7, GFX8, GFX9"
338>;
339
340def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
341  "HasSMemRealTime",
342  "true",
343  "Has s_memrealtime instruction"
344>;
345
346def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
347  "HasInv2PiInlineImm",
348  "true",
349  "Has 1 / (2 * pi) as inline immediate"
350>;
351
352def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
353  "Has16BitInsts",
354  "true",
355  "Has i16/f16 instructions"
356>;
357
358def FeatureVOP3P : SubtargetFeature<"vop3p",
359  "HasVOP3PInsts",
360  "true",
361  "Has VOP3P packed instructions"
362>;
363
364def FeatureMovrel : SubtargetFeature<"movrel",
365  "HasMovrel",
366  "true",
367  "Has v_movrel*_b32 instructions"
368>;
369
370def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
371  "HasVGPRIndexMode",
372  "true",
373  "Has VGPR mode register indexing"
374>;
375
376def FeatureScalarStores : SubtargetFeature<"scalar-stores",
377  "HasScalarStores",
378  "true",
379  "Has store scalar memory instructions"
380>;
381
382def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
383  "HasScalarAtomics",
384  "true",
385  "Has atomic scalar memory instructions"
386>;
387
388def FeatureSDWA : SubtargetFeature<"sdwa",
389  "HasSDWA",
390  "true",
391  "Support SDWA (Sub-DWORD Addressing) extension"
392>;
393
394def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
395  "HasSDWAOmod",
396  "true",
397  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
398>;
399
400def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
401  "HasSDWAScalar",
402  "true",
403  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
404>;
405
406def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
407  "HasSDWASdst",
408  "true",
409  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
410>;
411
412def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
413  "HasSDWAMac",
414  "true",
415  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
416>;
417
418def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
419  "HasSDWAOutModsVOPC",
420  "true",
421  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
422>;
423
424def FeatureDPP : SubtargetFeature<"dpp",
425  "HasDPP",
426  "true",
427  "Support DPP (Data Parallel Primitives) extension"
428>;
429
430// DPP8 allows arbitrary cross-lane swizzling within groups of 8 lanes.
431def FeatureDPP8 : SubtargetFeature<"dpp8",
432  "HasDPP8",
433  "true",
434  "Support DPP8 (Data Parallel Primitives) extension"
435>;
436
437def Feature64BitDPP : SubtargetFeature<"dpp-64bit",
438  "Has64BitDPP",
439  "true",
440  "Support DPP (Data Parallel Primitives) extension"
441>;
442
443def FeaturePackedFP32Ops : SubtargetFeature<"packed-fp32-ops",
444  "HasPackedFP32Ops",
445  "true",
446  "Support packed fp32 instructions"
447>;
448
449def FeatureR128A16 : SubtargetFeature<"r128-a16",
450  "HasR128A16",
451  "true",
452  "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
453>;
454
455def FeatureGFX10A16 : SubtargetFeature<"a16",
456  "HasGFX10A16",
457  "true",
458  "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
459>;
460
461def FeatureG16 : SubtargetFeature<"g16",
462  "HasG16",
463  "true",
464  "Support G16 for 16-bit gradient image operands"
465>;
466
467def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
468  "HasNSAEncoding",
469  "true",
470  "Support NSA encoding for image instructions"
471>;
472
473def FeatureImageInsts : SubtargetFeature<"image-insts",
474  "HasImageInsts",
475  "true",
476  "Support image instructions"
477>;
478
479def FeatureExtendedImageInsts : SubtargetFeature<"extended-image-insts",
480  "HasExtendedImageInsts",
481  "true",
482  "Support mips != 0, lod != 0, gather4, and get_lod"
483>;
484
485def FeatureGFX10_AEncoding : SubtargetFeature<"gfx10_a-encoding",
486  "GFX10_AEncoding",
487  "true",
488  "Has BVH ray tracing instructions"
489>;
490
491def FeatureGFX10_BEncoding : SubtargetFeature<"gfx10_b-encoding",
492  "GFX10_BEncoding",
493  "true",
494  "Encoding format GFX10_B"
495>;
496
497def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
498  "HasIntClamp",
499  "true",
500  "Support clamp for integer destination"
501>;
502
503def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
504  "HasUnpackedD16VMem",
505  "true",
506  "Has unpacked d16 vmem instructions"
507>;
508
509def FeatureDLInsts : SubtargetFeature<"dl-insts",
510  "HasDLInsts",
511  "true",
512  "Has v_fmac_f32 and v_xnor_b32 instructions"
513>;
514
515def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
516  "HasDot1Insts",
517  "true",
518  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
519>;
520
521def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
522  "HasDot2Insts",
523  "true",
524  "Has v_dot2_i32_i16, v_dot2_u32_u16 instructions"
525>;
526
527def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
528  "HasDot3Insts",
529  "true",
530  "Has v_dot8c_i32_i4 instruction"
531>;
532
533def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
534  "HasDot4Insts",
535  "true",
536  "Has v_dot2c_i32_i16 instruction"
537>;
538
539def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
540  "HasDot5Insts",
541  "true",
542  "Has v_dot2c_f32_f16 instruction"
543>;
544
545def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
546  "HasDot6Insts",
547  "true",
548  "Has v_dot4c_i32_i8 instruction"
549>;
550
551def FeatureDot7Insts : SubtargetFeature<"dot7-insts",
552  "HasDot7Insts",
553  "true",
554  "Has v_dot2_f32_f16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
555>;
556
557def FeatureMAIInsts : SubtargetFeature<"mai-insts",
558  "HasMAIInsts",
559  "true",
560  "Has mAI instructions"
561>;
562
563def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
564  "HasPkFmacF16Inst",
565  "true",
566  "Has v_pk_fmac_f16 instruction"
567>;
568
569def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
570  "HasAtomicFaddInsts",
571  "true",
572  "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
573  "global_atomic_pk_add_f16 instructions",
574  [FeatureFlatGlobalInsts]
575>;
576
577def FeatureSupportsSRAMECC : SubtargetFeature<"sramecc-support",
578  "SupportsSRAMECC",
579  "true",
580  "Hardware supports SRAMECC"
581>;
582
583def FeatureSRAMECC : SubtargetFeature<"sramecc",
584  "EnableSRAMECC",
585  "true",
586  "Enable SRAMECC"
587>;
588
589def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
590  "HasNoSdstCMPX",
591  "true",
592  "V_CMPX does not write VCC/SGPR in addition to EXEC"
593>;
594
595def FeatureVscnt : SubtargetFeature<"vscnt",
596  "HasVscnt",
597  "true",
598  "Has separate store vscnt counter"
599>;
600
601def FeatureGetWaveIdInst : SubtargetFeature<"get-wave-id-inst",
602  "HasGetWaveIdInst",
603  "true",
604  "Has s_get_waveid_in_workgroup instruction"
605>;
606
607def FeatureSMemTimeInst : SubtargetFeature<"s-memtime-inst",
608  "HasSMemTimeInst",
609  "true",
610  "Has s_memtime instruction"
611>;
612
613def FeatureShaderCyclesRegister : SubtargetFeature<"shader-cycles-register",
614  "HasShaderCyclesRegister",
615  "true",
616  "Has SHADER_CYCLES hardware register"
617>;
618
619def FeatureMadMacF32Insts : SubtargetFeature<"mad-mac-f32-insts",
620  "HasMadMacF32Insts",
621  "true",
622  "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions"
623>;
624
625def FeatureDsSrc2Insts : SubtargetFeature<"ds-src2-insts",
626  "HasDsSrc2Insts",
627  "true",
628  "Has ds_*_src2 instructions"
629>;
630
631def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
632  "HasVOP3Literal",
633  "true",
634  "Can use one literal in VOP3"
635>;
636
637def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
638  "HasNoDataDepHazard",
639  "true",
640  "Does not need SW waitstates"
641>;
642
643class SubtargetFeatureNSAMaxSize <int Value> : SubtargetFeature <
644  "nsa-max-size-"#Value,
645  "NSAMaxSize",
646  !cast<string>(Value),
647  "The maximum non-sequential address size in VGPRs."
648>;
649
650def FeatureNSAMaxSize5 : SubtargetFeatureNSAMaxSize<5>;
651def FeatureNSAMaxSize13 : SubtargetFeatureNSAMaxSize<13>;
652
653//===------------------------------------------------------------===//
654// Subtarget Features (options and debugging)
655//===------------------------------------------------------------===//
656
657class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
658  "max-private-element-size-"#size,
659  "MaxPrivateElementSize",
660  !cast<string>(size),
661  "Maximum private access size may be "#size
662>;
663
664def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
665def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
666def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
667
668def FeatureDumpCode : SubtargetFeature <"DumpCode",
669  "DumpCode",
670  "true",
671  "Dump MachineInstrs in the CodeEmitter"
672>;
673
674def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
675  "DumpCode",
676  "true",
677  "Dump MachineInstrs in the CodeEmitter"
678>;
679
680// XXX - This should probably be removed once enabled by default
681def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
682  "EnableLoadStoreOpt",
683  "true",
684  "Enable SI load/store optimizer pass"
685>;
686
687// Performance debugging feature. Allow using DS instruction immediate
688// offsets even if the base pointer can't be proven to be base. On SI,
689// base pointer values that won't give the same result as a 16-bit add
690// are not safe to fold, but this will override the conservative test
691// for the base pointer.
692def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
693  "unsafe-ds-offset-folding",
694  "EnableUnsafeDSOffsetFolding",
695  "true",
696  "Force using DS instruction immediate offsets on SI"
697>;
698
699def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
700  "EnableSIScheduler",
701  "true",
702  "Enable SI Machine Scheduler"
703>;
704
705def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
706  "EnableDS128",
707  "true",
708  "Use ds_{read|write}_b128"
709>;
710
711// Sparse texture support requires that all result registers are zeroed when
712// PRTStrictNull is set to true. This feature is turned on for all architectures
713// but is enabled as a feature in case there are situations where PRTStrictNull
714// is disabled by the driver.
715def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
716  "EnablePRTStrictNull",
717  "true",
718  "Enable zeroing of result registers for sparse texture fetches"
719>;
720
721// Unless +-flat-for-global is specified, turn on FlatForGlobal for
722// all OS-es on VI and newer hardware to avoid assertion failures due
723// to missing ADDR64 variants of MUBUF instructions.
724// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
725// instructions.
726
727def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
728  "FlatForGlobal",
729  "true",
730  "Force to generate flat instruction for global"
731>;
732
733def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
734  "auto-waitcnt-before-barrier",
735  "AutoWaitcntBeforeBarrier",
736  "true",
737  "Hardware automatically inserts waitcnt before barrier"
738>;
739
740def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
741  "HasTrigReducedRange",
742  "true",
743  "Requires use of fract on arguments to trig instructions"
744>;
745
746// Alignment enforcement is controlled by a configuration register:
747// SH_MEM_CONFIG.alignment_mode
748def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode",
749  "UnalignedAccessMode",
750  "true",
751  "Enable unaligned global, local and region loads and stores if the hardware"
752  " supports it"
753>;
754
755def FeaturePackedTID : SubtargetFeature<"packed-tid",
756  "HasPackedTID",
757  "true",
758  "Workitem IDs are packed into v0 at kernel launch"
759>;
760
761def FeatureArchitectedFlatScratch : SubtargetFeature<"architected-flat-scratch",
762  "HasArchitectedFlatScratch",
763  "true",
764  "Flat Scratch register is a readonly SPI initialized architected register"
765>;
766
767// Dummy feature used to disable assembler instructions.
768def FeatureDisable : SubtargetFeature<"",
769  "FeatureDisable","true",
770  "Dummy feature to disable assembler instructions"
771>;
772
773class GCNSubtargetFeatureGeneration <string Value,
774                                     string FeatureName,
775                                     list<SubtargetFeature> Implies> :
776        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
777
778def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
779    "southern-islands",
780  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
781  FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,
782  FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
783  FeatureTrigReducedRange, FeatureExtendedImageInsts, FeatureImageInsts
784  ]
785>;
786
787def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
788    "sea-islands",
789  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
790  FeatureWavefrontSize64, FeatureFlatAddressSpace,
791  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
792  FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
793  FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureUnalignedBufferAccess,
794  FeatureImageInsts
795  ]
796>;
797
798def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
799  "volcanic-islands",
800  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
801   FeatureWavefrontSize64, FeatureFlatAddressSpace,
802   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
803   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
804   FeatureScalarStores, FeatureInv2PiInlineImm,
805   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
806   FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
807   FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
808   FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureFastDenormalF32,
809   FeatureUnalignedBufferAccess, FeatureImageInsts
810  ]
811>;
812
813def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
814  "gfx9",
815  [FeatureFP64, FeatureLocalMemorySize65536,
816   FeatureWavefrontSize64, FeatureFlatAddressSpace,
817   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
818   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
819   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
820   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
821   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
822   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
823   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
824   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
825   FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureSupportsXNACK,
826   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess,
827   FeatureNegativeScratchOffsetBug
828  ]
829>;
830
831def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
832  "gfx10",
833  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
834   FeatureFlatAddressSpace,
835   FeatureCIInsts, Feature16BitInsts,
836   FeatureSMemRealTime, FeatureInv2PiInlineImm,
837   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
838   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
839   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
840   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
841   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
842   FeatureNoSdstCMPX, FeatureVscnt,
843   FeatureVOP3Literal, FeatureDPP8, FeatureExtendedImageInsts,
844   FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
845   FeatureGFX10A16, FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureG16,
846   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess, FeatureImageInsts
847  ]
848>;
849
850class FeatureSet<list<SubtargetFeature> Features_> {
851  list<SubtargetFeature> Features = Features_;
852}
853
854def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
855   FeatureFastFMAF32,
856   HalfRate64Ops,
857   FeatureLDSBankCount32]>;
858
859def FeatureISAVersion6_0_1 : FeatureSet<
860  [FeatureSouthernIslands,
861   FeatureLDSBankCount32]>;
862
863def FeatureISAVersion6_0_2 : FeatureSet<
864  [FeatureSouthernIslands,
865   FeatureLDSBankCount32]>;
866
867def FeatureISAVersion7_0_0 : FeatureSet<
868  [FeatureSeaIslands,
869   FeatureLDSBankCount32]>;
870
871def FeatureISAVersion7_0_1 : FeatureSet<
872  [FeatureSeaIslands,
873   HalfRate64Ops,
874   FeatureLDSBankCount32,
875   FeatureFastFMAF32]>;
876
877def FeatureISAVersion7_0_2 : FeatureSet<
878  [FeatureSeaIslands,
879   FeatureLDSBankCount16,
880   FeatureFastFMAF32]>;
881
882def FeatureISAVersion7_0_3 : FeatureSet<
883  [FeatureSeaIslands,
884   FeatureLDSBankCount16]>;
885
886def FeatureISAVersion7_0_4 : FeatureSet<
887  [FeatureSeaIslands,
888   FeatureLDSBankCount32]>;
889
890def FeatureISAVersion7_0_5 : FeatureSet<
891  [FeatureSeaIslands,
892   FeatureLDSBankCount16]>;
893
894def FeatureISAVersion8_0_1 : FeatureSet<
895  [FeatureVolcanicIslands,
896   FeatureFastFMAF32,
897   HalfRate64Ops,
898   FeatureLDSBankCount32,
899   FeatureSupportsXNACK,
900   FeatureUnpackedD16VMem]>;
901
902def FeatureISAVersion8_0_2 : FeatureSet<
903  [FeatureVolcanicIslands,
904   FeatureLDSBankCount32,
905   FeatureSGPRInitBug,
906   FeatureUnpackedD16VMem]>;
907
908def FeatureISAVersion8_0_3 : FeatureSet<
909  [FeatureVolcanicIslands,
910   FeatureLDSBankCount32,
911   FeatureUnpackedD16VMem]>;
912
913def FeatureISAVersion8_0_5 : FeatureSet<
914  [FeatureVolcanicIslands,
915   FeatureLDSBankCount32,
916   FeatureSGPRInitBug,
917   FeatureUnpackedD16VMem]>;
918
919def FeatureISAVersion8_1_0 : FeatureSet<
920  [FeatureVolcanicIslands,
921   FeatureLDSBankCount16,
922   FeatureSupportsXNACK,
923   FeatureImageStoreD16Bug,
924   FeatureImageGather4D16Bug]>;
925
926def FeatureISAVersion9_0_0 : FeatureSet<
927  [FeatureGFX9,
928   FeatureMadMixInsts,
929   FeatureLDSBankCount32,
930   FeatureDsSrc2Insts,
931   FeatureExtendedImageInsts,
932   FeatureImageInsts,
933   FeatureMadMacF32Insts,
934   FeatureImageGather4D16Bug]>;
935
936def FeatureISAVersion9_0_2 : FeatureSet<
937  [FeatureGFX9,
938   FeatureMadMixInsts,
939   FeatureLDSBankCount32,
940   FeatureDsSrc2Insts,
941   FeatureExtendedImageInsts,
942   FeatureImageInsts,
943   FeatureMadMacF32Insts,
944   FeatureImageGather4D16Bug]>;
945
946def FeatureISAVersion9_0_4 : FeatureSet<
947  [FeatureGFX9,
948   FeatureLDSBankCount32,
949   FeatureDsSrc2Insts,
950   FeatureExtendedImageInsts,
951   FeatureImageInsts,
952   FeatureMadMacF32Insts,
953   FeatureFmaMixInsts,
954   FeatureImageGather4D16Bug]>;
955
956def FeatureISAVersion9_0_6 : FeatureSet<
957  [FeatureGFX9,
958   HalfRate64Ops,
959   FeatureFmaMixInsts,
960   FeatureLDSBankCount32,
961   FeatureDsSrc2Insts,
962   FeatureExtendedImageInsts,
963   FeatureImageInsts,
964   FeatureMadMacF32Insts,
965   FeatureDLInsts,
966   FeatureDot1Insts,
967   FeatureDot2Insts,
968   FeatureDot7Insts,
969   FeatureSupportsSRAMECC,
970   FeatureImageGather4D16Bug]>;
971
972def FeatureISAVersion9_0_8 : FeatureSet<
973  [FeatureGFX9,
974   HalfRate64Ops,
975   FeatureFmaMixInsts,
976   FeatureLDSBankCount32,
977   FeatureDsSrc2Insts,
978   FeatureExtendedImageInsts,
979   FeatureImageInsts,
980   FeatureMadMacF32Insts,
981   FeatureDLInsts,
982   FeatureDot1Insts,
983   FeatureDot2Insts,
984   FeatureDot3Insts,
985   FeatureDot4Insts,
986   FeatureDot5Insts,
987   FeatureDot6Insts,
988   FeatureDot7Insts,
989   FeatureMAIInsts,
990   FeaturePkFmacF16Inst,
991   FeatureAtomicFaddInsts,
992   FeatureSupportsSRAMECC,
993   FeatureMFMAInlineLiteralBug,
994   FeatureImageGather4D16Bug]>;
995
996def FeatureISAVersion9_0_9 : FeatureSet<
997  [FeatureGFX9,
998   FeatureMadMixInsts,
999   FeatureLDSBankCount32,
1000   FeatureDsSrc2Insts,
1001   FeatureExtendedImageInsts,
1002   FeatureImageInsts,
1003   FeatureMadMacF32Insts,
1004   FeatureImageGather4D16Bug]>;
1005
1006def FeatureISAVersion9_0_A : FeatureSet<
1007  [FeatureGFX9,
1008   FeatureGFX90AInsts,
1009   FeatureFmaMixInsts,
1010   FeatureLDSBankCount32,
1011   FeatureDLInsts,
1012   FeatureDot1Insts,
1013   FeatureDot2Insts,
1014   FeatureDot3Insts,
1015   FeatureDot4Insts,
1016   FeatureDot5Insts,
1017   FeatureDot6Insts,
1018   FeatureDot7Insts,
1019   Feature64BitDPP,
1020   FeaturePackedFP32Ops,
1021   FeatureMAIInsts,
1022   FeaturePkFmacF16Inst,
1023   FeatureAtomicFaddInsts,
1024   FeatureImageInsts,
1025   FeatureMadMacF32Insts,
1026   FeatureSupportsSRAMECC,
1027   FeaturePackedTID,
1028   FullRate64Ops]>;
1029
1030def FeatureISAVersion9_0_C : FeatureSet<
1031  [FeatureGFX9,
1032   FeatureMadMixInsts,
1033   FeatureLDSBankCount32,
1034   FeatureDsSrc2Insts,
1035   FeatureExtendedImageInsts,
1036   FeatureImageInsts,
1037   FeatureMadMacF32Insts,
1038   FeatureImageGather4D16Bug]>;
1039
1040def FeatureISAVersion9_4_0 : FeatureSet<
1041  [FeatureGFX9,
1042   FeatureGFX90AInsts,
1043   FeatureGFX940Insts,
1044   FeatureFmaMixInsts,
1045   FeatureLDSBankCount32,
1046   FeatureDLInsts,
1047   FeatureDot1Insts,
1048   FeatureDot2Insts,
1049   FeatureDot3Insts,
1050   FeatureDot4Insts,
1051   FeatureDot5Insts,
1052   FeatureDot6Insts,
1053   FeatureDot7Insts,
1054   Feature64BitDPP,
1055   FeaturePackedFP32Ops,
1056   FeatureMAIInsts,
1057   FeaturePkFmacF16Inst,
1058   FeatureAtomicFaddInsts,
1059   FeatureSupportsSRAMECC,
1060   FeaturePackedTID,
1061   FeatureArchitectedFlatScratch,
1062   FullRate64Ops]>;
1063
1064// TODO: Organize more features into groups.
1065def FeatureGroup {
1066  // Bugs present on gfx10.1.
1067  list<SubtargetFeature> GFX10_1_Bugs = [
1068    FeatureVcmpxPermlaneHazard,
1069    FeatureVMEMtoScalarWriteHazard,
1070    FeatureSMEMtoVectorWriteHazard,
1071    FeatureInstFwdPrefetchBug,
1072    FeatureVcmpxExecWARHazard,
1073    FeatureLdsBranchVmemWARHazard,
1074    FeatureNSAtoVMEMBug,
1075    FeatureNSAClauseBug,
1076    FeatureOffset3fBug,
1077    FeatureFlatSegmentOffsetBug,
1078    FeatureNegativeUnalignedScratchOffsetBug
1079   ];
1080}
1081
1082def FeatureISAVersion10_1_0 : FeatureSet<
1083  !listconcat(FeatureGroup.GFX10_1_Bugs,
1084    [FeatureGFX10,
1085     FeatureLDSBankCount32,
1086     FeatureDLInsts,
1087     FeatureNSAEncoding,
1088     FeatureNSAMaxSize5,
1089     FeatureWavefrontSize32,
1090     FeatureScalarStores,
1091     FeatureScalarAtomics,
1092     FeatureScalarFlatScratchInsts,
1093     FeatureGetWaveIdInst,
1094     FeatureMadMacF32Insts,
1095     FeatureDsSrc2Insts,
1096     FeatureLdsMisalignedBug,
1097     FeatureSupportsXNACK])>;
1098
1099def FeatureISAVersion10_1_1 : FeatureSet<
1100  !listconcat(FeatureGroup.GFX10_1_Bugs,
1101    [FeatureGFX10,
1102     FeatureLDSBankCount32,
1103     FeatureDLInsts,
1104     FeatureDot1Insts,
1105     FeatureDot2Insts,
1106     FeatureDot5Insts,
1107     FeatureDot6Insts,
1108     FeatureDot7Insts,
1109     FeatureNSAEncoding,
1110     FeatureNSAMaxSize5,
1111     FeatureWavefrontSize32,
1112     FeatureScalarStores,
1113     FeatureScalarAtomics,
1114     FeatureScalarFlatScratchInsts,
1115     FeatureGetWaveIdInst,
1116     FeatureMadMacF32Insts,
1117     FeatureDsSrc2Insts,
1118     FeatureLdsMisalignedBug,
1119     FeatureSupportsXNACK])>;
1120
1121def FeatureISAVersion10_1_2 : FeatureSet<
1122  !listconcat(FeatureGroup.GFX10_1_Bugs,
1123    [FeatureGFX10,
1124     FeatureLDSBankCount32,
1125     FeatureDLInsts,
1126     FeatureDot1Insts,
1127     FeatureDot2Insts,
1128     FeatureDot5Insts,
1129     FeatureDot6Insts,
1130     FeatureDot7Insts,
1131     FeatureNSAEncoding,
1132     FeatureNSAMaxSize5,
1133     FeatureWavefrontSize32,
1134     FeatureScalarStores,
1135     FeatureScalarAtomics,
1136     FeatureScalarFlatScratchInsts,
1137     FeatureGetWaveIdInst,
1138     FeatureMadMacF32Insts,
1139     FeatureDsSrc2Insts,
1140     FeatureLdsMisalignedBug,
1141     FeatureSupportsXNACK])>;
1142
1143def FeatureISAVersion10_1_3 : FeatureSet<
1144  !listconcat(FeatureGroup.GFX10_1_Bugs,
1145    [FeatureGFX10,
1146     FeatureGFX10_AEncoding,
1147     FeatureLDSBankCount32,
1148     FeatureDLInsts,
1149     FeatureNSAEncoding,
1150     FeatureNSAMaxSize5,
1151     FeatureWavefrontSize32,
1152     FeatureScalarStores,
1153     FeatureScalarAtomics,
1154     FeatureScalarFlatScratchInsts,
1155     FeatureGetWaveIdInst,
1156     FeatureMadMacF32Insts,
1157     FeatureDsSrc2Insts,
1158     FeatureLdsMisalignedBug,
1159     FeatureSupportsXNACK])>;
1160
1161def FeatureISAVersion10_3_0 : FeatureSet<
1162  [FeatureGFX10,
1163   FeatureGFX10_AEncoding,
1164   FeatureGFX10_BEncoding,
1165   FeatureGFX10_3Insts,
1166   FeatureLDSBankCount32,
1167   FeatureDLInsts,
1168   FeatureDot1Insts,
1169   FeatureDot2Insts,
1170   FeatureDot5Insts,
1171   FeatureDot6Insts,
1172   FeatureDot7Insts,
1173   FeatureNSAEncoding,
1174   FeatureNSAMaxSize13,
1175   FeatureWavefrontSize32,
1176   FeatureShaderCyclesRegister]>;
1177
1178//===----------------------------------------------------------------------===//
1179
1180def AMDGPUInstrInfo : InstrInfo {
1181  let guessInstructionProperties = 1;
1182  let noNamedPositionallyEncodedOperands = 1;
1183}
1184
1185def AMDGPUAsmParser : AsmParser {
1186  // Some of the R600 registers have the same name, so this crashes.
1187  // For example T0_XYZW and T0_XY both have the asm name T0.
1188  let ShouldEmitMatchRegisterName = 0;
1189}
1190
1191def AMDGPUAsmWriter : AsmWriter {
1192  int PassSubtarget = 1;
1193}
1194
1195def AMDGPUAsmVariants {
1196  string Default = "Default";
1197  int Default_ID = 0;
1198  string VOP3 = "VOP3";
1199  int VOP3_ID = 1;
1200  string SDWA = "SDWA";
1201  int SDWA_ID = 2;
1202  string SDWA9 = "SDWA9";
1203  int SDWA9_ID = 3;
1204  string DPP = "DPP";
1205  int DPP_ID = 4;
1206  string Disable = "Disable";
1207  int Disable_ID = 5;
1208}
1209
1210def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
1211  let Variant = AMDGPUAsmVariants.Default_ID;
1212  let Name = AMDGPUAsmVariants.Default;
1213}
1214
1215def VOP3AsmParserVariant : AsmParserVariant {
1216  let Variant = AMDGPUAsmVariants.VOP3_ID;
1217  let Name = AMDGPUAsmVariants.VOP3;
1218}
1219
1220def SDWAAsmParserVariant : AsmParserVariant {
1221  let Variant = AMDGPUAsmVariants.SDWA_ID;
1222  let Name = AMDGPUAsmVariants.SDWA;
1223}
1224
1225def SDWA9AsmParserVariant : AsmParserVariant {
1226  let Variant = AMDGPUAsmVariants.SDWA9_ID;
1227  let Name = AMDGPUAsmVariants.SDWA9;
1228}
1229
1230
1231def DPPAsmParserVariant : AsmParserVariant {
1232  let Variant = AMDGPUAsmVariants.DPP_ID;
1233  let Name = AMDGPUAsmVariants.DPP;
1234}
1235
1236def AMDGPU : Target {
1237  // Pull in Instruction Info:
1238  let InstructionSet = AMDGPUInstrInfo;
1239  let AssemblyParsers = [AMDGPUAsmParser];
1240  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
1241                                VOP3AsmParserVariant,
1242                                SDWAAsmParserVariant,
1243                                SDWA9AsmParserVariant,
1244                                DPPAsmParserVariant];
1245  let AssemblyWriters = [AMDGPUAsmWriter];
1246  let AllowRegisterRenaming = 1;
1247}
1248
1249// Dummy Instruction itineraries for pseudo instructions
1250def ALU_NULL : FuncUnit;
1251def NullALU : InstrItinClass;
1252
1253//===----------------------------------------------------------------------===//
1254// Predicate helper class
1255//===----------------------------------------------------------------------===//
1256
1257def isGFX6 :
1258  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1259  AssemblerPredicate<(all_of FeatureSouthernIslands)>;
1260
1261def isGFX6GFX7 :
1262  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1263            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1264  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
1265
1266def isGFX6GFX7GFX10 :
1267  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1268            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1269            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1270  AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
1271
1272def isGFX7Only :
1273  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1274  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
1275
1276def isGFX7GFX10 :
1277  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1278            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1279  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
1280
1281def isGFX7GFX8GFX9 :
1282  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1283            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1284            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1285  AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
1286
1287def isGFX6GFX7GFX8GFX9 :
1288  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1289            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1290            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1291            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1292  AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
1293
1294def isGFX6GFX7GFX8GFX9NotGFX90A :
1295  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1296            "(Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1297            " Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1298            " Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1299            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1300  AssemblerPredicate<(all_of (not FeatureGFX10Insts), (not FeatureGFX90AInsts))>;
1301
1302def isGFX7Plus :
1303  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1304  AssemblerPredicate<(all_of FeatureCIInsts)>;
1305
1306def isGFX8Plus :
1307  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1308  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1309
1310def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1311                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1312  AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1313
1314def isGFX9Plus :
1315  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1316  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1317
1318def isGFX9Only : Predicate <
1319  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1320  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1321
1322def isGCN3ExcludingGFX90A :
1323  Predicate<"Subtarget->isGCN3Encoding() && !Subtarget->hasGFX90AInsts()">,
1324  AssemblerPredicate<(all_of FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1325
1326def isGFX90APlus :
1327  Predicate<"Subtarget->hasGFX90AInsts()">,
1328  AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1329
1330def isNotGFX90APlus :
1331  Predicate<"!Subtarget->hasGFX90AInsts()">,
1332  AssemblerPredicate<(all_of (not FeatureGFX90AInsts))>;
1333
1334def isGFX8GFX9NotGFX90A :
1335  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1336            "(Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1337            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1338  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1339
1340def isGFX90AOnly :
1341  Predicate<"Subtarget->hasGFX90AInsts() && !Subtarget->hasGFX940Insts()">,
1342  AssemblerPredicate<(all_of FeatureGFX90AInsts, (not FeatureGFX940Insts))>;
1343
1344def isGFX908orGFX90A :
1345  Predicate<"Subtarget->hasMAIInsts() && !Subtarget->hasGFX940Insts()">,
1346  AssemblerPredicate<(all_of FeatureMAIInsts, (not FeatureGFX940Insts))>;
1347
1348def isGFX940Plus :
1349  Predicate<"Subtarget->hasGFX940Insts()">,
1350  AssemblerPredicate<(all_of FeatureGFX940Insts)>;
1351
1352def isGFX8GFX9NotGFX940 :
1353  Predicate<"!Subtarget->hasGFX940Insts() &&"
1354            "(Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1355            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1356  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding, (not FeatureGFX940Insts))>;
1357
1358def isGFX8GFX9 :
1359  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1360            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1361  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1362
1363def isGFX10Plus :
1364  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1365  AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1366
1367def isGFX10Before1030 :
1368  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 &&"
1369            "!Subtarget->hasGFX10_3Insts()">,
1370  AssemblerPredicate<(all_of FeatureGFX10Insts,(not FeatureGFX10_3Insts))>;
1371
1372def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1373  AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1374
1375def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1376  AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1377def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1378  AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1379def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1380  AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1381def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1382  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1383
1384def HasFlatScratchSTMode : Predicate<"Subtarget->hasFlatScratchSTMode()">,
1385  AssemblerPredicate<(any_of FeatureGFX10_3Insts, FeatureGFX940Insts)>;
1386def HasFlatScratchSVSMode : Predicate<"Subtarget->hasFlatScratchSVSMode()">,
1387  AssemblerPredicate<(any_of FeatureGFX940Insts)>;
1388
1389def HasGFX10_AEncoding : Predicate<"Subtarget->hasGFX10_AEncoding()">,
1390  AssemblerPredicate<(all_of FeatureGFX10_AEncoding)>;
1391
1392def HasGFX10_BEncoding : Predicate<"Subtarget->hasGFX10_BEncoding()">,
1393  AssemblerPredicate<(all_of FeatureGFX10_BEncoding)>;
1394
1395def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1396  AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1397def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1398  AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1399
1400def D16PreservesUnusedBits :
1401  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1402  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1403
1404def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1405def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1406
1407def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1408  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1409
1410def HasLDSFPAtomicAdd : Predicate<"Subtarget->hasLDSFPAtomicAdd()">,
1411  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1412
1413def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1414  AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1415
1416def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1417
1418def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1419  AssemblerPredicate<(all_of Feature16BitInsts)>;
1420def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1421  AssemblerPredicate<(all_of FeatureVOP3P)>;
1422
1423def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
1424def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
1425
1426def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1427  AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1428
1429def HasSDWA9 :
1430  Predicate<"Subtarget->hasSDWA()">,
1431  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1432
1433def HasSDWA10 :
1434  Predicate<"Subtarget->hasSDWA()">,
1435  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1436
1437def HasDPP : Predicate<"Subtarget->hasDPP()">,
1438  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1439
1440def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1441  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1442
1443def Has64BitDPP : Predicate<"Subtarget->has64BitDPP()">,
1444  AssemblerPredicate<(all_of Feature64BitDPP)>;
1445
1446def HasPackedFP32Ops : Predicate<"Subtarget->hasPackedFP32Ops()">,
1447  AssemblerPredicate<(all_of FeaturePackedFP32Ops)>;
1448
1449def HasFmaakFmamkF32Insts :
1450  Predicate<"Subtarget->hasFmaakFmamkF32Insts()">,
1451  AssemblerPredicate<(any_of FeatureGFX10Insts, FeatureGFX940Insts)>;
1452
1453def HasImageInsts : Predicate<"Subtarget->hasImageInsts()">,
1454  AssemblerPredicate<(all_of FeatureImageInsts)>;
1455
1456def HasExtendedImageInsts : Predicate<"Subtarget->hasExtendedImageInsts()">,
1457  AssemblerPredicate<(all_of FeatureExtendedImageInsts)>;
1458
1459def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1460  AssemblerPredicate<(all_of FeatureR128A16)>;
1461
1462def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1463  AssemblerPredicate<(all_of FeatureGFX10A16)>;
1464
1465def HasG16 : Predicate<"Subtarget->hasG16()">,
1466  AssemblerPredicate<(all_of FeatureG16)>;
1467
1468def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1469  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1470
1471def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1472  AssemblerPredicate<(all_of FeatureIntClamp)>;
1473
1474def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1475  AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1476
1477def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1478  AssemblerPredicate<(all_of FeatureScalarStores)>;
1479
1480def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1481  AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1482
1483def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1484  AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1485
1486def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1487  AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1488
1489def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1490def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1491def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1492                      AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1493def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1494                AssemblerPredicate<(all_of FeatureMovrel)>;
1495
1496def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1497  AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1498
1499def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1500  AssemblerPredicate<(all_of FeatureDLInsts)>;
1501
1502def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1503  AssemblerPredicate<(all_of FeatureDot1Insts)>;
1504
1505def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1506  AssemblerPredicate<(all_of FeatureDot2Insts)>;
1507
1508def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1509  AssemblerPredicate<(all_of FeatureDot3Insts)>;
1510
1511def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1512  AssemblerPredicate<(all_of FeatureDot4Insts)>;
1513
1514def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1515  AssemblerPredicate<(all_of FeatureDot5Insts)>;
1516
1517def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1518  AssemblerPredicate<(all_of FeatureDot6Insts)>;
1519
1520def HasDot7Insts : Predicate<"Subtarget->hasDot7Insts()">,
1521  AssemblerPredicate<(all_of FeatureDot7Insts)>;
1522
1523def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">,
1524  AssemblerPredicate<(all_of FeatureGetWaveIdInst)>;
1525
1526def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1527  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1528
1529def HasSMemRealTime : Predicate<"Subtarget->hasSMemRealTime()">,
1530  AssemblerPredicate<(all_of FeatureSMemRealTime)>;
1531
1532def HasSMemTimeInst : Predicate<"Subtarget->hasSMemTimeInst()">,
1533  AssemblerPredicate<(all_of FeatureSMemTimeInst)>;
1534
1535def HasShaderCyclesRegister : Predicate<"Subtarget->hasShaderCyclesRegister()">,
1536  AssemblerPredicate<(all_of FeatureShaderCyclesRegister)>;
1537
1538def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1539  AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1540
1541def HasMadMacF32Insts : Predicate<"Subtarget->hasMadMacF32Insts()">,
1542  AssemblerPredicate<(all_of FeatureMadMacF32Insts)>;
1543
1544def HasFmaLegacy32 : Predicate<"Subtarget->hasGFX10_3Insts()">,
1545  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1546
1547def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1548  AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>;
1549
1550def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
1551  AssemblerPredicate<(all_of FeatureDsSrc2Insts)>;
1552
1553def EnableLateCFGStructurize : Predicate<
1554  "EnableLateStructurizeCFG">;
1555
1556def EnableFlatScratch : Predicate<"Subtarget->enableFlatScratch()">;
1557
1558def DisableFlatScratch : Predicate<"!Subtarget->enableFlatScratch()">;
1559
1560def HasUnalignedAccessMode : Predicate<"Subtarget->hasUnalignedAccessMode()">,
1561  AssemblerPredicate<(all_of FeatureUnalignedAccessMode)>;
1562
1563// Include AMDGPU TD files
1564include "SISchedule.td"
1565include "GCNProcessors.td"
1566include "AMDGPUInstrInfo.td"
1567include "SIRegisterInfo.td"
1568include "AMDGPURegisterBanks.td"
1569include "AMDGPUInstructions.td"
1570include "SIInstrInfo.td"
1571include "AMDGPUCallingConv.td"
1572include "AMDGPUSearchableTables.td"
1573