1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21
22class BoolToList<bit Value> {
23  list<int> ret = !if(Value, [1]<int>, []<int>);
24}
25
26//===------------------------------------------------------------===//
27// Subtarget Features (device properties)
28//===------------------------------------------------------------===//
29
30def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
31  "FastFMAF32",
32  "true",
33  "Assuming f32 fma is at least as fast as mul + add"
34>;
35
36def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
37  "MIMG_R128",
38  "true",
39  "Support 128-bit texture resources"
40>;
41
42def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
43  "HalfRate64Ops",
44  "true",
45  "Most fp64 instructions are half rate instead of quarter"
46>;
47
48def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
49  "FlatAddressSpace",
50  "true",
51  "Support flat address space"
52>;
53
54def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
55  "FlatInstOffsets",
56  "true",
57  "Flat instructions have immediate offset addressing mode"
58>;
59
60def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
61  "FlatGlobalInsts",
62  "true",
63  "Have global_* flat memory instructions"
64>;
65
66def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
67  "FlatScratchInsts",
68  "true",
69  "Have scratch_* flat memory instructions"
70>;
71
72def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
73  "ScalarFlatScratchInsts",
74  "true",
75  "Have s_scratch_* flat memory instructions"
76>;
77
78def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
79  "AddNoCarryInsts",
80  "true",
81  "Have VALU add/sub instructions without carry out"
82>;
83
84def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
85  "UnalignedBufferAccess",
86  "true",
87  "Support unaligned global loads and stores"
88>;
89
90def FeatureTrapHandler: SubtargetFeature<"trap-handler",
91  "TrapHandler",
92  "true",
93  "Trap handler support"
94>;
95
96def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
97  "UnalignedScratchAccess",
98  "true",
99  "Support unaligned scratch loads and stores"
100>;
101
102def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
103  "HasApertureRegs",
104  "true",
105  "Has Memory Aperture Base and Size Registers"
106>;
107
108def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
109  "HasMadMixInsts",
110  "true",
111  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
112>;
113
114def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
115  "HasFmaMixInsts",
116  "true",
117  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
118>;
119
120def FeatureDoesNotSupportXNACK : SubtargetFeature<"no-xnack-support",
121  "DoesNotSupportXNACK",
122  "true",
123  "Hardware does not support XNACK"
124>;
125
126// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
127// XNACK. The current default kernel driver setting is:
128// - graphics ring: XNACK disabled
129// - compute ring: XNACK enabled
130//
131// If XNACK is enabled, the VMEM latency can be worse.
132// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
133def FeatureXNACK : SubtargetFeature<"xnack",
134  "EnableXNACK",
135  "true",
136  "Enable XNACK support"
137>;
138
139def FeatureCuMode : SubtargetFeature<"cumode",
140  "EnableCuMode",
141  "true",
142  "Enable CU wavefront execution mode"
143>;
144
145def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
146  "SGPRInitBug",
147  "true",
148  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
149>;
150
151def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
152  "LDSMisalignedBug",
153  "true",
154  "Some GFX10 bug with misaligned multi-dword LDS access in WGP mode"
155>;
156
157def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
158  "HasMFMAInlineLiteralBug",
159  "true",
160  "MFMA cannot use inline literal as SrcC"
161>;
162
163def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
164  "HasVcmpxPermlaneHazard",
165  "true",
166  "TODO: describe me"
167>;
168
169def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
170  "HasVMEMtoScalarWriteHazard",
171  "true",
172  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
173>;
174
175def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
176  "HasSMEMtoVectorWriteHazard",
177  "true",
178  "s_load_dword followed by v_cmp page faults"
179>;
180
181def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
182  "HasInstFwdPrefetchBug",
183  "true",
184  "S_INST_PREFETCH instruction causes shader to hang"
185>;
186
187def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
188  "HasVcmpxExecWARHazard",
189  "true",
190  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
191>;
192
193def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
194  "HasLdsBranchVmemWARHazard",
195  "true",
196  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
197>;
198
199def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
200  "HasNSAtoVMEMBug",
201  "true",
202  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
203>;
204
205def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
206  "HasFlatSegmentOffsetBug",
207  "true",
208  "GFX10 bug, inst_offset ignored in flat segment"
209>;
210
211def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
212  "HasOffset3fBug",
213  "true",
214  "Branch offset of 3f hardware bug"
215>;
216
217class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
218  "ldsbankcount"#Value,
219  "LDSBankCount",
220  !cast<string>(Value),
221  "The number of LDS banks per compute unit."
222>;
223
224def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
225def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
226
227def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
228  "GCN3Encoding",
229  "true",
230  "Encoding format for VI"
231>;
232
233def FeatureCIInsts : SubtargetFeature<"ci-insts",
234  "CIInsts",
235  "true",
236  "Additional instructions for CI+"
237>;
238
239def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
240  "GFX8Insts",
241  "true",
242  "Additional instructions for GFX8+"
243>;
244
245def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
246  "GFX9Insts",
247  "true",
248  "Additional instructions for GFX9+"
249>;
250
251def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
252  "GFX10Insts",
253  "true",
254  "Additional instructions for GFX10+"
255>;
256
257def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
258  "GFX7GFX8GFX9Insts",
259  "true",
260  "Instructions shared in GFX7, GFX8, GFX9"
261>;
262
263def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
264  "HasSMemRealTime",
265  "true",
266  "Has s_memrealtime instruction"
267>;
268
269def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
270  "HasInv2PiInlineImm",
271  "true",
272  "Has 1 / (2 * pi) as inline immediate"
273>;
274
275def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
276  "Has16BitInsts",
277  "true",
278  "Has i16/f16 instructions"
279>;
280
281def FeatureVOP3P : SubtargetFeature<"vop3p",
282  "HasVOP3PInsts",
283  "true",
284  "Has VOP3P packed instructions"
285>;
286
287def FeatureMovrel : SubtargetFeature<"movrel",
288  "HasMovrel",
289  "true",
290  "Has v_movrel*_b32 instructions"
291>;
292
293def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
294  "HasVGPRIndexMode",
295  "true",
296  "Has VGPR mode register indexing"
297>;
298
299def FeatureScalarStores : SubtargetFeature<"scalar-stores",
300  "HasScalarStores",
301  "true",
302  "Has store scalar memory instructions"
303>;
304
305def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
306  "HasScalarAtomics",
307  "true",
308  "Has atomic scalar memory instructions"
309>;
310
311def FeatureSDWA : SubtargetFeature<"sdwa",
312  "HasSDWA",
313  "true",
314  "Support SDWA (Sub-DWORD Addressing) extension"
315>;
316
317def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
318  "HasSDWAOmod",
319  "true",
320  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
321>;
322
323def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
324  "HasSDWAScalar",
325  "true",
326  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
327>;
328
329def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
330  "HasSDWASdst",
331  "true",
332  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
333>;
334
335def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
336  "HasSDWAMac",
337  "true",
338  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
339>;
340
341def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
342  "HasSDWAOutModsVOPC",
343  "true",
344  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
345>;
346
347def FeatureDPP : SubtargetFeature<"dpp",
348  "HasDPP",
349  "true",
350  "Support DPP (Data Parallel Primitives) extension"
351>;
352
353// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
354def FeatureDPP8 : SubtargetFeature<"dpp8",
355  "HasDPP8",
356  "true",
357  "Support DPP8 (Data Parallel Primitives) extension"
358>;
359
360def FeatureR128A16 : SubtargetFeature<"r128-a16",
361  "HasR128A16",
362  "true",
363  "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
364>;
365
366def FeatureGFX10A16 : SubtargetFeature<"a16",
367  "HasGFX10A16",
368  "true",
369  "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
370>;
371
372def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
373  "HasNSAEncoding",
374  "true",
375  "Support NSA encoding for image instructions"
376>;
377
378def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
379  "HasIntClamp",
380  "true",
381  "Support clamp for integer destination"
382>;
383
384def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
385  "HasUnpackedD16VMem",
386  "true",
387  "Has unpacked d16 vmem instructions"
388>;
389
390def FeatureDLInsts : SubtargetFeature<"dl-insts",
391  "HasDLInsts",
392  "true",
393  "Has v_fmac_f32 and v_xnor_b32 instructions"
394>;
395
396def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
397  "HasDot1Insts",
398  "true",
399  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
400>;
401
402def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
403  "HasDot2Insts",
404  "true",
405  "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
406>;
407
408def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
409  "HasDot3Insts",
410  "true",
411  "Has v_dot8c_i32_i4 instruction"
412>;
413
414def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
415  "HasDot4Insts",
416  "true",
417  "Has v_dot2c_i32_i16 instruction"
418>;
419
420def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
421  "HasDot5Insts",
422  "true",
423  "Has v_dot2c_f32_f16 instruction"
424>;
425
426def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
427  "HasDot6Insts",
428  "true",
429  "Has v_dot4c_i32_i8 instruction"
430>;
431
432def FeatureMAIInsts : SubtargetFeature<"mai-insts",
433  "HasMAIInsts",
434  "true",
435  "Has mAI instructions"
436>;
437
438def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
439  "HasPkFmacF16Inst",
440  "true",
441  "Has v_pk_fmac_f16 instruction"
442>;
443
444def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
445  "HasAtomicFaddInsts",
446  "true",
447  "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
448  "global_atomic_pk_add_f16 instructions"
449>;
450
451def FeatureDoesNotSupportSRAMECC : SubtargetFeature<"no-sram-ecc-support",
452  "DoesNotSupportSRAMECC",
453  "true",
454  "Hardware does not support SRAM ECC"
455>;
456
457def FeatureSRAMECC : SubtargetFeature<"sram-ecc",
458  "EnableSRAMECC",
459  "true",
460  "Enable SRAM ECC"
461>;
462
463def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
464  "HasNoSdstCMPX",
465  "true",
466  "V_CMPX does not write VCC/SGPR in addition to EXEC"
467>;
468
469def FeatureVscnt : SubtargetFeature<"vscnt",
470  "HasVscnt",
471  "true",
472  "Has separate store vscnt counter"
473>;
474
475def FeatureRegisterBanking : SubtargetFeature<"register-banking",
476  "HasRegisterBanking",
477  "true",
478  "Has register banking"
479>;
480
481def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
482  "HasVOP3Literal",
483  "true",
484  "Can use one literal in VOP3"
485>;
486
487def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
488  "HasNoDataDepHazard",
489  "true",
490  "Does not need SW waitstates"
491>;
492
493//===------------------------------------------------------------===//
494// Subtarget Features (options and debugging)
495//===------------------------------------------------------------===//
496
497// Denormal handling for fp64 and fp16 is controlled by the same
498// config register when fp16 supported.
499// TODO: Do we need a separate f16 setting when not legal?
500def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
501  "FP64FP16Denormals",
502  "true",
503  "Enable double and half precision denormal handling",
504  [FeatureFP64]
505>;
506
507def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
508  "FP64FP16Denormals",
509  "true",
510  "Enable double and half precision denormal handling",
511  [FeatureFP64, FeatureFP64FP16Denormals]
512>;
513
514def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
515  "FP64FP16Denormals",
516  "true",
517  "Enable half precision denormal handling",
518  [FeatureFP64FP16Denormals]
519>;
520
521def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
522  "FPExceptions",
523  "true",
524  "Enable floating point exceptions"
525>;
526
527class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
528  "max-private-element-size-"#size,
529  "MaxPrivateElementSize",
530  !cast<string>(size),
531  "Maximum private access size may be "#size
532>;
533
534def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
535def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
536def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
537
538def FeatureDumpCode : SubtargetFeature <"DumpCode",
539  "DumpCode",
540  "true",
541  "Dump MachineInstrs in the CodeEmitter"
542>;
543
544def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
545  "DumpCode",
546  "true",
547  "Dump MachineInstrs in the CodeEmitter"
548>;
549
550// XXX - This should probably be removed once enabled by default
551def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
552  "EnableLoadStoreOpt",
553  "true",
554  "Enable SI load/store optimizer pass"
555>;
556
557// Performance debugging feature. Allow using DS instruction immediate
558// offsets even if the base pointer can't be proven to be base. On SI,
559// base pointer values that won't give the same result as a 16-bit add
560// are not safe to fold, but this will override the conservative test
561// for the base pointer.
562def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
563  "unsafe-ds-offset-folding",
564  "EnableUnsafeDSOffsetFolding",
565  "true",
566  "Force using DS instruction immediate offsets on SI"
567>;
568
569def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
570  "EnableSIScheduler",
571  "true",
572  "Enable SI Machine Scheduler"
573>;
574
575def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
576  "EnableDS128",
577  "true",
578  "Use ds_{read|write}_b128"
579>;
580
581// Sparse texture support requires that all result registers are zeroed when
582// PRTStrictNull is set to true. This feature is turned on for all architectures
583// but is enabled as a feature in case there are situations where PRTStrictNull
584// is disabled by the driver.
585def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
586  "EnablePRTStrictNull",
587  "true",
588  "Enable zeroing of result registers for sparse texture fetches"
589>;
590
591// Unless +-flat-for-global is specified, turn on FlatForGlobal for
592// all OS-es on VI and newer hardware to avoid assertion failures due
593// to missing ADDR64 variants of MUBUF instructions.
594// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
595// instructions.
596
597def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
598  "FlatForGlobal",
599  "true",
600  "Force to generate flat instruction for global"
601>;
602
603def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
604  "auto-waitcnt-before-barrier",
605  "AutoWaitcntBeforeBarrier",
606  "true",
607  "Hardware automatically inserts waitcnt before barrier"
608>;
609
610def FeatureCodeObjectV3 : SubtargetFeature <
611  "code-object-v3",
612  "CodeObjectV3",
613  "true",
614  "Generate code object version 3"
615>;
616
617def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
618  "HasTrigReducedRange",
619  "true",
620  "Requires use of fract on arguments to trig instructions"
621>;
622
623// Dummy feature used to disable assembler instructions.
624def FeatureDisable : SubtargetFeature<"",
625  "FeatureDisable","true",
626  "Dummy feature to disable assembler instructions"
627>;
628
629class GCNSubtargetFeatureGeneration <string Value,
630                                     string FeatureName,
631                                     list<SubtargetFeature> Implies> :
632        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
633
634def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
635    "southern-islands",
636  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
637  FeatureWavefrontSize64,
638  FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange,
639  FeatureDoesNotSupportSRAMECC, FeatureDoesNotSupportXNACK]
640>;
641
642def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
643    "sea-islands",
644  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
645  FeatureWavefrontSize64, FeatureFlatAddressSpace,
646  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
647  FeatureGFX7GFX8GFX9Insts, FeatureDoesNotSupportSRAMECC]
648>;
649
650def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
651  "volcanic-islands",
652  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
653   FeatureWavefrontSize64, FeatureFlatAddressSpace,
654   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
655   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
656   FeatureScalarStores, FeatureInv2PiInlineImm,
657   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
658   FeatureIntClamp, FeatureTrigReducedRange, FeatureDoesNotSupportSRAMECC,
659   FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts
660  ]
661>;
662
663def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
664  "gfx9",
665  [FeatureFP64, FeatureLocalMemorySize65536,
666   FeatureWavefrontSize64, FeatureFlatAddressSpace,
667   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
668   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
669   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
670   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
671   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
672   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
673   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
674   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16
675  ]
676>;
677
678def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
679  "gfx10",
680  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
681   FeatureFlatAddressSpace,
682   FeatureCIInsts, Feature16BitInsts,
683   FeatureSMemRealTime, FeatureInv2PiInlineImm,
684   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
685   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
686   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
687   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
688   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
689   FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
690   FeatureVOP3Literal, FeatureDPP8,
691   FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureDoesNotSupportSRAMECC,
692   FeatureGFX10A16
693  ]
694>;
695
696class FeatureSet<list<SubtargetFeature> Features_> {
697  list<SubtargetFeature> Features = Features_;
698}
699
700def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
701   FeatureFastFMAF32,
702   HalfRate64Ops,
703   FeatureLDSBankCount32,
704   FeatureDoesNotSupportXNACK,
705   FeatureCodeObjectV3]>;
706
707def FeatureISAVersion6_0_1 : FeatureSet<
708  [FeatureSouthernIslands,
709   FeatureLDSBankCount32,
710   FeatureDoesNotSupportXNACK,
711   FeatureCodeObjectV3]>;
712
713def FeatureISAVersion7_0_0 : FeatureSet<
714  [FeatureSeaIslands,
715   FeatureLDSBankCount32,
716   FeatureDoesNotSupportXNACK,
717   FeatureCodeObjectV3]>;
718
719def FeatureISAVersion7_0_1 : FeatureSet<
720  [FeatureSeaIslands,
721   HalfRate64Ops,
722   FeatureLDSBankCount32,
723   FeatureFastFMAF32,
724   FeatureDoesNotSupportXNACK,
725   FeatureCodeObjectV3]>;
726
727def FeatureISAVersion7_0_2 : FeatureSet<
728  [FeatureSeaIslands,
729   FeatureLDSBankCount16,
730   FeatureFastFMAF32,
731   FeatureDoesNotSupportXNACK,
732   FeatureCodeObjectV3]>;
733
734def FeatureISAVersion7_0_3 : FeatureSet<
735  [FeatureSeaIslands,
736   FeatureLDSBankCount16,
737   FeatureDoesNotSupportXNACK,
738   FeatureCodeObjectV3]>;
739
740def FeatureISAVersion7_0_4 : FeatureSet<
741  [FeatureSeaIslands,
742   FeatureLDSBankCount32,
743   FeatureDoesNotSupportXNACK,
744   FeatureCodeObjectV3]>;
745
746def FeatureISAVersion8_0_1 : FeatureSet<
747  [FeatureVolcanicIslands,
748   FeatureFastFMAF32,
749   HalfRate64Ops,
750   FeatureLDSBankCount32,
751   FeatureXNACK,
752   FeatureUnpackedD16VMem,
753   FeatureCodeObjectV3]>;
754
755def FeatureISAVersion8_0_2 : FeatureSet<
756  [FeatureVolcanicIslands,
757   FeatureLDSBankCount32,
758   FeatureSGPRInitBug,
759   FeatureUnpackedD16VMem,
760   FeatureDoesNotSupportXNACK,
761   FeatureCodeObjectV3]>;
762
763def FeatureISAVersion8_0_3 : FeatureSet<
764  [FeatureVolcanicIslands,
765   FeatureLDSBankCount32,
766   FeatureUnpackedD16VMem,
767   FeatureDoesNotSupportXNACK,
768   FeatureCodeObjectV3]>;
769
770def FeatureISAVersion8_1_0 : FeatureSet<
771  [FeatureVolcanicIslands,
772   FeatureLDSBankCount16,
773   FeatureXNACK,
774   FeatureCodeObjectV3]>;
775
776def FeatureISAVersion9_0_0 : FeatureSet<
777  [FeatureGFX9,
778   FeatureMadMixInsts,
779   FeatureLDSBankCount32,
780   FeatureCodeObjectV3,
781   FeatureDoesNotSupportXNACK,
782   FeatureDoesNotSupportSRAMECC]>;
783
784def FeatureISAVersion9_0_2 : FeatureSet<
785  [FeatureGFX9,
786   FeatureMadMixInsts,
787   FeatureLDSBankCount32,
788   FeatureXNACK,
789   FeatureDoesNotSupportSRAMECC,
790   FeatureCodeObjectV3]>;
791
792def FeatureISAVersion9_0_4 : FeatureSet<
793  [FeatureGFX9,
794   FeatureLDSBankCount32,
795   FeatureFmaMixInsts,
796   FeatureDoesNotSupportXNACK,
797   FeatureDoesNotSupportSRAMECC,
798   FeatureCodeObjectV3]>;
799
800def FeatureISAVersion9_0_6 : FeatureSet<
801  [FeatureGFX9,
802   HalfRate64Ops,
803   FeatureFmaMixInsts,
804   FeatureLDSBankCount32,
805   FeatureDLInsts,
806   FeatureDot1Insts,
807   FeatureDot2Insts,
808   FeatureDoesNotSupportXNACK,
809   FeatureCodeObjectV3]>;
810
811def FeatureISAVersion9_0_8 : FeatureSet<
812  [FeatureGFX9,
813   HalfRate64Ops,
814   FeatureFmaMixInsts,
815   FeatureLDSBankCount32,
816   FeatureDLInsts,
817   FeatureDot1Insts,
818   FeatureDot2Insts,
819   FeatureDot3Insts,
820   FeatureDot4Insts,
821   FeatureDot5Insts,
822   FeatureDot6Insts,
823   FeatureMAIInsts,
824   FeaturePkFmacF16Inst,
825   FeatureAtomicFaddInsts,
826   FeatureSRAMECC,
827   FeatureMFMAInlineLiteralBug,
828   FeatureCodeObjectV3]>;
829
830def FeatureISAVersion9_0_9 : FeatureSet<
831  [FeatureGFX9,
832   FeatureMadMixInsts,
833   FeatureLDSBankCount32,
834   FeatureXNACK,
835   FeatureCodeObjectV3]>;
836
837// TODO: Organize more features into groups.
838def FeatureGroup {
839  // Bugs present on gfx10.1.
840  list<SubtargetFeature> GFX10_1_Bugs = [
841    FeatureVcmpxPermlaneHazard,
842    FeatureVMEMtoScalarWriteHazard,
843    FeatureSMEMtoVectorWriteHazard,
844    FeatureInstFwdPrefetchBug,
845    FeatureVcmpxExecWARHazard,
846    FeatureLdsBranchVmemWARHazard,
847    FeatureNSAtoVMEMBug,
848    FeatureOffset3fBug,
849    FeatureFlatSegmentOffsetBug
850   ];
851}
852
853def FeatureISAVersion10_1_0 : FeatureSet<
854  !listconcat(FeatureGroup.GFX10_1_Bugs,
855    [FeatureGFX10,
856     FeatureLDSBankCount32,
857     FeatureDLInsts,
858     FeatureNSAEncoding,
859     FeatureWavefrontSize32,
860     FeatureScalarStores,
861     FeatureScalarAtomics,
862     FeatureScalarFlatScratchInsts,
863     FeatureLdsMisalignedBug,
864     FeatureDoesNotSupportXNACK,
865     FeatureCodeObjectV3])>;
866
867def FeatureISAVersion10_1_1 : FeatureSet<
868  !listconcat(FeatureGroup.GFX10_1_Bugs,
869    [FeatureGFX10,
870     FeatureLDSBankCount32,
871     FeatureDLInsts,
872     FeatureDot1Insts,
873     FeatureDot2Insts,
874     FeatureDot5Insts,
875     FeatureDot6Insts,
876     FeatureNSAEncoding,
877     FeatureWavefrontSize32,
878     FeatureScalarStores,
879     FeatureScalarAtomics,
880     FeatureScalarFlatScratchInsts,
881     FeatureDoesNotSupportXNACK,
882     FeatureCodeObjectV3])>;
883
884def FeatureISAVersion10_1_2 : FeatureSet<
885  !listconcat(FeatureGroup.GFX10_1_Bugs,
886    [FeatureGFX10,
887     FeatureLDSBankCount32,
888     FeatureDLInsts,
889     FeatureDot1Insts,
890     FeatureDot2Insts,
891     FeatureDot5Insts,
892     FeatureDot6Insts,
893     FeatureNSAEncoding,
894     FeatureWavefrontSize32,
895     FeatureScalarStores,
896     FeatureScalarAtomics,
897     FeatureScalarFlatScratchInsts,
898     FeatureLdsMisalignedBug,
899     FeatureDoesNotSupportXNACK,
900     FeatureCodeObjectV3])>;
901
902//===----------------------------------------------------------------------===//
903
904def AMDGPUInstrInfo : InstrInfo {
905  let guessInstructionProperties = 1;
906  let noNamedPositionallyEncodedOperands = 1;
907}
908
909def AMDGPUAsmParser : AsmParser {
910  // Some of the R600 registers have the same name, so this crashes.
911  // For example T0_XYZW and T0_XY both have the asm name T0.
912  let ShouldEmitMatchRegisterName = 0;
913}
914
915def AMDGPUAsmWriter : AsmWriter {
916  int PassSubtarget = 1;
917}
918
919def AMDGPUAsmVariants {
920  string Default = "Default";
921  int Default_ID = 0;
922  string VOP3 = "VOP3";
923  int VOP3_ID = 1;
924  string SDWA = "SDWA";
925  int SDWA_ID = 2;
926  string SDWA9 = "SDWA9";
927  int SDWA9_ID = 3;
928  string DPP = "DPP";
929  int DPP_ID = 4;
930  string Disable = "Disable";
931  int Disable_ID = 5;
932}
933
934def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
935  let Variant = AMDGPUAsmVariants.Default_ID;
936  let Name = AMDGPUAsmVariants.Default;
937}
938
939def VOP3AsmParserVariant : AsmParserVariant {
940  let Variant = AMDGPUAsmVariants.VOP3_ID;
941  let Name = AMDGPUAsmVariants.VOP3;
942}
943
944def SDWAAsmParserVariant : AsmParserVariant {
945  let Variant = AMDGPUAsmVariants.SDWA_ID;
946  let Name = AMDGPUAsmVariants.SDWA;
947}
948
949def SDWA9AsmParserVariant : AsmParserVariant {
950  let Variant = AMDGPUAsmVariants.SDWA9_ID;
951  let Name = AMDGPUAsmVariants.SDWA9;
952}
953
954
955def DPPAsmParserVariant : AsmParserVariant {
956  let Variant = AMDGPUAsmVariants.DPP_ID;
957  let Name = AMDGPUAsmVariants.DPP;
958}
959
960def AMDGPU : Target {
961  // Pull in Instruction Info:
962  let InstructionSet = AMDGPUInstrInfo;
963  let AssemblyParsers = [AMDGPUAsmParser];
964  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
965                                VOP3AsmParserVariant,
966                                SDWAAsmParserVariant,
967                                SDWA9AsmParserVariant,
968                                DPPAsmParserVariant];
969  let AssemblyWriters = [AMDGPUAsmWriter];
970  let AllowRegisterRenaming = 1;
971}
972
973// Dummy Instruction itineraries for pseudo instructions
974def ALU_NULL : FuncUnit;
975def NullALU : InstrItinClass;
976
977//===----------------------------------------------------------------------===//
978// Predicate helper class
979//===----------------------------------------------------------------------===//
980
981def isGFX6 :
982  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
983  AssemblerPredicate<(all_of FeatureSouthernIslands)>;
984
985def isGFX6GFX7 :
986  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
987            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
988  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
989
990def isGFX6GFX7GFX10 :
991  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
992            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
993            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
994  AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
995
996def isGFX7Only :
997  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
998  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
999
1000def isGFX7GFX10 :
1001  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1002            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1003  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
1004
1005def isGFX7GFX8GFX9 :
1006  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1007            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1008            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1009  AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
1010
1011def isGFX6GFX7GFX8GFX9 :
1012  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1013            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1014            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1015            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1016  AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
1017
1018def isGFX7Plus :
1019  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1020  AssemblerPredicate<(all_of FeatureCIInsts)>;
1021
1022def isGFX8Plus :
1023  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1024  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1025
1026def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1027                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1028  AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1029
1030def isGFX9Plus :
1031  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1032  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1033
1034def isGFX9Only : Predicate <
1035  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1036  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1037
1038def isGFX8GFX9 :
1039  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1040            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1041  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1042
1043def isGFX10Plus :
1044  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1045  AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1046
1047def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1048  AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1049
1050def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1051  AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1052def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1053  AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1054def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1055  AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1056def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1057  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1058
1059def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1060  AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1061def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1062  AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1063
1064def D16PreservesUnusedBits :
1065  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1066  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1067
1068def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1069def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1070
1071def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1072  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1073
1074def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1075  AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1076
1077def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1078
1079def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1080  AssemblerPredicate<(all_of Feature16BitInsts)>;
1081def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1082  AssemblerPredicate<(all_of FeatureVOP3P)>;
1083
1084def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1085  AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1086
1087def HasSDWA9 :
1088  Predicate<"Subtarget->hasSDWA()">,
1089  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1090
1091def HasSDWA10 :
1092  Predicate<"Subtarget->hasSDWA()">,
1093  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1094
1095def HasDPP : Predicate<"Subtarget->hasDPP()">,
1096  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1097
1098def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1099  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1100
1101def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1102  AssemblerPredicate<(all_of FeatureR128A16)>;
1103
1104def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1105  AssemblerPredicate<(all_of FeatureGFX10A16)>;
1106
1107def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1108  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1109
1110def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1111  AssemblerPredicate<(all_of FeatureIntClamp)>;
1112
1113def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1114  AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1115
1116def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1117  AssemblerPredicate<(all_of FeatureScalarStores)>;
1118
1119def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1120  AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1121
1122def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1123  AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1124
1125def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1126  AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1127
1128def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1129def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1130def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1131                      AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1132def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1133                AssemblerPredicate<(all_of FeatureMovrel)>;
1134
1135def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1136  AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1137
1138def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1139  AssemblerPredicate<(all_of FeatureDLInsts)>;
1140
1141def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1142  AssemblerPredicate<(all_of FeatureDot1Insts)>;
1143
1144def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1145  AssemblerPredicate<(all_of FeatureDot2Insts)>;
1146
1147def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1148  AssemblerPredicate<(all_of FeatureDot3Insts)>;
1149
1150def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1151  AssemblerPredicate<(all_of FeatureDot4Insts)>;
1152
1153def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1154  AssemblerPredicate<(all_of FeatureDot5Insts)>;
1155
1156def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1157  AssemblerPredicate<(all_of FeatureDot6Insts)>;
1158
1159def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1160  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1161
1162def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1163  AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1164
1165def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1166  AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>;
1167
1168def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">,
1169  AssemblerPredicate<(all_of FeatureOffset3fBug)>;
1170
1171def EnableLateCFGStructurize : Predicate<
1172  "EnableLateStructurizeCFG">;
1173
1174// Include AMDGPU TD files
1175include "SISchedule.td"
1176include "GCNProcessors.td"
1177include "AMDGPUInstrInfo.td"
1178include "SIRegisterInfo.td"
1179include "AMDGPURegisterBanks.td"
1180include "AMDGPUInstructions.td"
1181include "SIInstrInfo.td"
1182include "AMDGPUCallingConv.td"
1183include "AMDGPUSearchableTables.td"
1184