1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21
22class BoolToList<bit Value> {
23  list<int> ret = !if(Value, [1]<int>, []<int>);
24}
25
26//===------------------------------------------------------------===//
27// Subtarget Features (device properties)
28//===------------------------------------------------------------===//
29
30def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
31  "FastFMAF32",
32  "true",
33  "Assuming f32 fma is at least as fast as mul + add"
34>;
35
36def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
37  "FastDenormalF32",
38  "true",
39  "Enabling denormals does not cause f32 instructions to run at f64 rates"
40>;
41
42def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
43  "MIMG_R128",
44  "true",
45  "Support 128-bit texture resources"
46>;
47
48def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
49  "HalfRate64Ops",
50  "true",
51  "Most fp64 instructions are half rate instead of quarter"
52>;
53
54def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
55  "FlatAddressSpace",
56  "true",
57  "Support flat address space"
58>;
59
60def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
61  "FlatInstOffsets",
62  "true",
63  "Flat instructions have immediate offset addressing mode"
64>;
65
66def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
67  "FlatGlobalInsts",
68  "true",
69  "Have global_* flat memory instructions"
70>;
71
72def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
73  "FlatScratchInsts",
74  "true",
75  "Have scratch_* flat memory instructions"
76>;
77
78def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
79  "ScalarFlatScratchInsts",
80  "true",
81  "Have s_scratch_* flat memory instructions"
82>;
83
84def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
85  "AddNoCarryInsts",
86  "true",
87  "Have VALU add/sub instructions without carry out"
88>;
89
90def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
91  "UnalignedBufferAccess",
92  "true",
93  "Support unaligned global loads and stores"
94>;
95
96def FeatureTrapHandler: SubtargetFeature<"trap-handler",
97  "TrapHandler",
98  "true",
99  "Trap handler support"
100>;
101
102def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
103  "UnalignedScratchAccess",
104  "true",
105  "Support unaligned scratch loads and stores"
106>;
107
108def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
109  "HasApertureRegs",
110  "true",
111  "Has Memory Aperture Base and Size Registers"
112>;
113
114def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
115  "HasMadMixInsts",
116  "true",
117  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
118>;
119
120def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
121  "HasFmaMixInsts",
122  "true",
123  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
124>;
125
126def FeatureDoesNotSupportXNACK : SubtargetFeature<"no-xnack-support",
127  "DoesNotSupportXNACK",
128  "true",
129  "Hardware does not support XNACK"
130>;
131
132// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
133// XNACK. The current default kernel driver setting is:
134// - graphics ring: XNACK disabled
135// - compute ring: XNACK enabled
136//
137// If XNACK is enabled, the VMEM latency can be worse.
138// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
139def FeatureXNACK : SubtargetFeature<"xnack",
140  "EnableXNACK",
141  "true",
142  "Enable XNACK support"
143>;
144
145def FeatureCuMode : SubtargetFeature<"cumode",
146  "EnableCuMode",
147  "true",
148  "Enable CU wavefront execution mode"
149>;
150
151def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
152  "SGPRInitBug",
153  "true",
154  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
155>;
156
157def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
158  "LDSMisalignedBug",
159  "true",
160  "Some GFX10 bug with misaligned multi-dword LDS access in WGP mode"
161>;
162
163def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
164  "HasMFMAInlineLiteralBug",
165  "true",
166  "MFMA cannot use inline literal as SrcC"
167>;
168
169def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
170  "HasVcmpxPermlaneHazard",
171  "true",
172  "TODO: describe me"
173>;
174
175def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
176  "HasVMEMtoScalarWriteHazard",
177  "true",
178  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
179>;
180
181def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
182  "HasSMEMtoVectorWriteHazard",
183  "true",
184  "s_load_dword followed by v_cmp page faults"
185>;
186
187def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
188  "HasInstFwdPrefetchBug",
189  "true",
190  "S_INST_PREFETCH instruction causes shader to hang"
191>;
192
193def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
194  "HasVcmpxExecWARHazard",
195  "true",
196  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
197>;
198
199def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
200  "HasLdsBranchVmemWARHazard",
201  "true",
202  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
203>;
204
205def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
206  "HasNSAtoVMEMBug",
207  "true",
208  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
209>;
210
211def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
212  "HasFlatSegmentOffsetBug",
213  "true",
214  "GFX10 bug, inst_offset ignored in flat segment"
215>;
216
217def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
218  "HasOffset3fBug",
219  "true",
220  "Branch offset of 3f hardware bug"
221>;
222
223class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
224  "ldsbankcount"#Value,
225  "LDSBankCount",
226  !cast<string>(Value),
227  "The number of LDS banks per compute unit."
228>;
229
230def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
231def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
232
233def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
234  "GCN3Encoding",
235  "true",
236  "Encoding format for VI"
237>;
238
239def FeatureCIInsts : SubtargetFeature<"ci-insts",
240  "CIInsts",
241  "true",
242  "Additional instructions for CI+"
243>;
244
245def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
246  "GFX8Insts",
247  "true",
248  "Additional instructions for GFX8+"
249>;
250
251def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
252  "GFX9Insts",
253  "true",
254  "Additional instructions for GFX9+"
255>;
256
257def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
258  "GFX10Insts",
259  "true",
260  "Additional instructions for GFX10+"
261>;
262
263def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
264  "GFX7GFX8GFX9Insts",
265  "true",
266  "Instructions shared in GFX7, GFX8, GFX9"
267>;
268
269def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
270  "HasSMemRealTime",
271  "true",
272  "Has s_memrealtime instruction"
273>;
274
275def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
276  "HasInv2PiInlineImm",
277  "true",
278  "Has 1 / (2 * pi) as inline immediate"
279>;
280
281def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
282  "Has16BitInsts",
283  "true",
284  "Has i16/f16 instructions"
285>;
286
287def FeatureVOP3P : SubtargetFeature<"vop3p",
288  "HasVOP3PInsts",
289  "true",
290  "Has VOP3P packed instructions"
291>;
292
293def FeatureMovrel : SubtargetFeature<"movrel",
294  "HasMovrel",
295  "true",
296  "Has v_movrel*_b32 instructions"
297>;
298
299def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
300  "HasVGPRIndexMode",
301  "true",
302  "Has VGPR mode register indexing"
303>;
304
305def FeatureScalarStores : SubtargetFeature<"scalar-stores",
306  "HasScalarStores",
307  "true",
308  "Has store scalar memory instructions"
309>;
310
311def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
312  "HasScalarAtomics",
313  "true",
314  "Has atomic scalar memory instructions"
315>;
316
317def FeatureSDWA : SubtargetFeature<"sdwa",
318  "HasSDWA",
319  "true",
320  "Support SDWA (Sub-DWORD Addressing) extension"
321>;
322
323def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
324  "HasSDWAOmod",
325  "true",
326  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
327>;
328
329def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
330  "HasSDWAScalar",
331  "true",
332  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
333>;
334
335def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
336  "HasSDWASdst",
337  "true",
338  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
339>;
340
341def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
342  "HasSDWAMac",
343  "true",
344  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
345>;
346
347def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
348  "HasSDWAOutModsVOPC",
349  "true",
350  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
351>;
352
353def FeatureDPP : SubtargetFeature<"dpp",
354  "HasDPP",
355  "true",
356  "Support DPP (Data Parallel Primitives) extension"
357>;
358
359// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
360def FeatureDPP8 : SubtargetFeature<"dpp8",
361  "HasDPP8",
362  "true",
363  "Support DPP8 (Data Parallel Primitives) extension"
364>;
365
366def FeatureR128A16 : SubtargetFeature<"r128-a16",
367  "HasR128A16",
368  "true",
369  "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
370>;
371
372def FeatureGFX10A16 : SubtargetFeature<"a16",
373  "HasGFX10A16",
374  "true",
375  "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
376>;
377
378def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
379  "HasNSAEncoding",
380  "true",
381  "Support NSA encoding for image instructions"
382>;
383
384def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
385  "HasIntClamp",
386  "true",
387  "Support clamp for integer destination"
388>;
389
390def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
391  "HasUnpackedD16VMem",
392  "true",
393  "Has unpacked d16 vmem instructions"
394>;
395
396def FeatureDLInsts : SubtargetFeature<"dl-insts",
397  "HasDLInsts",
398  "true",
399  "Has v_fmac_f32 and v_xnor_b32 instructions"
400>;
401
402def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
403  "HasDot1Insts",
404  "true",
405  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
406>;
407
408def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
409  "HasDot2Insts",
410  "true",
411  "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
412>;
413
414def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
415  "HasDot3Insts",
416  "true",
417  "Has v_dot8c_i32_i4 instruction"
418>;
419
420def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
421  "HasDot4Insts",
422  "true",
423  "Has v_dot2c_i32_i16 instruction"
424>;
425
426def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
427  "HasDot5Insts",
428  "true",
429  "Has v_dot2c_f32_f16 instruction"
430>;
431
432def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
433  "HasDot6Insts",
434  "true",
435  "Has v_dot4c_i32_i8 instruction"
436>;
437
438def FeatureMAIInsts : SubtargetFeature<"mai-insts",
439  "HasMAIInsts",
440  "true",
441  "Has mAI instructions"
442>;
443
444def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
445  "HasPkFmacF16Inst",
446  "true",
447  "Has v_pk_fmac_f16 instruction"
448>;
449
450def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
451  "HasAtomicFaddInsts",
452  "true",
453  "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
454  "global_atomic_pk_add_f16 instructions"
455>;
456
457def FeatureDoesNotSupportSRAMECC : SubtargetFeature<"no-sram-ecc-support",
458  "DoesNotSupportSRAMECC",
459  "true",
460  "Hardware does not support SRAM ECC"
461>;
462
463def FeatureSRAMECC : SubtargetFeature<"sram-ecc",
464  "EnableSRAMECC",
465  "true",
466  "Enable SRAM ECC"
467>;
468
469def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
470  "HasNoSdstCMPX",
471  "true",
472  "V_CMPX does not write VCC/SGPR in addition to EXEC"
473>;
474
475def FeatureVscnt : SubtargetFeature<"vscnt",
476  "HasVscnt",
477  "true",
478  "Has separate store vscnt counter"
479>;
480
481def FeatureRegisterBanking : SubtargetFeature<"register-banking",
482  "HasRegisterBanking",
483  "true",
484  "Has register banking"
485>;
486
487def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
488  "HasVOP3Literal",
489  "true",
490  "Can use one literal in VOP3"
491>;
492
493def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
494  "HasNoDataDepHazard",
495  "true",
496  "Does not need SW waitstates"
497>;
498
499//===------------------------------------------------------------===//
500// Subtarget Features (options and debugging)
501//===------------------------------------------------------------===//
502
503def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
504  "FPExceptions",
505  "true",
506  "Enable floating point exceptions"
507>;
508
509class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
510  "max-private-element-size-"#size,
511  "MaxPrivateElementSize",
512  !cast<string>(size),
513  "Maximum private access size may be "#size
514>;
515
516def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
517def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
518def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
519
520def FeatureDumpCode : SubtargetFeature <"DumpCode",
521  "DumpCode",
522  "true",
523  "Dump MachineInstrs in the CodeEmitter"
524>;
525
526def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
527  "DumpCode",
528  "true",
529  "Dump MachineInstrs in the CodeEmitter"
530>;
531
532// XXX - This should probably be removed once enabled by default
533def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
534  "EnableLoadStoreOpt",
535  "true",
536  "Enable SI load/store optimizer pass"
537>;
538
539// Performance debugging feature. Allow using DS instruction immediate
540// offsets even if the base pointer can't be proven to be base. On SI,
541// base pointer values that won't give the same result as a 16-bit add
542// are not safe to fold, but this will override the conservative test
543// for the base pointer.
544def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
545  "unsafe-ds-offset-folding",
546  "EnableUnsafeDSOffsetFolding",
547  "true",
548  "Force using DS instruction immediate offsets on SI"
549>;
550
551def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
552  "EnableSIScheduler",
553  "true",
554  "Enable SI Machine Scheduler"
555>;
556
557def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
558  "EnableDS128",
559  "true",
560  "Use ds_{read|write}_b128"
561>;
562
563// Sparse texture support requires that all result registers are zeroed when
564// PRTStrictNull is set to true. This feature is turned on for all architectures
565// but is enabled as a feature in case there are situations where PRTStrictNull
566// is disabled by the driver.
567def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
568  "EnablePRTStrictNull",
569  "true",
570  "Enable zeroing of result registers for sparse texture fetches"
571>;
572
573// Unless +-flat-for-global is specified, turn on FlatForGlobal for
574// all OS-es on VI and newer hardware to avoid assertion failures due
575// to missing ADDR64 variants of MUBUF instructions.
576// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
577// instructions.
578
579def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
580  "FlatForGlobal",
581  "true",
582  "Force to generate flat instruction for global"
583>;
584
585def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
586  "auto-waitcnt-before-barrier",
587  "AutoWaitcntBeforeBarrier",
588  "true",
589  "Hardware automatically inserts waitcnt before barrier"
590>;
591
592def FeatureCodeObjectV3 : SubtargetFeature <
593  "code-object-v3",
594  "CodeObjectV3",
595  "true",
596  "Generate code object version 3"
597>;
598
599def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
600  "HasTrigReducedRange",
601  "true",
602  "Requires use of fract on arguments to trig instructions"
603>;
604
605// Dummy feature used to disable assembler instructions.
606def FeatureDisable : SubtargetFeature<"",
607  "FeatureDisable","true",
608  "Dummy feature to disable assembler instructions"
609>;
610
611class GCNSubtargetFeatureGeneration <string Value,
612                                     string FeatureName,
613                                     list<SubtargetFeature> Implies> :
614        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
615
616def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
617    "southern-islands",
618  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
619  FeatureWavefrontSize64,
620  FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange,
621  FeatureDoesNotSupportSRAMECC, FeatureDoesNotSupportXNACK]
622>;
623
624def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
625    "sea-islands",
626  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
627  FeatureWavefrontSize64, FeatureFlatAddressSpace,
628  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
629  FeatureGFX7GFX8GFX9Insts, FeatureDoesNotSupportSRAMECC]
630>;
631
632def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
633  "volcanic-islands",
634  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
635   FeatureWavefrontSize64, FeatureFlatAddressSpace,
636   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
637   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
638   FeatureScalarStores, FeatureInv2PiInlineImm,
639   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
640   FeatureIntClamp, FeatureTrigReducedRange, FeatureDoesNotSupportSRAMECC,
641   FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts, FeatureFastDenormalF32
642  ]
643>;
644
645def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
646  "gfx9",
647  [FeatureFP64, FeatureLocalMemorySize65536,
648   FeatureWavefrontSize64, FeatureFlatAddressSpace,
649   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
650   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
651   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
652   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
653   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
654   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
655   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
656   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
657   FeatureFastDenormalF32]
658>;
659
660def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
661  "gfx10",
662  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
663   FeatureFlatAddressSpace,
664   FeatureCIInsts, Feature16BitInsts,
665   FeatureSMemRealTime, FeatureInv2PiInlineImm,
666   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
667   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
668   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
669   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
670   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
671   FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
672   FeatureVOP3Literal, FeatureDPP8,
673   FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureDoesNotSupportSRAMECC,
674   FeatureGFX10A16, FeatureFastDenormalF32
675  ]
676>;
677
678class FeatureSet<list<SubtargetFeature> Features_> {
679  list<SubtargetFeature> Features = Features_;
680}
681
682def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
683   FeatureFastFMAF32,
684   HalfRate64Ops,
685   FeatureLDSBankCount32,
686   FeatureDoesNotSupportXNACK,
687   FeatureCodeObjectV3]>;
688
689def FeatureISAVersion6_0_1 : FeatureSet<
690  [FeatureSouthernIslands,
691   FeatureLDSBankCount32,
692   FeatureDoesNotSupportXNACK,
693   FeatureCodeObjectV3]>;
694
695def FeatureISAVersion7_0_0 : FeatureSet<
696  [FeatureSeaIslands,
697   FeatureLDSBankCount32,
698   FeatureDoesNotSupportXNACK,
699   FeatureCodeObjectV3]>;
700
701def FeatureISAVersion7_0_1 : FeatureSet<
702  [FeatureSeaIslands,
703   HalfRate64Ops,
704   FeatureLDSBankCount32,
705   FeatureFastFMAF32,
706   FeatureDoesNotSupportXNACK,
707   FeatureCodeObjectV3]>;
708
709def FeatureISAVersion7_0_2 : FeatureSet<
710  [FeatureSeaIslands,
711   FeatureLDSBankCount16,
712   FeatureFastFMAF32,
713   FeatureDoesNotSupportXNACK,
714   FeatureCodeObjectV3]>;
715
716def FeatureISAVersion7_0_3 : FeatureSet<
717  [FeatureSeaIslands,
718   FeatureLDSBankCount16,
719   FeatureDoesNotSupportXNACK,
720   FeatureCodeObjectV3]>;
721
722def FeatureISAVersion7_0_4 : FeatureSet<
723  [FeatureSeaIslands,
724   FeatureLDSBankCount32,
725   FeatureDoesNotSupportXNACK,
726   FeatureCodeObjectV3]>;
727
728def FeatureISAVersion8_0_1 : FeatureSet<
729  [FeatureVolcanicIslands,
730   FeatureFastFMAF32,
731   HalfRate64Ops,
732   FeatureLDSBankCount32,
733   FeatureXNACK,
734   FeatureUnpackedD16VMem,
735   FeatureCodeObjectV3]>;
736
737def FeatureISAVersion8_0_2 : FeatureSet<
738  [FeatureVolcanicIslands,
739   FeatureLDSBankCount32,
740   FeatureSGPRInitBug,
741   FeatureUnpackedD16VMem,
742   FeatureDoesNotSupportXNACK,
743   FeatureCodeObjectV3]>;
744
745def FeatureISAVersion8_0_3 : FeatureSet<
746  [FeatureVolcanicIslands,
747   FeatureLDSBankCount32,
748   FeatureUnpackedD16VMem,
749   FeatureDoesNotSupportXNACK,
750   FeatureCodeObjectV3]>;
751
752def FeatureISAVersion8_1_0 : FeatureSet<
753  [FeatureVolcanicIslands,
754   FeatureLDSBankCount16,
755   FeatureXNACK,
756   FeatureCodeObjectV3]>;
757
758def FeatureISAVersion9_0_0 : FeatureSet<
759  [FeatureGFX9,
760   FeatureMadMixInsts,
761   FeatureLDSBankCount32,
762   FeatureCodeObjectV3,
763   FeatureDoesNotSupportXNACK,
764   FeatureDoesNotSupportSRAMECC]>;
765
766def FeatureISAVersion9_0_2 : FeatureSet<
767  [FeatureGFX9,
768   FeatureMadMixInsts,
769   FeatureLDSBankCount32,
770   FeatureXNACK,
771   FeatureDoesNotSupportSRAMECC,
772   FeatureCodeObjectV3]>;
773
774def FeatureISAVersion9_0_4 : FeatureSet<
775  [FeatureGFX9,
776   FeatureLDSBankCount32,
777   FeatureFmaMixInsts,
778   FeatureDoesNotSupportXNACK,
779   FeatureDoesNotSupportSRAMECC,
780   FeatureCodeObjectV3]>;
781
782def FeatureISAVersion9_0_6 : FeatureSet<
783  [FeatureGFX9,
784   HalfRate64Ops,
785   FeatureFmaMixInsts,
786   FeatureLDSBankCount32,
787   FeatureDLInsts,
788   FeatureDot1Insts,
789   FeatureDot2Insts,
790   FeatureDoesNotSupportXNACK,
791   FeatureCodeObjectV3]>;
792
793def FeatureISAVersion9_0_8 : FeatureSet<
794  [FeatureGFX9,
795   HalfRate64Ops,
796   FeatureFmaMixInsts,
797   FeatureLDSBankCount32,
798   FeatureDLInsts,
799   FeatureDot1Insts,
800   FeatureDot2Insts,
801   FeatureDot3Insts,
802   FeatureDot4Insts,
803   FeatureDot5Insts,
804   FeatureDot6Insts,
805   FeatureMAIInsts,
806   FeaturePkFmacF16Inst,
807   FeatureAtomicFaddInsts,
808   FeatureSRAMECC,
809   FeatureMFMAInlineLiteralBug,
810   FeatureCodeObjectV3]>;
811
812def FeatureISAVersion9_0_9 : FeatureSet<
813  [FeatureGFX9,
814   FeatureMadMixInsts,
815   FeatureLDSBankCount32,
816   FeatureXNACK,
817   FeatureCodeObjectV3]>;
818
819// TODO: Organize more features into groups.
820def FeatureGroup {
821  // Bugs present on gfx10.1.
822  list<SubtargetFeature> GFX10_1_Bugs = [
823    FeatureVcmpxPermlaneHazard,
824    FeatureVMEMtoScalarWriteHazard,
825    FeatureSMEMtoVectorWriteHazard,
826    FeatureInstFwdPrefetchBug,
827    FeatureVcmpxExecWARHazard,
828    FeatureLdsBranchVmemWARHazard,
829    FeatureNSAtoVMEMBug,
830    FeatureOffset3fBug,
831    FeatureFlatSegmentOffsetBug
832   ];
833}
834
835def FeatureISAVersion10_1_0 : FeatureSet<
836  !listconcat(FeatureGroup.GFX10_1_Bugs,
837    [FeatureGFX10,
838     FeatureLDSBankCount32,
839     FeatureDLInsts,
840     FeatureNSAEncoding,
841     FeatureWavefrontSize32,
842     FeatureScalarStores,
843     FeatureScalarAtomics,
844     FeatureScalarFlatScratchInsts,
845     FeatureLdsMisalignedBug,
846     FeatureDoesNotSupportXNACK,
847     FeatureCodeObjectV3])>;
848
849def FeatureISAVersion10_1_1 : FeatureSet<
850  !listconcat(FeatureGroup.GFX10_1_Bugs,
851    [FeatureGFX10,
852     FeatureLDSBankCount32,
853     FeatureDLInsts,
854     FeatureDot1Insts,
855     FeatureDot2Insts,
856     FeatureDot5Insts,
857     FeatureDot6Insts,
858     FeatureNSAEncoding,
859     FeatureWavefrontSize32,
860     FeatureScalarStores,
861     FeatureScalarAtomics,
862     FeatureScalarFlatScratchInsts,
863     FeatureDoesNotSupportXNACK,
864     FeatureCodeObjectV3])>;
865
866def FeatureISAVersion10_1_2 : FeatureSet<
867  !listconcat(FeatureGroup.GFX10_1_Bugs,
868    [FeatureGFX10,
869     FeatureLDSBankCount32,
870     FeatureDLInsts,
871     FeatureDot1Insts,
872     FeatureDot2Insts,
873     FeatureDot5Insts,
874     FeatureDot6Insts,
875     FeatureNSAEncoding,
876     FeatureWavefrontSize32,
877     FeatureScalarStores,
878     FeatureScalarAtomics,
879     FeatureScalarFlatScratchInsts,
880     FeatureLdsMisalignedBug,
881     FeatureDoesNotSupportXNACK,
882     FeatureCodeObjectV3])>;
883
884//===----------------------------------------------------------------------===//
885
886def AMDGPUInstrInfo : InstrInfo {
887  let guessInstructionProperties = 1;
888  let noNamedPositionallyEncodedOperands = 1;
889}
890
891def AMDGPUAsmParser : AsmParser {
892  // Some of the R600 registers have the same name, so this crashes.
893  // For example T0_XYZW and T0_XY both have the asm name T0.
894  let ShouldEmitMatchRegisterName = 0;
895}
896
897def AMDGPUAsmWriter : AsmWriter {
898  int PassSubtarget = 1;
899}
900
901def AMDGPUAsmVariants {
902  string Default = "Default";
903  int Default_ID = 0;
904  string VOP3 = "VOP3";
905  int VOP3_ID = 1;
906  string SDWA = "SDWA";
907  int SDWA_ID = 2;
908  string SDWA9 = "SDWA9";
909  int SDWA9_ID = 3;
910  string DPP = "DPP";
911  int DPP_ID = 4;
912  string Disable = "Disable";
913  int Disable_ID = 5;
914}
915
916def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
917  let Variant = AMDGPUAsmVariants.Default_ID;
918  let Name = AMDGPUAsmVariants.Default;
919}
920
921def VOP3AsmParserVariant : AsmParserVariant {
922  let Variant = AMDGPUAsmVariants.VOP3_ID;
923  let Name = AMDGPUAsmVariants.VOP3;
924}
925
926def SDWAAsmParserVariant : AsmParserVariant {
927  let Variant = AMDGPUAsmVariants.SDWA_ID;
928  let Name = AMDGPUAsmVariants.SDWA;
929}
930
931def SDWA9AsmParserVariant : AsmParserVariant {
932  let Variant = AMDGPUAsmVariants.SDWA9_ID;
933  let Name = AMDGPUAsmVariants.SDWA9;
934}
935
936
937def DPPAsmParserVariant : AsmParserVariant {
938  let Variant = AMDGPUAsmVariants.DPP_ID;
939  let Name = AMDGPUAsmVariants.DPP;
940}
941
942def AMDGPU : Target {
943  // Pull in Instruction Info:
944  let InstructionSet = AMDGPUInstrInfo;
945  let AssemblyParsers = [AMDGPUAsmParser];
946  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
947                                VOP3AsmParserVariant,
948                                SDWAAsmParserVariant,
949                                SDWA9AsmParserVariant,
950                                DPPAsmParserVariant];
951  let AssemblyWriters = [AMDGPUAsmWriter];
952  let AllowRegisterRenaming = 1;
953}
954
955// Dummy Instruction itineraries for pseudo instructions
956def ALU_NULL : FuncUnit;
957def NullALU : InstrItinClass;
958
959//===----------------------------------------------------------------------===//
960// Predicate helper class
961//===----------------------------------------------------------------------===//
962
963def isGFX6 :
964  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
965  AssemblerPredicate<(all_of FeatureSouthernIslands)>;
966
967def isGFX6GFX7 :
968  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
969            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
970  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
971
972def isGFX6GFX7GFX10 :
973  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
974            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
975            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
976  AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
977
978def isGFX7Only :
979  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
980  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
981
982def isGFX7GFX10 :
983  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
984            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
985  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
986
987def isGFX7GFX8GFX9 :
988  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
989            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
990            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
991  AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
992
993def isGFX6GFX7GFX8GFX9 :
994  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
995            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
996            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
997            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
998  AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
999
1000def isGFX7Plus :
1001  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1002  AssemblerPredicate<(all_of FeatureCIInsts)>;
1003
1004def isGFX8Plus :
1005  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1006  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1007
1008def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1009                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1010  AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1011
1012def isGFX9Plus :
1013  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1014  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1015
1016def isGFX9Only : Predicate <
1017  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1018  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1019
1020def isGFX8GFX9 :
1021  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1022            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1023  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1024
1025def isGFX10Plus :
1026  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1027  AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1028
1029def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1030  AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1031
1032def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1033  AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1034def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1035  AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1036def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1037  AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1038def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1039  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1040
1041def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1042  AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1043def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1044  AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1045
1046def D16PreservesUnusedBits :
1047  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1048  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1049
1050def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1051def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1052
1053def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1054  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1055
1056def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1057  AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1058
1059def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1060
1061def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1062  AssemblerPredicate<(all_of Feature16BitInsts)>;
1063def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1064  AssemblerPredicate<(all_of FeatureVOP3P)>;
1065
1066def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1067  AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1068
1069def HasSDWA9 :
1070  Predicate<"Subtarget->hasSDWA()">,
1071  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1072
1073def HasSDWA10 :
1074  Predicate<"Subtarget->hasSDWA()">,
1075  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1076
1077def HasDPP : Predicate<"Subtarget->hasDPP()">,
1078  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1079
1080def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1081  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1082
1083def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1084  AssemblerPredicate<(all_of FeatureR128A16)>;
1085
1086def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1087  AssemblerPredicate<(all_of FeatureGFX10A16)>;
1088
1089def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1090  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1091
1092def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1093  AssemblerPredicate<(all_of FeatureIntClamp)>;
1094
1095def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1096  AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1097
1098def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1099  AssemblerPredicate<(all_of FeatureScalarStores)>;
1100
1101def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1102  AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1103
1104def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1105  AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1106
1107def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1108  AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1109
1110def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1111def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1112def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1113                      AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1114def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1115                AssemblerPredicate<(all_of FeatureMovrel)>;
1116
1117def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1118  AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1119
1120def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1121  AssemblerPredicate<(all_of FeatureDLInsts)>;
1122
1123def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1124  AssemblerPredicate<(all_of FeatureDot1Insts)>;
1125
1126def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1127  AssemblerPredicate<(all_of FeatureDot2Insts)>;
1128
1129def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1130  AssemblerPredicate<(all_of FeatureDot3Insts)>;
1131
1132def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1133  AssemblerPredicate<(all_of FeatureDot4Insts)>;
1134
1135def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1136  AssemblerPredicate<(all_of FeatureDot5Insts)>;
1137
1138def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1139  AssemblerPredicate<(all_of FeatureDot6Insts)>;
1140
1141def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1142  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1143
1144def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1145  AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1146
1147def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1148  AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>;
1149
1150def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">,
1151  AssemblerPredicate<(all_of FeatureOffset3fBug)>;
1152
1153def EnableLateCFGStructurize : Predicate<
1154  "EnableLateStructurizeCFG">;
1155
1156// Include AMDGPU TD files
1157include "SISchedule.td"
1158include "GCNProcessors.td"
1159include "AMDGPUInstrInfo.td"
1160include "SIRegisterInfo.td"
1161include "AMDGPURegisterBanks.td"
1162include "AMDGPUInstructions.td"
1163include "SIInstrInfo.td"
1164include "AMDGPUCallingConv.td"
1165include "AMDGPUSearchableTables.td"
1166