1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21
22class BoolToList<bit Value> {
23  list<int> ret = !if(Value, [1]<int>, []<int>);
24}
25
26//===------------------------------------------------------------===//
27// Subtarget Features (device properties)
28//===------------------------------------------------------------===//
29
30def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
31  "FastFMAF32",
32  "true",
33  "Assuming f32 fma is at least as fast as mul + add"
34>;
35
36def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
37  "FastDenormalF32",
38  "true",
39  "Enabling denormals does not cause f32 instructions to run at f64 rates"
40>;
41
42def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
43  "MIMG_R128",
44  "true",
45  "Support 128-bit texture resources"
46>;
47
48def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
49  "HalfRate64Ops",
50  "true",
51  "Most fp64 instructions are half rate instead of quarter"
52>;
53
54def FullRate64Ops : SubtargetFeature<"full-rate-64-ops",
55  "FullRate64Ops",
56  "true",
57  "Most fp64 instructions are full rate"
58>;
59
60def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
61  "FlatAddressSpace",
62  "true",
63  "Support flat address space"
64>;
65
66def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
67  "FlatInstOffsets",
68  "true",
69  "Flat instructions have immediate offset addressing mode"
70>;
71
72def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
73  "FlatGlobalInsts",
74  "true",
75  "Have global_* flat memory instructions"
76>;
77
78def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
79  "FlatScratchInsts",
80  "true",
81  "Have scratch_* flat memory instructions"
82>;
83
84def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
85  "ScalarFlatScratchInsts",
86  "true",
87  "Have s_scratch_* flat memory instructions"
88>;
89
90def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
91  "AddNoCarryInsts",
92  "true",
93  "Have VALU add/sub instructions without carry out"
94>;
95
96def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
97  "UnalignedBufferAccess",
98  "true",
99  "Hardware supports unaligned global loads and stores"
100>;
101
102def FeatureTrapHandler: SubtargetFeature<"trap-handler",
103  "TrapHandler",
104  "true",
105  "Trap handler support"
106>;
107
108def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
109  "UnalignedScratchAccess",
110  "true",
111  "Support unaligned scratch loads and stores"
112>;
113
114def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access",
115  "UnalignedDSAccess",
116  "true",
117  "Hardware supports unaligned local and region loads and stores"
118>;
119
120def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
121  "HasApertureRegs",
122  "true",
123  "Has Memory Aperture Base and Size Registers"
124>;
125
126def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
127  "HasMadMixInsts",
128  "true",
129  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
130>;
131
132def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
133  "HasFmaMixInsts",
134  "true",
135  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
136>;
137
138def FeatureSupportsXNACK : SubtargetFeature<"xnack-support",
139  "SupportsXNACK",
140  "true",
141  "Hardware supports XNACK"
142>;
143
144// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
145// XNACK. The current default kernel driver setting is:
146// - graphics ring: XNACK disabled
147// - compute ring: XNACK enabled
148//
149// If XNACK is enabled, the VMEM latency can be worse.
150// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
151def FeatureXNACK : SubtargetFeature<"xnack",
152  "EnableXNACK",
153  "true",
154  "Enable XNACK support"
155>;
156
157def FeatureTgSplit : SubtargetFeature<"tgsplit",
158  "EnableTgSplit",
159  "true",
160  "Enable threadgroup split execution"
161>;
162
163def FeatureCuMode : SubtargetFeature<"cumode",
164  "EnableCuMode",
165  "true",
166  "Enable CU wavefront execution mode"
167>;
168
169def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
170  "SGPRInitBug",
171  "true",
172  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
173>;
174
175def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
176  "LDSMisalignedBug",
177  "true",
178  "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode"
179>;
180
181def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
182  "HasMFMAInlineLiteralBug",
183  "true",
184  "MFMA cannot use inline literal as SrcC"
185>;
186
187def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
188  "HasVcmpxPermlaneHazard",
189  "true",
190  "TODO: describe me"
191>;
192
193def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
194  "HasVMEMtoScalarWriteHazard",
195  "true",
196  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
197>;
198
199def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
200  "HasSMEMtoVectorWriteHazard",
201  "true",
202  "s_load_dword followed by v_cmp page faults"
203>;
204
205def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
206  "HasInstFwdPrefetchBug",
207  "true",
208  "S_INST_PREFETCH instruction causes shader to hang"
209>;
210
211def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
212  "HasVcmpxExecWARHazard",
213  "true",
214  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
215>;
216
217def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
218  "HasLdsBranchVmemWARHazard",
219  "true",
220  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
221>;
222
223def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
224  "HasNSAtoVMEMBug",
225  "true",
226  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
227>;
228
229def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
230  "HasFlatSegmentOffsetBug",
231  "true",
232  "GFX10 bug where inst_offset is ignored when flat instructions access global memory"
233>;
234
235def FeatureNegativeScratchOffsetBug : SubtargetFeature<"negative-scratch-offset-bug",
236  "NegativeScratchOffsetBug",
237  "true",
238  "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9"
239>;
240
241def FeatureNegativeUnalignedScratchOffsetBug : SubtargetFeature<"negative-unaligned-scratch-offset-bug",
242  "NegativeUnalignedScratchOffsetBug",
243  "true",
244  "Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10"
245>;
246
247def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
248  "HasOffset3fBug",
249  "true",
250  "Branch offset of 3f hardware bug"
251>;
252
253def FeatureImageStoreD16Bug : SubtargetFeature<"image-store-d16-bug",
254  "HasImageStoreD16Bug",
255  "true",
256  "Image Store D16 hardware bug"
257>;
258
259def FeatureImageGather4D16Bug : SubtargetFeature<"image-gather4-d16-bug",
260  "HasImageGather4D16Bug",
261  "true",
262  "Image Gather4 D16 hardware bug"
263>;
264
265class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
266  "ldsbankcount"#Value,
267  "LDSBankCount",
268  !cast<string>(Value),
269  "The number of LDS banks per compute unit."
270>;
271
272def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
273def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
274
275def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
276  "GCN3Encoding",
277  "true",
278  "Encoding format for VI"
279>;
280
281def FeatureCIInsts : SubtargetFeature<"ci-insts",
282  "CIInsts",
283  "true",
284  "Additional instructions for CI+"
285>;
286
287def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
288  "GFX8Insts",
289  "true",
290  "Additional instructions for GFX8+"
291>;
292
293def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
294  "GFX9Insts",
295  "true",
296  "Additional instructions for GFX9+"
297>;
298
299def FeatureGFX90AInsts : SubtargetFeature<"gfx90a-insts",
300  "GFX90AInsts",
301  "true",
302  "Additional instructions for GFX90A+"
303>;
304
305def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
306  "GFX10Insts",
307  "true",
308  "Additional instructions for GFX10+"
309>;
310
311def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts",
312  "GFX10_3Insts",
313  "true",
314  "Additional instructions for GFX10.3"
315>;
316
317def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
318  "GFX7GFX8GFX9Insts",
319  "true",
320  "Instructions shared in GFX7, GFX8, GFX9"
321>;
322
323def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
324  "HasSMemRealTime",
325  "true",
326  "Has s_memrealtime instruction"
327>;
328
329def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
330  "HasInv2PiInlineImm",
331  "true",
332  "Has 1 / (2 * pi) as inline immediate"
333>;
334
335def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
336  "Has16BitInsts",
337  "true",
338  "Has i16/f16 instructions"
339>;
340
341def FeatureVOP3P : SubtargetFeature<"vop3p",
342  "HasVOP3PInsts",
343  "true",
344  "Has VOP3P packed instructions"
345>;
346
347def FeatureMovrel : SubtargetFeature<"movrel",
348  "HasMovrel",
349  "true",
350  "Has v_movrel*_b32 instructions"
351>;
352
353def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
354  "HasVGPRIndexMode",
355  "true",
356  "Has VGPR mode register indexing"
357>;
358
359def FeatureScalarStores : SubtargetFeature<"scalar-stores",
360  "HasScalarStores",
361  "true",
362  "Has store scalar memory instructions"
363>;
364
365def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
366  "HasScalarAtomics",
367  "true",
368  "Has atomic scalar memory instructions"
369>;
370
371def FeatureSDWA : SubtargetFeature<"sdwa",
372  "HasSDWA",
373  "true",
374  "Support SDWA (Sub-DWORD Addressing) extension"
375>;
376
377def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
378  "HasSDWAOmod",
379  "true",
380  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
381>;
382
383def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
384  "HasSDWAScalar",
385  "true",
386  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
387>;
388
389def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
390  "HasSDWASdst",
391  "true",
392  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
393>;
394
395def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
396  "HasSDWAMac",
397  "true",
398  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
399>;
400
401def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
402  "HasSDWAOutModsVOPC",
403  "true",
404  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
405>;
406
407def FeatureDPP : SubtargetFeature<"dpp",
408  "HasDPP",
409  "true",
410  "Support DPP (Data Parallel Primitives) extension"
411>;
412
413// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
414def FeatureDPP8 : SubtargetFeature<"dpp8",
415  "HasDPP8",
416  "true",
417  "Support DPP8 (Data Parallel Primitives) extension"
418>;
419
420def Feature64BitDPP : SubtargetFeature<"dpp-64bit",
421  "Has64BitDPP",
422  "true",
423  "Support DPP (Data Parallel Primitives) extension"
424>;
425
426def FeaturePackedFP32Ops : SubtargetFeature<"packed-fp32-ops",
427  "HasPackedFP32Ops",
428  "true",
429  "Support packed fp32 instructions"
430>;
431
432def FeatureR128A16 : SubtargetFeature<"r128-a16",
433  "HasR128A16",
434  "true",
435  "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
436>;
437
438def FeatureGFX10A16 : SubtargetFeature<"a16",
439  "HasGFX10A16",
440  "true",
441  "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
442>;
443
444def FeatureG16 : SubtargetFeature<"g16",
445  "HasG16",
446  "true",
447  "Support G16 for 16-bit gradient image operands"
448>;
449
450def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
451  "HasNSAEncoding",
452  "true",
453  "Support NSA encoding for image instructions"
454>;
455
456def FeatureExtendedImageInsts : SubtargetFeature<"extended-image-insts",
457  "HasExtendedImageInsts",
458  "true",
459  "Support mips != 0, lod != 0, gather4, and get_lod"
460>;
461
462def FeatureGFX10_BEncoding : SubtargetFeature<"gfx10_b-encoding",
463  "GFX10_BEncoding",
464  "true",
465  "Encoding format GFX10_B"
466>;
467
468def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
469  "HasIntClamp",
470  "true",
471  "Support clamp for integer destination"
472>;
473
474def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
475  "HasUnpackedD16VMem",
476  "true",
477  "Has unpacked d16 vmem instructions"
478>;
479
480def FeatureDLInsts : SubtargetFeature<"dl-insts",
481  "HasDLInsts",
482  "true",
483  "Has v_fmac_f32 and v_xnor_b32 instructions"
484>;
485
486def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
487  "HasDot1Insts",
488  "true",
489  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
490>;
491
492def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
493  "HasDot2Insts",
494  "true",
495  "Has v_dot2_i32_i16, v_dot2_u32_u16 instructions"
496>;
497
498def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
499  "HasDot3Insts",
500  "true",
501  "Has v_dot8c_i32_i4 instruction"
502>;
503
504def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
505  "HasDot4Insts",
506  "true",
507  "Has v_dot2c_i32_i16 instruction"
508>;
509
510def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
511  "HasDot5Insts",
512  "true",
513  "Has v_dot2c_f32_f16 instruction"
514>;
515
516def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
517  "HasDot6Insts",
518  "true",
519  "Has v_dot4c_i32_i8 instruction"
520>;
521
522def FeatureDot7Insts : SubtargetFeature<"dot7-insts",
523  "HasDot7Insts",
524  "true",
525  "Has v_dot2_f32_f16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
526>;
527
528def FeatureMAIInsts : SubtargetFeature<"mai-insts",
529  "HasMAIInsts",
530  "true",
531  "Has mAI instructions"
532>;
533
534def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
535  "HasPkFmacF16Inst",
536  "true",
537  "Has v_pk_fmac_f16 instruction"
538>;
539
540def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
541  "HasAtomicFaddInsts",
542  "true",
543  "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
544  "global_atomic_pk_add_f16 instructions",
545  [FeatureFlatGlobalInsts]
546>;
547
548def FeatureSupportsSRAMECC : SubtargetFeature<"sramecc-support",
549  "SupportsSRAMECC",
550  "true",
551  "Hardware supports SRAMECC"
552>;
553
554def FeatureSRAMECC : SubtargetFeature<"sramecc",
555  "EnableSRAMECC",
556  "true",
557  "Enable SRAMECC"
558>;
559
560def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
561  "HasNoSdstCMPX",
562  "true",
563  "V_CMPX does not write VCC/SGPR in addition to EXEC"
564>;
565
566def FeatureVscnt : SubtargetFeature<"vscnt",
567  "HasVscnt",
568  "true",
569  "Has separate store vscnt counter"
570>;
571
572def FeatureGetWaveIdInst : SubtargetFeature<"get-wave-id-inst",
573  "HasGetWaveIdInst",
574  "true",
575  "Has s_get_waveid_in_workgroup instruction"
576>;
577
578def FeatureSMemTimeInst : SubtargetFeature<"s-memtime-inst",
579  "HasSMemTimeInst",
580  "true",
581  "Has s_memtime instruction"
582>;
583
584def FeatureShaderCyclesRegister : SubtargetFeature<"shader-cycles-register",
585  "HasShaderCyclesRegister",
586  "true",
587  "Has SHADER_CYCLES hardware register"
588>;
589
590def FeatureMadMacF32Insts : SubtargetFeature<"mad-mac-f32-insts",
591  "HasMadMacF32Insts",
592  "true",
593  "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions"
594>;
595
596def FeatureDsSrc2Insts : SubtargetFeature<"ds-src2-insts",
597  "HasDsSrc2Insts",
598  "true",
599  "Has ds_*_src2 instructions"
600>;
601
602def FeatureRegisterBanking : SubtargetFeature<"register-banking",
603  "HasRegisterBanking",
604  "true",
605  "Has register banking"
606>;
607
608def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
609  "HasVOP3Literal",
610  "true",
611  "Can use one literal in VOP3"
612>;
613
614def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
615  "HasNoDataDepHazard",
616  "true",
617  "Does not need SW waitstates"
618>;
619
620//===------------------------------------------------------------===//
621// Subtarget Features (options and debugging)
622//===------------------------------------------------------------===//
623
624class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
625  "max-private-element-size-"#size,
626  "MaxPrivateElementSize",
627  !cast<string>(size),
628  "Maximum private access size may be "#size
629>;
630
631def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
632def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
633def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
634
635def FeatureDumpCode : SubtargetFeature <"DumpCode",
636  "DumpCode",
637  "true",
638  "Dump MachineInstrs in the CodeEmitter"
639>;
640
641def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
642  "DumpCode",
643  "true",
644  "Dump MachineInstrs in the CodeEmitter"
645>;
646
647// XXX - This should probably be removed once enabled by default
648def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
649  "EnableLoadStoreOpt",
650  "true",
651  "Enable SI load/store optimizer pass"
652>;
653
654// Performance debugging feature. Allow using DS instruction immediate
655// offsets even if the base pointer can't be proven to be base. On SI,
656// base pointer values that won't give the same result as a 16-bit add
657// are not safe to fold, but this will override the conservative test
658// for the base pointer.
659def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
660  "unsafe-ds-offset-folding",
661  "EnableUnsafeDSOffsetFolding",
662  "true",
663  "Force using DS instruction immediate offsets on SI"
664>;
665
666def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
667  "EnableSIScheduler",
668  "true",
669  "Enable SI Machine Scheduler"
670>;
671
672def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
673  "EnableDS128",
674  "true",
675  "Use ds_{read|write}_b128"
676>;
677
678// Sparse texture support requires that all result registers are zeroed when
679// PRTStrictNull is set to true. This feature is turned on for all architectures
680// but is enabled as a feature in case there are situations where PRTStrictNull
681// is disabled by the driver.
682def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
683  "EnablePRTStrictNull",
684  "true",
685  "Enable zeroing of result registers for sparse texture fetches"
686>;
687
688// Unless +-flat-for-global is specified, turn on FlatForGlobal for
689// all OS-es on VI and newer hardware to avoid assertion failures due
690// to missing ADDR64 variants of MUBUF instructions.
691// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
692// instructions.
693
694def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
695  "FlatForGlobal",
696  "true",
697  "Force to generate flat instruction for global"
698>;
699
700def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
701  "auto-waitcnt-before-barrier",
702  "AutoWaitcntBeforeBarrier",
703  "true",
704  "Hardware automatically inserts waitcnt before barrier"
705>;
706
707def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
708  "HasTrigReducedRange",
709  "true",
710  "Requires use of fract on arguments to trig instructions"
711>;
712
713// Alignment enforcement is controlled by a configuration register:
714// SH_MEM_CONFIG.alignment_mode
715def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode",
716  "UnalignedAccessMode",
717  "true",
718  "Enable unaligned global, local and region loads and stores if the hardware"
719  " supports it"
720>;
721
722def FeaturePackedTID : SubtargetFeature<"packed-tid",
723  "HasPackedTID",
724  "true",
725  "Workitem IDs are packed into v0 at kernel launch"
726>;
727
728// Dummy feature used to disable assembler instructions.
729def FeatureDisable : SubtargetFeature<"",
730  "FeatureDisable","true",
731  "Dummy feature to disable assembler instructions"
732>;
733
734class GCNSubtargetFeatureGeneration <string Value,
735                                     string FeatureName,
736                                     list<SubtargetFeature> Implies> :
737        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
738
739def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
740    "southern-islands",
741  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
742  FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,
743  FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
744  FeatureTrigReducedRange, FeatureExtendedImageInsts
745  ]
746>;
747
748def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
749    "sea-islands",
750  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
751  FeatureWavefrontSize64, FeatureFlatAddressSpace,
752  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
753  FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
754  FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureUnalignedBufferAccess
755  ]
756>;
757
758def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
759  "volcanic-islands",
760  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
761   FeatureWavefrontSize64, FeatureFlatAddressSpace,
762   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
763   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
764   FeatureScalarStores, FeatureInv2PiInlineImm,
765   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
766   FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
767   FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
768   FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureFastDenormalF32,
769   FeatureUnalignedBufferAccess
770  ]
771>;
772
773def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
774  "gfx9",
775  [FeatureFP64, FeatureLocalMemorySize65536,
776   FeatureWavefrontSize64, FeatureFlatAddressSpace,
777   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
778   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
779   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
780   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
781   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
782   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
783   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
784   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
785   FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureSupportsXNACK,
786   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess,
787   FeatureNegativeScratchOffsetBug
788  ]
789>;
790
791def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
792  "gfx10",
793  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
794   FeatureFlatAddressSpace,
795   FeatureCIInsts, Feature16BitInsts,
796   FeatureSMemRealTime, FeatureInv2PiInlineImm,
797   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
798   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
799   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
800   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
801   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
802   FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
803   FeatureVOP3Literal, FeatureDPP8, FeatureExtendedImageInsts,
804   FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
805   FeatureGFX10A16, FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureG16,
806   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess
807  ]
808>;
809
810class FeatureSet<list<SubtargetFeature> Features_> {
811  list<SubtargetFeature> Features = Features_;
812}
813
814def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
815   FeatureFastFMAF32,
816   HalfRate64Ops,
817   FeatureLDSBankCount32]>;
818
819def FeatureISAVersion6_0_1 : FeatureSet<
820  [FeatureSouthernIslands,
821   FeatureLDSBankCount32]>;
822
823def FeatureISAVersion6_0_2 : FeatureSet<
824  [FeatureSouthernIslands,
825   FeatureLDSBankCount32]>;
826
827def FeatureISAVersion7_0_0 : FeatureSet<
828  [FeatureSeaIslands,
829   FeatureLDSBankCount32]>;
830
831def FeatureISAVersion7_0_1 : FeatureSet<
832  [FeatureSeaIslands,
833   HalfRate64Ops,
834   FeatureLDSBankCount32,
835   FeatureFastFMAF32]>;
836
837def FeatureISAVersion7_0_2 : FeatureSet<
838  [FeatureSeaIslands,
839   FeatureLDSBankCount16,
840   FeatureFastFMAF32]>;
841
842def FeatureISAVersion7_0_3 : FeatureSet<
843  [FeatureSeaIslands,
844   FeatureLDSBankCount16]>;
845
846def FeatureISAVersion7_0_4 : FeatureSet<
847  [FeatureSeaIslands,
848   FeatureLDSBankCount32]>;
849
850def FeatureISAVersion7_0_5 : FeatureSet<
851  [FeatureSeaIslands,
852   FeatureLDSBankCount16]>;
853
854def FeatureISAVersion8_0_1 : FeatureSet<
855  [FeatureVolcanicIslands,
856   FeatureFastFMAF32,
857   HalfRate64Ops,
858   FeatureLDSBankCount32,
859   FeatureSupportsXNACK,
860   FeatureUnpackedD16VMem]>;
861
862def FeatureISAVersion8_0_2 : FeatureSet<
863  [FeatureVolcanicIslands,
864   FeatureLDSBankCount32,
865   FeatureSGPRInitBug,
866   FeatureUnpackedD16VMem]>;
867
868def FeatureISAVersion8_0_3 : FeatureSet<
869  [FeatureVolcanicIslands,
870   FeatureLDSBankCount32,
871   FeatureUnpackedD16VMem]>;
872
873def FeatureISAVersion8_0_5 : FeatureSet<
874  [FeatureVolcanicIslands,
875   FeatureLDSBankCount32,
876   FeatureSGPRInitBug,
877   FeatureUnpackedD16VMem]>;
878
879def FeatureISAVersion8_1_0 : FeatureSet<
880  [FeatureVolcanicIslands,
881   FeatureLDSBankCount16,
882   FeatureSupportsXNACK,
883   FeatureImageStoreD16Bug,
884   FeatureImageGather4D16Bug]>;
885
886def FeatureISAVersion9_0_0 : FeatureSet<
887  [FeatureGFX9,
888   FeatureMadMixInsts,
889   FeatureLDSBankCount32,
890   FeatureDsSrc2Insts,
891   FeatureExtendedImageInsts,
892   FeatureMadMacF32Insts,
893   FeatureImageGather4D16Bug]>;
894
895def FeatureISAVersion9_0_2 : FeatureSet<
896  [FeatureGFX9,
897   FeatureMadMixInsts,
898   FeatureLDSBankCount32,
899   FeatureDsSrc2Insts,
900   FeatureExtendedImageInsts,
901   FeatureMadMacF32Insts,
902   FeatureImageGather4D16Bug]>;
903
904def FeatureISAVersion9_0_4 : FeatureSet<
905  [FeatureGFX9,
906   FeatureLDSBankCount32,
907   FeatureDsSrc2Insts,
908   FeatureExtendedImageInsts,
909   FeatureMadMacF32Insts,
910   FeatureFmaMixInsts,
911   FeatureImageGather4D16Bug]>;
912
913def FeatureISAVersion9_0_6 : FeatureSet<
914  [FeatureGFX9,
915   HalfRate64Ops,
916   FeatureFmaMixInsts,
917   FeatureLDSBankCount32,
918   FeatureDsSrc2Insts,
919   FeatureExtendedImageInsts,
920   FeatureMadMacF32Insts,
921   FeatureDLInsts,
922   FeatureDot1Insts,
923   FeatureDot2Insts,
924   FeatureDot7Insts,
925   FeatureSupportsSRAMECC,
926   FeatureImageGather4D16Bug]>;
927
928def FeatureISAVersion9_0_8 : FeatureSet<
929  [FeatureGFX9,
930   HalfRate64Ops,
931   FeatureFmaMixInsts,
932   FeatureLDSBankCount32,
933   FeatureDsSrc2Insts,
934   FeatureExtendedImageInsts,
935   FeatureMadMacF32Insts,
936   FeatureDLInsts,
937   FeatureDot1Insts,
938   FeatureDot2Insts,
939   FeatureDot3Insts,
940   FeatureDot4Insts,
941   FeatureDot5Insts,
942   FeatureDot6Insts,
943   FeatureDot7Insts,
944   FeatureMAIInsts,
945   FeaturePkFmacF16Inst,
946   FeatureAtomicFaddInsts,
947   FeatureSupportsSRAMECC,
948   FeatureMFMAInlineLiteralBug,
949   FeatureImageGather4D16Bug]>;
950
951def FeatureISAVersion9_0_9 : FeatureSet<
952  [FeatureGFX9,
953   FeatureMadMixInsts,
954   FeatureLDSBankCount32,
955   FeatureDsSrc2Insts,
956   FeatureExtendedImageInsts,
957   FeatureMadMacF32Insts,
958   FeatureImageGather4D16Bug]>;
959
960def FeatureISAVersion9_0_A : FeatureSet<
961  [FeatureGFX9,
962   FeatureGFX90AInsts,
963   FeatureFmaMixInsts,
964   FeatureLDSBankCount32,
965   FeatureDLInsts,
966   FeatureDot1Insts,
967   FeatureDot2Insts,
968   FeatureDot3Insts,
969   FeatureDot4Insts,
970   FeatureDot5Insts,
971   FeatureDot6Insts,
972   FeatureDot7Insts,
973   Feature64BitDPP,
974   FeaturePackedFP32Ops,
975   FeatureMAIInsts,
976   FeaturePkFmacF16Inst,
977   FeatureAtomicFaddInsts,
978   FeatureMadMacF32Insts,
979   FeatureSupportsSRAMECC,
980   FeaturePackedTID,
981   FullRate64Ops]>;
982
983def FeatureISAVersion9_0_C : FeatureSet<
984  [FeatureGFX9,
985   FeatureMadMixInsts,
986   FeatureLDSBankCount32,
987   FeatureDsSrc2Insts,
988   FeatureExtendedImageInsts,
989   FeatureMadMacF32Insts,
990   FeatureImageGather4D16Bug]>;
991
992// TODO: Organize more features into groups.
993def FeatureGroup {
994  // Bugs present on gfx10.1.
995  list<SubtargetFeature> GFX10_1_Bugs = [
996    FeatureVcmpxPermlaneHazard,
997    FeatureVMEMtoScalarWriteHazard,
998    FeatureSMEMtoVectorWriteHazard,
999    FeatureInstFwdPrefetchBug,
1000    FeatureVcmpxExecWARHazard,
1001    FeatureLdsBranchVmemWARHazard,
1002    FeatureNSAtoVMEMBug,
1003    FeatureOffset3fBug,
1004    FeatureFlatSegmentOffsetBug,
1005    FeatureNegativeUnalignedScratchOffsetBug
1006   ];
1007}
1008
1009def FeatureISAVersion10_1_0 : FeatureSet<
1010  !listconcat(FeatureGroup.GFX10_1_Bugs,
1011    [FeatureGFX10,
1012     FeatureLDSBankCount32,
1013     FeatureDLInsts,
1014     FeatureNSAEncoding,
1015     FeatureWavefrontSize32,
1016     FeatureScalarStores,
1017     FeatureScalarAtomics,
1018     FeatureScalarFlatScratchInsts,
1019     FeatureGetWaveIdInst,
1020     FeatureMadMacF32Insts,
1021     FeatureDsSrc2Insts,
1022     FeatureLdsMisalignedBug,
1023     FeatureSupportsXNACK])>;
1024
1025def FeatureISAVersion10_1_1 : FeatureSet<
1026  !listconcat(FeatureGroup.GFX10_1_Bugs,
1027    [FeatureGFX10,
1028     FeatureLDSBankCount32,
1029     FeatureDLInsts,
1030     FeatureDot1Insts,
1031     FeatureDot2Insts,
1032     FeatureDot5Insts,
1033     FeatureDot6Insts,
1034     FeatureDot7Insts,
1035     FeatureNSAEncoding,
1036     FeatureWavefrontSize32,
1037     FeatureScalarStores,
1038     FeatureScalarAtomics,
1039     FeatureScalarFlatScratchInsts,
1040     FeatureGetWaveIdInst,
1041     FeatureMadMacF32Insts,
1042     FeatureDsSrc2Insts,
1043     FeatureLdsMisalignedBug,
1044     FeatureSupportsXNACK])>;
1045
1046def FeatureISAVersion10_1_2 : FeatureSet<
1047  !listconcat(FeatureGroup.GFX10_1_Bugs,
1048    [FeatureGFX10,
1049     FeatureLDSBankCount32,
1050     FeatureDLInsts,
1051     FeatureDot1Insts,
1052     FeatureDot2Insts,
1053     FeatureDot5Insts,
1054     FeatureDot6Insts,
1055     FeatureDot7Insts,
1056     FeatureNSAEncoding,
1057     FeatureWavefrontSize32,
1058     FeatureScalarStores,
1059     FeatureScalarAtomics,
1060     FeatureScalarFlatScratchInsts,
1061     FeatureGetWaveIdInst,
1062     FeatureMadMacF32Insts,
1063     FeatureDsSrc2Insts,
1064     FeatureLdsMisalignedBug,
1065     FeatureSupportsXNACK])>;
1066
1067def FeatureISAVersion10_3_0 : FeatureSet<
1068  [FeatureGFX10,
1069   FeatureGFX10_BEncoding,
1070   FeatureGFX10_3Insts,
1071   FeatureLDSBankCount32,
1072   FeatureDLInsts,
1073   FeatureDot1Insts,
1074   FeatureDot2Insts,
1075   FeatureDot5Insts,
1076   FeatureDot6Insts,
1077   FeatureDot7Insts,
1078   FeatureNSAEncoding,
1079   FeatureWavefrontSize32,
1080   FeatureShaderCyclesRegister]>;
1081
1082//===----------------------------------------------------------------------===//
1083
1084def AMDGPUInstrInfo : InstrInfo {
1085  let guessInstructionProperties = 1;
1086  let noNamedPositionallyEncodedOperands = 1;
1087}
1088
1089def AMDGPUAsmParser : AsmParser {
1090  // Some of the R600 registers have the same name, so this crashes.
1091  // For example T0_XYZW and T0_XY both have the asm name T0.
1092  let ShouldEmitMatchRegisterName = 0;
1093}
1094
1095def AMDGPUAsmWriter : AsmWriter {
1096  int PassSubtarget = 1;
1097}
1098
1099def AMDGPUAsmVariants {
1100  string Default = "Default";
1101  int Default_ID = 0;
1102  string VOP3 = "VOP3";
1103  int VOP3_ID = 1;
1104  string SDWA = "SDWA";
1105  int SDWA_ID = 2;
1106  string SDWA9 = "SDWA9";
1107  int SDWA9_ID = 3;
1108  string DPP = "DPP";
1109  int DPP_ID = 4;
1110  string Disable = "Disable";
1111  int Disable_ID = 5;
1112}
1113
1114def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
1115  let Variant = AMDGPUAsmVariants.Default_ID;
1116  let Name = AMDGPUAsmVariants.Default;
1117}
1118
1119def VOP3AsmParserVariant : AsmParserVariant {
1120  let Variant = AMDGPUAsmVariants.VOP3_ID;
1121  let Name = AMDGPUAsmVariants.VOP3;
1122}
1123
1124def SDWAAsmParserVariant : AsmParserVariant {
1125  let Variant = AMDGPUAsmVariants.SDWA_ID;
1126  let Name = AMDGPUAsmVariants.SDWA;
1127}
1128
1129def SDWA9AsmParserVariant : AsmParserVariant {
1130  let Variant = AMDGPUAsmVariants.SDWA9_ID;
1131  let Name = AMDGPUAsmVariants.SDWA9;
1132}
1133
1134
1135def DPPAsmParserVariant : AsmParserVariant {
1136  let Variant = AMDGPUAsmVariants.DPP_ID;
1137  let Name = AMDGPUAsmVariants.DPP;
1138}
1139
1140def AMDGPU : Target {
1141  // Pull in Instruction Info:
1142  let InstructionSet = AMDGPUInstrInfo;
1143  let AssemblyParsers = [AMDGPUAsmParser];
1144  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
1145                                VOP3AsmParserVariant,
1146                                SDWAAsmParserVariant,
1147                                SDWA9AsmParserVariant,
1148                                DPPAsmParserVariant];
1149  let AssemblyWriters = [AMDGPUAsmWriter];
1150  let AllowRegisterRenaming = 1;
1151}
1152
1153// Dummy Instruction itineraries for pseudo instructions
1154def ALU_NULL : FuncUnit;
1155def NullALU : InstrItinClass;
1156
1157//===----------------------------------------------------------------------===//
1158// Predicate helper class
1159//===----------------------------------------------------------------------===//
1160
1161def isGFX6 :
1162  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1163  AssemblerPredicate<(all_of FeatureSouthernIslands)>;
1164
1165def isGFX6GFX7 :
1166  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1167            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1168  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
1169
1170def isGFX6GFX7GFX10 :
1171  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1172            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1173            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1174  AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
1175
1176def isGFX7Only :
1177  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1178  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
1179
1180def isGFX7GFX10 :
1181  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1182            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1183  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
1184
1185def isGFX7GFX8GFX9 :
1186  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1187            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1188            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1189  AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
1190
1191def isGFX6GFX7GFX8GFX9 :
1192  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1193            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1194            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1195            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1196  AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
1197
1198def isGFX6GFX7GFX8GFX9NotGFX90A :
1199  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1200            "(Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1201            " Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1202            " Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1203            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1204  AssemblerPredicate<(all_of (not FeatureGFX10Insts), (not FeatureGFX90AInsts))>;
1205
1206def isGFX7Plus :
1207  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1208  AssemblerPredicate<(all_of FeatureCIInsts)>;
1209
1210def isGFX8Plus :
1211  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1212  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1213
1214def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1215                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1216  AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1217
1218def isGFX9Plus :
1219  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1220  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1221
1222def isGFX9Only : Predicate <
1223  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1224  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1225
1226def isGCN3ExcludingGFX90A :
1227  Predicate<"Subtarget->isGCN3Encoding() && !Subtarget->hasGFX90AInsts()">,
1228  AssemblerPredicate<(all_of FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1229
1230def isGFX90APlus :
1231  Predicate<"Subtarget->hasGFX90AInsts()">,
1232  AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1233
1234def isNotGFX90APlus :
1235  Predicate<"!Subtarget->hasGFX90AInsts()">,
1236  AssemblerPredicate<(all_of (not FeatureGFX90AInsts))>;
1237
1238def isGFX8GFX9NotGFX90A :
1239  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1240            "(Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1241            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1242  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1243
1244def isGFX90AOnly :
1245  Predicate<"Subtarget->hasGFX90AInsts()">,
1246  AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1247
1248def isGFX908orGFX90A :
1249  Predicate<"Subtarget->hasMAIInsts()">,
1250  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1251
1252def isGFX8GFX9 :
1253  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1254            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1255  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1256
1257def isGFX10Plus :
1258  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1259  AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1260
1261def isGFX10Before1030 :
1262  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 &&"
1263            "!Subtarget->hasGFX10_3Insts()">,
1264  AssemblerPredicate<(all_of FeatureGFX10Insts,(not FeatureGFX10_3Insts))>;
1265
1266def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1267  AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1268
1269def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1270  AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1271def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1272  AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1273def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1274  AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1275def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1276  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1277
1278def HasFlatScratchSTMode : Predicate<"Subtarget->hasFlatScratchSTMode()">,
1279  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1280
1281def HasGFX10_BEncoding : Predicate<"Subtarget->hasGFX10_BEncoding()">,
1282  AssemblerPredicate<(all_of FeatureGFX10_BEncoding)>;
1283
1284def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1285  AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1286def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1287  AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1288
1289def D16PreservesUnusedBits :
1290  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1291  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1292
1293def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1294def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1295
1296def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1297  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1298
1299def HasLDSFPAtomics : Predicate<"Subtarget->hasLDSFPAtomics()">,
1300  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1301
1302def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1303  AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1304
1305def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1306
1307def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1308  AssemblerPredicate<(all_of Feature16BitInsts)>;
1309def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1310  AssemblerPredicate<(all_of FeatureVOP3P)>;
1311
1312def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
1313def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
1314
1315def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1316  AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1317
1318def HasSDWA9 :
1319  Predicate<"Subtarget->hasSDWA()">,
1320  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1321
1322def HasSDWA10 :
1323  Predicate<"Subtarget->hasSDWA()">,
1324  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1325
1326def HasDPP : Predicate<"Subtarget->hasDPP()">,
1327  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1328
1329def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1330  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1331
1332def Has64BitDPP : Predicate<"Subtarget->has64BitDPP()">,
1333  AssemblerPredicate<(all_of Feature64BitDPP)>;
1334
1335def HasPackedFP32Ops : Predicate<"Subtarget->hasPackedFP32Ops()">,
1336  AssemblerPredicate<(all_of FeaturePackedFP32Ops)>;
1337
1338def HasFmaakFmamkF32Insts :
1339  Predicate<"Subtarget->hasFmaakFmamkF32Insts()">,
1340  AssemblerPredicate<(any_of FeatureGFX10Insts)>;
1341
1342def HasExtendedImageInsts : Predicate<"Subtarget->hasExtendedImageInsts()">,
1343  AssemblerPredicate<(all_of FeatureExtendedImageInsts)>;
1344
1345def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1346  AssemblerPredicate<(all_of FeatureR128A16)>;
1347
1348def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1349  AssemblerPredicate<(all_of FeatureGFX10A16)>;
1350
1351def HasG16 : Predicate<"Subtarget->hasG16()">,
1352  AssemblerPredicate<(all_of FeatureG16)>;
1353
1354def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1355  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1356
1357def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1358  AssemblerPredicate<(all_of FeatureIntClamp)>;
1359
1360def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1361  AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1362
1363def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1364  AssemblerPredicate<(all_of FeatureScalarStores)>;
1365
1366def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1367  AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1368
1369def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1370  AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1371
1372def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1373  AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1374
1375def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1376def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1377def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1378                      AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1379def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1380                AssemblerPredicate<(all_of FeatureMovrel)>;
1381
1382def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1383  AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1384
1385def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1386  AssemblerPredicate<(all_of FeatureDLInsts)>;
1387
1388def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1389  AssemblerPredicate<(all_of FeatureDot1Insts)>;
1390
1391def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1392  AssemblerPredicate<(all_of FeatureDot2Insts)>;
1393
1394def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1395  AssemblerPredicate<(all_of FeatureDot3Insts)>;
1396
1397def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1398  AssemblerPredicate<(all_of FeatureDot4Insts)>;
1399
1400def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1401  AssemblerPredicate<(all_of FeatureDot5Insts)>;
1402
1403def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1404  AssemblerPredicate<(all_of FeatureDot6Insts)>;
1405
1406def HasDot7Insts : Predicate<"Subtarget->hasDot7Insts()">,
1407  AssemblerPredicate<(all_of FeatureDot7Insts)>;
1408
1409def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">,
1410  AssemblerPredicate<(all_of FeatureGetWaveIdInst)>;
1411
1412def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1413  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1414
1415def HasSMemRealTime : Predicate<"Subtarget->hasSMemRealTime()">,
1416  AssemblerPredicate<(all_of FeatureSMemRealTime)>;
1417
1418def HasSMemTimeInst : Predicate<"Subtarget->hasSMemTimeInst()">,
1419  AssemblerPredicate<(all_of FeatureSMemTimeInst)>;
1420
1421def HasShaderCyclesRegister : Predicate<"Subtarget->hasShaderCyclesRegister()">,
1422  AssemblerPredicate<(all_of FeatureShaderCyclesRegister)>;
1423
1424def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1425  AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1426
1427def HasMadMacF32Insts : Predicate<"Subtarget->hasMadMacF32Insts()">,
1428  AssemblerPredicate<(all_of FeatureMadMacF32Insts)>;
1429
1430def HasFmaLegacy32 : Predicate<"Subtarget->hasGFX10_3Insts()">,
1431  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1432
1433def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1434  AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>;
1435
1436def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
1437  AssemblerPredicate<(all_of FeatureDsSrc2Insts)>;
1438
1439def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">,
1440  AssemblerPredicate<(all_of FeatureOffset3fBug)>;
1441
1442def EnableLateCFGStructurize : Predicate<
1443  "EnableLateStructurizeCFG">;
1444
1445def EnableFlatScratch : Predicate<"Subtarget->enableFlatScratch()">;
1446
1447def DisableFlatScratch : Predicate<"!Subtarget->enableFlatScratch()">;
1448
1449def HasUnalignedAccessMode : Predicate<"Subtarget->hasUnalignedAccessMode()">,
1450  AssemblerPredicate<(all_of FeatureUnalignedAccessMode)>;
1451
1452// Include AMDGPU TD files
1453include "SISchedule.td"
1454include "GCNProcessors.td"
1455include "AMDGPUInstrInfo.td"
1456include "SIRegisterInfo.td"
1457include "AMDGPURegisterBanks.td"
1458include "AMDGPUInstructions.td"
1459include "SIInstrInfo.td"
1460include "AMDGPUCallingConv.td"
1461include "AMDGPUSearchableTables.td"
1462