1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 13 14 #include "llvm/Support/TargetRegistry.h" 15 #include "llvm/Target/TargetMachine.h" 16 17 namespace llvm { 18 19 class AMDGPUInstrPrinter; 20 class AMDGPUSubtarget; 21 class AMDGPUTargetMachine; 22 class FunctionPass; 23 struct MachineSchedContext; 24 class MCAsmInfo; 25 class raw_ostream; 26 class ScheduleDAGInstrs; 27 class Target; 28 class TargetMachine; 29 30 // R600 Passes 31 FunctionPass *createR600VectorRegMerger(TargetMachine &tm); 32 FunctionPass *createR600TextureIntrinsicsReplacer(); 33 FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm); 34 FunctionPass *createR600EmitClauseMarkers(); 35 FunctionPass *createR600ClauseMergePass(TargetMachine &tm); 36 FunctionPass *createR600Packetizer(TargetMachine &tm); 37 FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm); 38 FunctionPass *createAMDGPUCFGStructurizerPass(); 39 40 // SI Passes 41 FunctionPass *createSITypeRewriter(); 42 FunctionPass *createSIAnnotateControlFlowPass(); 43 FunctionPass *createSIFoldOperandsPass(); 44 FunctionPass *createSILowerI1CopiesPass(); 45 FunctionPass *createSIShrinkInstructionsPass(); 46 FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm); 47 FunctionPass *createSIWholeQuadModePass(); 48 FunctionPass *createSILowerControlFlowPass(); 49 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 50 FunctionPass *createSIFixSGPRCopiesPass(); 51 FunctionPass *createSIFixSGPRLiveRangesPass(); 52 FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS); 53 FunctionPass *createSIInsertNopsPass(); 54 FunctionPass *createSIInsertWaitsPass(); 55 56 ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C); 57 58 ModulePass *createAMDGPUAnnotateKernelFeaturesPass(); 59 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 60 extern char &AMDGPUAnnotateKernelFeaturesID; 61 62 void initializeSIFoldOperandsPass(PassRegistry &); 63 extern char &SIFoldOperandsID; 64 65 void initializeSIFixSGPRCopiesPass(PassRegistry &); 66 extern char &SIFixSGPRCopiesID; 67 68 void initializeSILowerI1CopiesPass(PassRegistry &); 69 extern char &SILowerI1CopiesID; 70 71 void initializeSILoadStoreOptimizerPass(PassRegistry &); 72 extern char &SILoadStoreOptimizerID; 73 74 void initializeSIWholeQuadModePass(PassRegistry &); 75 extern char &SIWholeQuadModeID; 76 77 void initializeSILowerControlFlowPass(PassRegistry &); 78 extern char &SILowerControlFlowPassID; 79 80 81 // Passes common to R600 and SI 82 FunctionPass *createAMDGPUPromoteAlloca(const TargetMachine *TM = nullptr); 83 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 84 extern char &AMDGPUPromoteAllocaID; 85 86 FunctionPass *createAMDGPUAddDivergenceMetadata(const AMDGPUSubtarget &ST); 87 Pass *createAMDGPUStructurizeCFGPass(); 88 FunctionPass *createAMDGPUISelDag(TargetMachine &tm); 89 ModulePass *createAMDGPUAlwaysInlinePass(); 90 ModulePass *createAMDGPUOpenCLImageTypeLoweringPass(); 91 FunctionPass *createAMDGPUAnnotateUniformValues(); 92 93 void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&); 94 extern char &SIFixControlFlowLiveIntervalsID; 95 96 void initializeSIFixSGPRLiveRangesPass(PassRegistry&); 97 extern char &SIFixSGPRLiveRangesID; 98 99 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 100 extern char &AMDGPUAnnotateUniformValuesPassID; 101 102 void initializeSIAnnotateControlFlowPass(PassRegistry&); 103 extern char &SIAnnotateControlFlowPassID; 104 105 void initializeSIInsertNopsPass(PassRegistry&); 106 extern char &SIInsertNopsID; 107 108 void initializeSIInsertWaitsPass(PassRegistry&); 109 extern char &SIInsertWaitsID; 110 111 extern Target TheAMDGPUTarget; 112 extern Target TheGCNTarget; 113 114 namespace AMDGPU { 115 enum TargetIndex { 116 TI_CONSTDATA_START, 117 TI_SCRATCH_RSRC_DWORD0, 118 TI_SCRATCH_RSRC_DWORD1, 119 TI_SCRATCH_RSRC_DWORD2, 120 TI_SCRATCH_RSRC_DWORD3 121 }; 122 } 123 124 } // End namespace llvm 125 126 namespace ShaderType { 127 enum Type { 128 PIXEL = 0, 129 VERTEX = 1, 130 GEOMETRY = 2, 131 COMPUTE = 3 132 }; 133 } 134 135 /// OpenCL uses address spaces to differentiate between 136 /// various memory regions on the hardware. On the CPU 137 /// all of the address spaces point to the same memory, 138 /// however on the GPU, each address space points to 139 /// a separate piece of memory that is unique from other 140 /// memory locations. 141 namespace AMDGPUAS { 142 enum AddressSpaces : unsigned { 143 PRIVATE_ADDRESS = 0, ///< Address space for private memory. 144 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 145 CONSTANT_ADDRESS = 2, ///< Address space for constant memory 146 LOCAL_ADDRESS = 3, ///< Address space for local memory. 147 FLAT_ADDRESS = 4, ///< Address space for flat memory. 148 REGION_ADDRESS = 5, ///< Address space for region memory. 149 PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0) 150 PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1) 151 152 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this 153 // order to be able to dynamically index a constant buffer, for example: 154 // 155 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 156 157 CONSTANT_BUFFER_0 = 8, 158 CONSTANT_BUFFER_1 = 9, 159 CONSTANT_BUFFER_2 = 10, 160 CONSTANT_BUFFER_3 = 11, 161 CONSTANT_BUFFER_4 = 12, 162 CONSTANT_BUFFER_5 = 13, 163 CONSTANT_BUFFER_6 = 14, 164 CONSTANT_BUFFER_7 = 15, 165 CONSTANT_BUFFER_8 = 16, 166 CONSTANT_BUFFER_9 = 17, 167 CONSTANT_BUFFER_10 = 18, 168 CONSTANT_BUFFER_11 = 19, 169 CONSTANT_BUFFER_12 = 20, 170 CONSTANT_BUFFER_13 = 21, 171 CONSTANT_BUFFER_14 = 22, 172 CONSTANT_BUFFER_15 = 23, 173 ADDRESS_NONE = 24, ///< Address space for unknown memory. 174 LAST_ADDRESS = ADDRESS_NONE, 175 176 // Some places use this if the address space can't be determined. 177 UNKNOWN_ADDRESS_SPACE = ~0u 178 }; 179 180 } // namespace AMDGPUAS 181 182 #endif 183