1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 /// \file 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12 13 #include "llvm/IR/IntrinsicsR600.h" // TODO: Sink this. 14 #include "llvm/IR/IntrinsicsAMDGPU.h" // TODO: Sink this. 15 #include "llvm/Support/CodeGen.h" 16 17 namespace llvm { 18 19 class AMDGPUTargetMachine; 20 class FunctionPass; 21 class GCNTargetMachine; 22 class ImmutablePass; 23 class ModulePass; 24 class Pass; 25 class Target; 26 class TargetMachine; 27 class TargetOptions; 28 class PassRegistry; 29 class Module; 30 31 // GlobalISel passes 32 void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &); 33 FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone); 34 void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &); 35 FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone); 36 FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone); 37 void initializeAMDGPURegBankCombinerPass(PassRegistry &); 38 39 // R600 Passes 40 FunctionPass *createR600VectorRegMerger(); 41 FunctionPass *createR600ExpandSpecialInstrsPass(); 42 FunctionPass *createR600EmitClauseMarkers(); 43 FunctionPass *createR600ClauseMergePass(); 44 FunctionPass *createR600Packetizer(); 45 FunctionPass *createR600ControlFlowFinalizer(); 46 FunctionPass *createAMDGPUCFGStructurizerPass(); 47 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel); 48 49 // SI Passes 50 FunctionPass *createGCNDPPCombinePass(); 51 FunctionPass *createSIAnnotateControlFlowPass(); 52 FunctionPass *createSIFoldOperandsPass(); 53 FunctionPass *createSIPeepholeSDWAPass(); 54 FunctionPass *createSILowerI1CopiesPass(); 55 FunctionPass *createSIAddIMGInitPass(); 56 FunctionPass *createSIShrinkInstructionsPass(); 57 FunctionPass *createSILoadStoreOptimizerPass(); 58 FunctionPass *createSIWholeQuadModePass(); 59 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 60 FunctionPass *createSIOptimizeExecMaskingPreRAPass(); 61 FunctionPass *createSIFixSGPRCopiesPass(); 62 FunctionPass *createSIMemoryLegalizerPass(); 63 FunctionPass *createSIInsertWaitcntsPass(); 64 FunctionPass *createSIPreAllocateWWMRegsPass(); 65 FunctionPass *createSIFormMemoryClausesPass(); 66 67 FunctionPass *createSIPostRABundlerPass(); 68 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetMachine *); 69 FunctionPass *createAMDGPUUseNativeCallsPass(); 70 FunctionPass *createAMDGPUCodeGenPreparePass(); 71 FunctionPass *createAMDGPUMachineCFGStructurizerPass(); 72 FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *); 73 ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *); 74 FunctionPass *createAMDGPURewriteOutArgumentsPass(); 75 FunctionPass *createSIModeRegisterPass(); 76 77 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&); 78 79 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&); 80 extern char &AMDGPUMachineCFGStructurizerID; 81 82 void initializeAMDGPUAlwaysInlinePass(PassRegistry&); 83 84 Pass *createAMDGPUAnnotateKernelFeaturesPass(); 85 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 86 extern char &AMDGPUAnnotateKernelFeaturesID; 87 88 FunctionPass *createAMDGPUAtomicOptimizerPass(); 89 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &); 90 extern char &AMDGPUAtomicOptimizerID; 91 92 ModulePass *createAMDGPULowerIntrinsicsPass(); 93 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &); 94 extern char &AMDGPULowerIntrinsicsID; 95 96 ModulePass *createAMDGPUFixFunctionBitcastsPass(); 97 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &); 98 extern char &AMDGPUFixFunctionBitcastsID; 99 100 FunctionPass *createAMDGPULowerKernelArgumentsPass(); 101 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &); 102 extern char &AMDGPULowerKernelArgumentsID; 103 104 ModulePass *createAMDGPULowerKernelAttributesPass(); 105 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &); 106 extern char &AMDGPULowerKernelAttributesID; 107 108 void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &); 109 extern char &AMDGPUPropagateAttributesEarlyID; 110 111 void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &); 112 extern char &AMDGPUPropagateAttributesLateID; 113 114 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &); 115 extern char &AMDGPURewriteOutArgumentsID; 116 117 void initializeGCNDPPCombinePass(PassRegistry &); 118 extern char &GCNDPPCombineID; 119 120 void initializeR600ClauseMergePassPass(PassRegistry &); 121 extern char &R600ClauseMergePassID; 122 123 void initializeR600ControlFlowFinalizerPass(PassRegistry &); 124 extern char &R600ControlFlowFinalizerID; 125 126 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &); 127 extern char &R600ExpandSpecialInstrsPassID; 128 129 void initializeR600VectorRegMergerPass(PassRegistry &); 130 extern char &R600VectorRegMergerID; 131 132 void initializeR600PacketizerPass(PassRegistry &); 133 extern char &R600PacketizerID; 134 135 void initializeSIFoldOperandsPass(PassRegistry &); 136 extern char &SIFoldOperandsID; 137 138 void initializeSIPeepholeSDWAPass(PassRegistry &); 139 extern char &SIPeepholeSDWAID; 140 141 void initializeSIShrinkInstructionsPass(PassRegistry&); 142 extern char &SIShrinkInstructionsID; 143 144 void initializeSIFixSGPRCopiesPass(PassRegistry &); 145 extern char &SIFixSGPRCopiesID; 146 147 void initializeSIFixVGPRCopiesPass(PassRegistry &); 148 extern char &SIFixVGPRCopiesID; 149 150 void initializeSILowerI1CopiesPass(PassRegistry &); 151 extern char &SILowerI1CopiesID; 152 153 void initializeSILowerSGPRSpillsPass(PassRegistry &); 154 extern char &SILowerSGPRSpillsID; 155 156 void initializeSILoadStoreOptimizerPass(PassRegistry &); 157 extern char &SILoadStoreOptimizerID; 158 159 void initializeSIWholeQuadModePass(PassRegistry &); 160 extern char &SIWholeQuadModeID; 161 162 void initializeSILowerControlFlowPass(PassRegistry &); 163 extern char &SILowerControlFlowID; 164 165 void initializeSIRemoveShortExecBranchesPass(PassRegistry &); 166 extern char &SIRemoveShortExecBranchesID; 167 168 void initializeSIPreEmitPeepholePass(PassRegistry &); 169 extern char &SIPreEmitPeepholeID; 170 171 void initializeSIInsertSkipsPass(PassRegistry &); 172 extern char &SIInsertSkipsPassID; 173 174 void initializeSIOptimizeExecMaskingPass(PassRegistry &); 175 extern char &SIOptimizeExecMaskingID; 176 177 void initializeSIPreAllocateWWMRegsPass(PassRegistry &); 178 extern char &SIPreAllocateWWMRegsID; 179 180 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &); 181 extern char &AMDGPUSimplifyLibCallsID; 182 183 void initializeAMDGPUUseNativeCallsPass(PassRegistry &); 184 extern char &AMDGPUUseNativeCallsID; 185 186 void initializeSIAddIMGInitPass(PassRegistry &); 187 extern char &SIAddIMGInitID; 188 189 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &); 190 extern char &AMDGPUPerfHintAnalysisID; 191 192 // Passes common to R600 and SI 193 FunctionPass *createAMDGPUPromoteAlloca(); 194 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 195 extern char &AMDGPUPromoteAllocaID; 196 197 FunctionPass *createAMDGPUPromoteAllocaToVector(); 198 void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry&); 199 extern char &AMDGPUPromoteAllocaToVectorID; 200 201 Pass *createAMDGPUStructurizeCFGPass(); 202 FunctionPass *createAMDGPUISelDag( 203 TargetMachine *TM = nullptr, 204 CodeGenOpt::Level OptLevel = CodeGenOpt::Default); 205 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true); 206 ModulePass *createR600OpenCLImageTypeLoweringPass(); 207 FunctionPass *createAMDGPUAnnotateUniformValues(); 208 209 ModulePass *createAMDGPUPrintfRuntimeBinding(); 210 void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&); 211 extern char &AMDGPUPrintfRuntimeBindingID; 212 213 ModulePass* createAMDGPUUnifyMetadataPass(); 214 void initializeAMDGPUUnifyMetadataPass(PassRegistry&); 215 extern char &AMDGPUUnifyMetadataID; 216 217 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&); 218 extern char &SIOptimizeExecMaskingPreRAID; 219 220 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 221 extern char &AMDGPUAnnotateUniformValuesPassID; 222 223 void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 224 extern char &AMDGPUCodeGenPrepareID; 225 226 void initializeSIAnnotateControlFlowPass(PassRegistry&); 227 extern char &SIAnnotateControlFlowPassID; 228 229 void initializeSIMemoryLegalizerPass(PassRegistry&); 230 extern char &SIMemoryLegalizerID; 231 232 void initializeSIModeRegisterPass(PassRegistry&); 233 extern char &SIModeRegisterID; 234 235 void initializeSIInsertHardClausesPass(PassRegistry &); 236 extern char &SIInsertHardClausesID; 237 238 void initializeSIInsertWaitcntsPass(PassRegistry&); 239 extern char &SIInsertWaitcntsID; 240 241 void initializeSIFormMemoryClausesPass(PassRegistry&); 242 extern char &SIFormMemoryClausesID; 243 244 void initializeSIPostRABundlerPass(PassRegistry&); 245 extern char &SIPostRABundlerID; 246 247 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&); 248 extern char &AMDGPUUnifyDivergentExitNodesID; 249 250 ImmutablePass *createAMDGPUAAWrapperPass(); 251 void initializeAMDGPUAAWrapperPassPass(PassRegistry&); 252 ImmutablePass *createAMDGPUExternalAAWrapperPass(); 253 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&); 254 255 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &); 256 257 Pass *createAMDGPUFunctionInliningPass(); 258 void initializeAMDGPUInlinerPass(PassRegistry&); 259 260 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass(); 261 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &); 262 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID; 263 264 void initializeGCNRegBankReassignPass(PassRegistry &); 265 extern char &GCNRegBankReassignID; 266 267 void initializeGCNNSAReassignPass(PassRegistry &); 268 extern char &GCNNSAReassignID; 269 270 namespace AMDGPU { 271 enum TargetIndex { 272 TI_CONSTDATA_START, 273 TI_SCRATCH_RSRC_DWORD0, 274 TI_SCRATCH_RSRC_DWORD1, 275 TI_SCRATCH_RSRC_DWORD2, 276 TI_SCRATCH_RSRC_DWORD3 277 }; 278 } 279 280 /// OpenCL uses address spaces to differentiate between 281 /// various memory regions on the hardware. On the CPU 282 /// all of the address spaces point to the same memory, 283 /// however on the GPU, each address space points to 284 /// a separate piece of memory that is unique from other 285 /// memory locations. 286 namespace AMDGPUAS { 287 enum : unsigned { 288 // The maximum value for flat, generic, local, private, constant and region. 289 MAX_AMDGPU_ADDRESS = 7, 290 291 FLAT_ADDRESS = 0, ///< Address space for flat memory. 292 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 293 REGION_ADDRESS = 2, ///< Address space for region memory. (GDS) 294 295 CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2). 296 LOCAL_ADDRESS = 3, ///< Address space for local memory. 297 PRIVATE_ADDRESS = 5, ///< Address space for private memory. 298 299 CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory. 300 301 BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers. 302 303 /// Address space for direct addressible parameter memory (CONST0). 304 PARAM_D_ADDRESS = 6, 305 /// Address space for indirect addressible parameter memory (VTX1). 306 PARAM_I_ADDRESS = 7, 307 308 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on 309 // this order to be able to dynamically index a constant buffer, for 310 // example: 311 // 312 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 313 314 CONSTANT_BUFFER_0 = 8, 315 CONSTANT_BUFFER_1 = 9, 316 CONSTANT_BUFFER_2 = 10, 317 CONSTANT_BUFFER_3 = 11, 318 CONSTANT_BUFFER_4 = 12, 319 CONSTANT_BUFFER_5 = 13, 320 CONSTANT_BUFFER_6 = 14, 321 CONSTANT_BUFFER_7 = 15, 322 CONSTANT_BUFFER_8 = 16, 323 CONSTANT_BUFFER_9 = 17, 324 CONSTANT_BUFFER_10 = 18, 325 CONSTANT_BUFFER_11 = 19, 326 CONSTANT_BUFFER_12 = 20, 327 CONSTANT_BUFFER_13 = 21, 328 CONSTANT_BUFFER_14 = 22, 329 CONSTANT_BUFFER_15 = 23, 330 331 // Some places use this if the address space can't be determined. 332 UNKNOWN_ADDRESS_SPACE = ~0u, 333 }; 334 } 335 336 namespace AMDGPU { 337 338 // FIXME: Missing constant_32bit 339 inline bool isFlatGlobalAddrSpace(unsigned AS) { 340 return AS == AMDGPUAS::GLOBAL_ADDRESS || 341 AS == AMDGPUAS::FLAT_ADDRESS || 342 AS == AMDGPUAS::CONSTANT_ADDRESS || 343 AS > AMDGPUAS::MAX_AMDGPU_ADDRESS; 344 } 345 } 346 347 } // End namespace llvm 348 349 #endif 350