1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 /// \file 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12 13 #include "llvm/Target/TargetMachine.h" 14 15 namespace llvm { 16 17 class AMDGPUTargetMachine; 18 class FunctionPass; 19 class GCNTargetMachine; 20 class ModulePass; 21 class Pass; 22 class Target; 23 class TargetMachine; 24 class TargetOptions; 25 class PassRegistry; 26 class Module; 27 28 // R600 Passes 29 FunctionPass *createR600VectorRegMerger(); 30 FunctionPass *createR600ExpandSpecialInstrsPass(); 31 FunctionPass *createR600EmitClauseMarkers(); 32 FunctionPass *createR600ClauseMergePass(); 33 FunctionPass *createR600Packetizer(); 34 FunctionPass *createR600ControlFlowFinalizer(); 35 FunctionPass *createAMDGPUCFGStructurizerPass(); 36 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel); 37 38 // SI Passes 39 FunctionPass *createGCNDPPCombinePass(); 40 FunctionPass *createSIAnnotateControlFlowPass(); 41 FunctionPass *createSIFoldOperandsPass(); 42 FunctionPass *createSIPeepholeSDWAPass(); 43 FunctionPass *createSILowerI1CopiesPass(); 44 FunctionPass *createSIFixupVectorISelPass(); 45 FunctionPass *createSIAddIMGInitPass(); 46 FunctionPass *createSIShrinkInstructionsPass(); 47 FunctionPass *createSILoadStoreOptimizerPass(); 48 FunctionPass *createSIWholeQuadModePass(); 49 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 50 FunctionPass *createSIOptimizeExecMaskingPreRAPass(); 51 FunctionPass *createSIFixSGPRCopiesPass(); 52 FunctionPass *createSIMemoryLegalizerPass(); 53 FunctionPass *createSIInsertWaitcntsPass(); 54 FunctionPass *createSIPreAllocateWWMRegsPass(); 55 FunctionPass *createSIFormMemoryClausesPass(); 56 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &); 57 FunctionPass *createAMDGPUUseNativeCallsPass(); 58 FunctionPass *createAMDGPUCodeGenPreparePass(); 59 FunctionPass *createAMDGPUMachineCFGStructurizerPass(); 60 FunctionPass *createAMDGPURewriteOutArgumentsPass(); 61 FunctionPass *createSIModeRegisterPass(); 62 63 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&); 64 65 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&); 66 extern char &AMDGPUMachineCFGStructurizerID; 67 68 void initializeAMDGPUAlwaysInlinePass(PassRegistry&); 69 70 Pass *createAMDGPUAnnotateKernelFeaturesPass(); 71 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 72 extern char &AMDGPUAnnotateKernelFeaturesID; 73 74 FunctionPass *createAMDGPUAtomicOptimizerPass(); 75 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &); 76 extern char &AMDGPUAtomicOptimizerID; 77 78 ModulePass *createAMDGPULowerIntrinsicsPass(); 79 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &); 80 extern char &AMDGPULowerIntrinsicsID; 81 82 ModulePass *createAMDGPUFixFunctionBitcastsPass(); 83 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &); 84 extern char &AMDGPUFixFunctionBitcastsID; 85 86 FunctionPass *createAMDGPULowerKernelArgumentsPass(); 87 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &); 88 extern char &AMDGPULowerKernelArgumentsID; 89 90 ModulePass *createAMDGPULowerKernelAttributesPass(); 91 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &); 92 extern char &AMDGPULowerKernelAttributesID; 93 94 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &); 95 extern char &AMDGPURewriteOutArgumentsID; 96 97 void initializeGCNDPPCombinePass(PassRegistry &); 98 extern char &GCNDPPCombineID; 99 100 void initializeR600ClauseMergePassPass(PassRegistry &); 101 extern char &R600ClauseMergePassID; 102 103 void initializeR600ControlFlowFinalizerPass(PassRegistry &); 104 extern char &R600ControlFlowFinalizerID; 105 106 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &); 107 extern char &R600ExpandSpecialInstrsPassID; 108 109 void initializeR600VectorRegMergerPass(PassRegistry &); 110 extern char &R600VectorRegMergerID; 111 112 void initializeR600PacketizerPass(PassRegistry &); 113 extern char &R600PacketizerID; 114 115 void initializeSIFoldOperandsPass(PassRegistry &); 116 extern char &SIFoldOperandsID; 117 118 void initializeSIPeepholeSDWAPass(PassRegistry &); 119 extern char &SIPeepholeSDWAID; 120 121 void initializeSIShrinkInstructionsPass(PassRegistry&); 122 extern char &SIShrinkInstructionsID; 123 124 void initializeSIFixSGPRCopiesPass(PassRegistry &); 125 extern char &SIFixSGPRCopiesID; 126 127 void initializeSIFixVGPRCopiesPass(PassRegistry &); 128 extern char &SIFixVGPRCopiesID; 129 130 void initializeSIFixupVectorISelPass(PassRegistry &); 131 extern char &SIFixupVectorISelID; 132 133 void initializeSILowerI1CopiesPass(PassRegistry &); 134 extern char &SILowerI1CopiesID; 135 136 void initializeSILoadStoreOptimizerPass(PassRegistry &); 137 extern char &SILoadStoreOptimizerID; 138 139 void initializeSIWholeQuadModePass(PassRegistry &); 140 extern char &SIWholeQuadModeID; 141 142 void initializeSILowerControlFlowPass(PassRegistry &); 143 extern char &SILowerControlFlowID; 144 145 void initializeSIInsertSkipsPass(PassRegistry &); 146 extern char &SIInsertSkipsPassID; 147 148 void initializeSIOptimizeExecMaskingPass(PassRegistry &); 149 extern char &SIOptimizeExecMaskingID; 150 151 void initializeSIPreAllocateWWMRegsPass(PassRegistry &); 152 extern char &SIPreAllocateWWMRegsID; 153 154 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &); 155 extern char &AMDGPUSimplifyLibCallsID; 156 157 void initializeAMDGPUUseNativeCallsPass(PassRegistry &); 158 extern char &AMDGPUUseNativeCallsID; 159 160 void initializeSIAddIMGInitPass(PassRegistry &); 161 extern char &SIAddIMGInitID; 162 163 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &); 164 extern char &AMDGPUPerfHintAnalysisID; 165 166 // Passes common to R600 and SI 167 FunctionPass *createAMDGPUPromoteAlloca(); 168 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 169 extern char &AMDGPUPromoteAllocaID; 170 171 Pass *createAMDGPUStructurizeCFGPass(); 172 FunctionPass *createAMDGPUISelDag( 173 TargetMachine *TM = nullptr, 174 CodeGenOpt::Level OptLevel = CodeGenOpt::Default); 175 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true); 176 ModulePass *createR600OpenCLImageTypeLoweringPass(); 177 FunctionPass *createAMDGPUAnnotateUniformValues(); 178 179 ModulePass* createAMDGPUUnifyMetadataPass(); 180 void initializeAMDGPUUnifyMetadataPass(PassRegistry&); 181 extern char &AMDGPUUnifyMetadataID; 182 183 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&); 184 extern char &SIOptimizeExecMaskingPreRAID; 185 186 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 187 extern char &AMDGPUAnnotateUniformValuesPassID; 188 189 void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 190 extern char &AMDGPUCodeGenPrepareID; 191 192 void initializeSIAnnotateControlFlowPass(PassRegistry&); 193 extern char &SIAnnotateControlFlowPassID; 194 195 void initializeSIMemoryLegalizerPass(PassRegistry&); 196 extern char &SIMemoryLegalizerID; 197 198 void initializeSIModeRegisterPass(PassRegistry&); 199 extern char &SIModeRegisterID; 200 201 void initializeSIInsertWaitcntsPass(PassRegistry&); 202 extern char &SIInsertWaitcntsID; 203 204 void initializeSIFormMemoryClausesPass(PassRegistry&); 205 extern char &SIFormMemoryClausesID; 206 207 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&); 208 extern char &AMDGPUUnifyDivergentExitNodesID; 209 210 ImmutablePass *createAMDGPUAAWrapperPass(); 211 void initializeAMDGPUAAWrapperPassPass(PassRegistry&); 212 ImmutablePass *createAMDGPUExternalAAWrapperPass(); 213 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&); 214 215 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &); 216 217 Pass *createAMDGPUFunctionInliningPass(); 218 void initializeAMDGPUInlinerPass(PassRegistry&); 219 220 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass(); 221 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &); 222 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID; 223 224 Target &getTheAMDGPUTarget(); 225 Target &getTheGCNTarget(); 226 227 namespace AMDGPU { 228 enum TargetIndex { 229 TI_CONSTDATA_START, 230 TI_SCRATCH_RSRC_DWORD0, 231 TI_SCRATCH_RSRC_DWORD1, 232 TI_SCRATCH_RSRC_DWORD2, 233 TI_SCRATCH_RSRC_DWORD3 234 }; 235 } 236 237 } // End namespace llvm 238 239 /// OpenCL uses address spaces to differentiate between 240 /// various memory regions on the hardware. On the CPU 241 /// all of the address spaces point to the same memory, 242 /// however on the GPU, each address space points to 243 /// a separate piece of memory that is unique from other 244 /// memory locations. 245 namespace AMDGPUAS { 246 enum : unsigned { 247 // The maximum value for flat, generic, local, private, constant and region. 248 MAX_AMDGPU_ADDRESS = 7, 249 250 FLAT_ADDRESS = 0, ///< Address space for flat memory. 251 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 252 REGION_ADDRESS = 2, ///< Address space for region memory. (GDS) 253 254 CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2). 255 LOCAL_ADDRESS = 3, ///< Address space for local memory. 256 PRIVATE_ADDRESS = 5, ///< Address space for private memory. 257 258 CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory. 259 260 BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers. 261 262 /// Address space for direct addressible parameter memory (CONST0). 263 PARAM_D_ADDRESS = 6, 264 /// Address space for indirect addressible parameter memory (VTX1). 265 PARAM_I_ADDRESS = 7, 266 267 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on 268 // this order to be able to dynamically index a constant buffer, for 269 // example: 270 // 271 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 272 273 CONSTANT_BUFFER_0 = 8, 274 CONSTANT_BUFFER_1 = 9, 275 CONSTANT_BUFFER_2 = 10, 276 CONSTANT_BUFFER_3 = 11, 277 CONSTANT_BUFFER_4 = 12, 278 CONSTANT_BUFFER_5 = 13, 279 CONSTANT_BUFFER_6 = 14, 280 CONSTANT_BUFFER_7 = 15, 281 CONSTANT_BUFFER_8 = 16, 282 CONSTANT_BUFFER_9 = 17, 283 CONSTANT_BUFFER_10 = 18, 284 CONSTANT_BUFFER_11 = 19, 285 CONSTANT_BUFFER_12 = 20, 286 CONSTANT_BUFFER_13 = 21, 287 CONSTANT_BUFFER_14 = 22, 288 CONSTANT_BUFFER_15 = 23, 289 290 // Some places use this if the address space can't be determined. 291 UNKNOWN_ADDRESS_SPACE = ~0u, 292 }; 293 } 294 295 #endif 296