1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12 
13 #include "llvm/IR/PassManager.h"
14 #include "llvm/Support/CodeGen.h"
15 
16 namespace llvm {
17 
18 class FunctionPass;
19 class GCNTargetMachine;
20 class ImmutablePass;
21 class ModulePass;
22 class Pass;
23 class Target;
24 class TargetMachine;
25 class TargetOptions;
26 class PassRegistry;
27 class Module;
28 
29 // GlobalISel passes
30 void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);
31 FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);
32 void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &);
33 FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
34 FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone);
35 void initializeAMDGPURegBankCombinerPass(PassRegistry &);
36 
37 // R600 Passes
38 FunctionPass *createR600VectorRegMerger();
39 FunctionPass *createR600ExpandSpecialInstrsPass();
40 FunctionPass *createR600EmitClauseMarkers();
41 FunctionPass *createR600ClauseMergePass();
42 FunctionPass *createR600Packetizer();
43 FunctionPass *createR600ControlFlowFinalizer();
44 FunctionPass *createAMDGPUCFGStructurizerPass();
45 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
46 
47 // SI Passes
48 FunctionPass *createGCNDPPCombinePass();
49 FunctionPass *createSIAnnotateControlFlowPass();
50 FunctionPass *createSIFoldOperandsPass();
51 FunctionPass *createSIPeepholeSDWAPass();
52 FunctionPass *createSILowerI1CopiesPass();
53 FunctionPass *createSIAddIMGInitPass();
54 FunctionPass *createSIShrinkInstructionsPass();
55 FunctionPass *createSILoadStoreOptimizerPass();
56 FunctionPass *createSIWholeQuadModePass();
57 FunctionPass *createSIFixControlFlowLiveIntervalsPass();
58 FunctionPass *createSIOptimizeExecMaskingPreRAPass();
59 FunctionPass *createSIFixSGPRCopiesPass();
60 FunctionPass *createSIMemoryLegalizerPass();
61 FunctionPass *createSIInsertWaitcntsPass();
62 FunctionPass *createSIPreAllocateWWMRegsPass();
63 FunctionPass *createSIFormMemoryClausesPass();
64 
65 FunctionPass *createSIPostRABundlerPass();
66 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetMachine *);
67 FunctionPass *createAMDGPUUseNativeCallsPass();
68 FunctionPass *createAMDGPUCodeGenPreparePass();
69 FunctionPass *createAMDGPULateCodeGenPreparePass();
70 FunctionPass *createAMDGPUMachineCFGStructurizerPass();
71 FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *);
72 ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *);
73 FunctionPass *createAMDGPURewriteOutArgumentsPass();
74 ModulePass *createAMDGPULowerModuleLDSPass();
75 FunctionPass *createSIModeRegisterPass();
76 
77 struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> {
78   AMDGPUSimplifyLibCallsPass(TargetMachine &TM) : TM(TM) {}
79   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
80 
81 private:
82   TargetMachine &TM;
83 };
84 
85 struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
86   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
87 };
88 
89 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
90 
91 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
92 extern char &AMDGPUMachineCFGStructurizerID;
93 
94 void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
95 
96 Pass *createAMDGPUAnnotateKernelFeaturesPass();
97 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
98 extern char &AMDGPUAnnotateKernelFeaturesID;
99 
100 FunctionPass *createAMDGPUAtomicOptimizerPass();
101 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
102 extern char &AMDGPUAtomicOptimizerID;
103 
104 ModulePass *createAMDGPULowerIntrinsicsPass();
105 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
106 extern char &AMDGPULowerIntrinsicsID;
107 
108 ModulePass *createAMDGPUFixFunctionBitcastsPass();
109 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &);
110 extern char &AMDGPUFixFunctionBitcastsID;
111 
112 FunctionPass *createAMDGPULowerKernelArgumentsPass();
113 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
114 extern char &AMDGPULowerKernelArgumentsID;
115 
116 ModulePass *createAMDGPULowerKernelAttributesPass();
117 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
118 extern char &AMDGPULowerKernelAttributesID;
119 
120 struct AMDGPULowerKernelAttributesPass
121     : PassInfoMixin<AMDGPULowerKernelAttributesPass> {
122   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
123 };
124 
125 void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &);
126 extern char &AMDGPUPropagateAttributesEarlyID;
127 
128 struct AMDGPUPropagateAttributesEarlyPass
129     : PassInfoMixin<AMDGPUPropagateAttributesEarlyPass> {
130   AMDGPUPropagateAttributesEarlyPass(TargetMachine &TM) : TM(TM) {}
131   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
132 
133 private:
134   TargetMachine &TM;
135 };
136 
137 void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &);
138 extern char &AMDGPUPropagateAttributesLateID;
139 
140 struct AMDGPUPropagateAttributesLatePass
141     : PassInfoMixin<AMDGPUPropagateAttributesLatePass> {
142   AMDGPUPropagateAttributesLatePass(TargetMachine &TM) : TM(TM) {}
143   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
144 
145 private:
146   TargetMachine &TM;
147 };
148 
149 void initializeAMDGPULowerModuleLDSPass(PassRegistry &);
150 extern char &AMDGPULowerModuleLDSID;
151 
152 struct AMDGPULowerModuleLDSPass : PassInfoMixin<AMDGPULowerModuleLDSPass> {
153   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
154 };
155 
156 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
157 extern char &AMDGPURewriteOutArgumentsID;
158 
159 void initializeGCNDPPCombinePass(PassRegistry &);
160 extern char &GCNDPPCombineID;
161 
162 void initializeR600ClauseMergePassPass(PassRegistry &);
163 extern char &R600ClauseMergePassID;
164 
165 void initializeR600ControlFlowFinalizerPass(PassRegistry &);
166 extern char &R600ControlFlowFinalizerID;
167 
168 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &);
169 extern char &R600ExpandSpecialInstrsPassID;
170 
171 void initializeR600VectorRegMergerPass(PassRegistry &);
172 extern char &R600VectorRegMergerID;
173 
174 void initializeR600PacketizerPass(PassRegistry &);
175 extern char &R600PacketizerID;
176 
177 void initializeSIFoldOperandsPass(PassRegistry &);
178 extern char &SIFoldOperandsID;
179 
180 void initializeSIPeepholeSDWAPass(PassRegistry &);
181 extern char &SIPeepholeSDWAID;
182 
183 void initializeSIShrinkInstructionsPass(PassRegistry&);
184 extern char &SIShrinkInstructionsID;
185 
186 void initializeSIFixSGPRCopiesPass(PassRegistry &);
187 extern char &SIFixSGPRCopiesID;
188 
189 void initializeSIFixVGPRCopiesPass(PassRegistry &);
190 extern char &SIFixVGPRCopiesID;
191 
192 void initializeSILowerI1CopiesPass(PassRegistry &);
193 extern char &SILowerI1CopiesID;
194 
195 void initializeSILowerSGPRSpillsPass(PassRegistry &);
196 extern char &SILowerSGPRSpillsID;
197 
198 void initializeSILoadStoreOptimizerPass(PassRegistry &);
199 extern char &SILoadStoreOptimizerID;
200 
201 void initializeSIWholeQuadModePass(PassRegistry &);
202 extern char &SIWholeQuadModeID;
203 
204 void initializeSILowerControlFlowPass(PassRegistry &);
205 extern char &SILowerControlFlowID;
206 
207 void initializeSIPreEmitPeepholePass(PassRegistry &);
208 extern char &SIPreEmitPeepholeID;
209 
210 void initializeSILateBranchLoweringPass(PassRegistry &);
211 extern char &SILateBranchLoweringPassID;
212 
213 void initializeSIOptimizeExecMaskingPass(PassRegistry &);
214 extern char &SIOptimizeExecMaskingID;
215 
216 void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
217 extern char &SIPreAllocateWWMRegsID;
218 
219 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &);
220 extern char &AMDGPUSimplifyLibCallsID;
221 
222 void initializeAMDGPUUseNativeCallsPass(PassRegistry &);
223 extern char &AMDGPUUseNativeCallsID;
224 
225 void initializeSIAddIMGInitPass(PassRegistry &);
226 extern char &SIAddIMGInitID;
227 
228 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &);
229 extern char &AMDGPUPerfHintAnalysisID;
230 
231 // Passes common to R600 and SI
232 FunctionPass *createAMDGPUPromoteAlloca();
233 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
234 extern char &AMDGPUPromoteAllocaID;
235 
236 FunctionPass *createAMDGPUPromoteAllocaToVector();
237 void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry&);
238 extern char &AMDGPUPromoteAllocaToVectorID;
239 
240 struct AMDGPUPromoteAllocaPass : PassInfoMixin<AMDGPUPromoteAllocaPass> {
241   AMDGPUPromoteAllocaPass(TargetMachine &TM) : TM(TM) {}
242   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
243 
244 private:
245   TargetMachine &TM;
246 };
247 
248 struct AMDGPUPromoteAllocaToVectorPass
249     : PassInfoMixin<AMDGPUPromoteAllocaToVectorPass> {
250   AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM) : TM(TM) {}
251   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
252 
253 private:
254   TargetMachine &TM;
255 };
256 
257 Pass *createAMDGPUStructurizeCFGPass();
258 FunctionPass *createAMDGPUISelDag(
259   TargetMachine *TM = nullptr,
260   CodeGenOpt::Level OptLevel = CodeGenOpt::Default);
261 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
262 
263 struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> {
264   AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {}
265   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
266 
267 private:
268   bool GlobalOpt;
269 };
270 
271 ModulePass *createR600OpenCLImageTypeLoweringPass();
272 FunctionPass *createAMDGPUAnnotateUniformValues();
273 
274 ModulePass *createAMDGPUPrintfRuntimeBinding();
275 void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
276 extern char &AMDGPUPrintfRuntimeBindingID;
277 
278 struct AMDGPUPrintfRuntimeBindingPass
279     : PassInfoMixin<AMDGPUPrintfRuntimeBindingPass> {
280   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
281 };
282 
283 ModulePass* createAMDGPUUnifyMetadataPass();
284 void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
285 extern char &AMDGPUUnifyMetadataID;
286 
287 struct AMDGPUUnifyMetadataPass : PassInfoMixin<AMDGPUUnifyMetadataPass> {
288   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
289 };
290 
291 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
292 extern char &SIOptimizeExecMaskingPreRAID;
293 
294 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
295 extern char &AMDGPUAnnotateUniformValuesPassID;
296 
297 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
298 extern char &AMDGPUCodeGenPrepareID;
299 
300 void initializeAMDGPULateCodeGenPreparePass(PassRegistry &);
301 extern char &AMDGPULateCodeGenPrepareID;
302 
303 void initializeSIAnnotateControlFlowPass(PassRegistry&);
304 extern char &SIAnnotateControlFlowPassID;
305 
306 void initializeSIMemoryLegalizerPass(PassRegistry&);
307 extern char &SIMemoryLegalizerID;
308 
309 void initializeSIModeRegisterPass(PassRegistry&);
310 extern char &SIModeRegisterID;
311 
312 void initializeSIInsertHardClausesPass(PassRegistry &);
313 extern char &SIInsertHardClausesID;
314 
315 void initializeSIInsertWaitcntsPass(PassRegistry&);
316 extern char &SIInsertWaitcntsID;
317 
318 void initializeSIFormMemoryClausesPass(PassRegistry&);
319 extern char &SIFormMemoryClausesID;
320 
321 void initializeSIPostRABundlerPass(PassRegistry&);
322 extern char &SIPostRABundlerID;
323 
324 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
325 extern char &AMDGPUUnifyDivergentExitNodesID;
326 
327 ImmutablePass *createAMDGPUAAWrapperPass();
328 void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
329 ImmutablePass *createAMDGPUExternalAAWrapperPass();
330 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
331 
332 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
333 
334 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass();
335 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &);
336 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID;
337 
338 void initializeGCNRegBankReassignPass(PassRegistry &);
339 extern char &GCNRegBankReassignID;
340 
341 void initializeGCNNSAReassignPass(PassRegistry &);
342 extern char &GCNNSAReassignID;
343 
344 namespace AMDGPU {
345 enum TargetIndex {
346   TI_CONSTDATA_START,
347   TI_SCRATCH_RSRC_DWORD0,
348   TI_SCRATCH_RSRC_DWORD1,
349   TI_SCRATCH_RSRC_DWORD2,
350   TI_SCRATCH_RSRC_DWORD3
351 };
352 }
353 
354 /// OpenCL uses address spaces to differentiate between
355 /// various memory regions on the hardware. On the CPU
356 /// all of the address spaces point to the same memory,
357 /// however on the GPU, each address space points to
358 /// a separate piece of memory that is unique from other
359 /// memory locations.
360 namespace AMDGPUAS {
361   enum : unsigned {
362     // The maximum value for flat, generic, local, private, constant and region.
363     MAX_AMDGPU_ADDRESS = 7,
364 
365     FLAT_ADDRESS = 0,     ///< Address space for flat memory.
366     GLOBAL_ADDRESS = 1,   ///< Address space for global memory (RAT0, VTX0).
367     REGION_ADDRESS = 2,   ///< Address space for region memory. (GDS)
368 
369     CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
370     LOCAL_ADDRESS = 3,    ///< Address space for local memory.
371     PRIVATE_ADDRESS = 5,  ///< Address space for private memory.
372 
373     CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
374 
375     BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
376 
377     /// Address space for direct addressible parameter memory (CONST0).
378     PARAM_D_ADDRESS = 6,
379     /// Address space for indirect addressible parameter memory (VTX1).
380     PARAM_I_ADDRESS = 7,
381 
382     // Do not re-order the CONSTANT_BUFFER_* enums.  Several places depend on
383     // this order to be able to dynamically index a constant buffer, for
384     // example:
385     //
386     // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
387 
388     CONSTANT_BUFFER_0 = 8,
389     CONSTANT_BUFFER_1 = 9,
390     CONSTANT_BUFFER_2 = 10,
391     CONSTANT_BUFFER_3 = 11,
392     CONSTANT_BUFFER_4 = 12,
393     CONSTANT_BUFFER_5 = 13,
394     CONSTANT_BUFFER_6 = 14,
395     CONSTANT_BUFFER_7 = 15,
396     CONSTANT_BUFFER_8 = 16,
397     CONSTANT_BUFFER_9 = 17,
398     CONSTANT_BUFFER_10 = 18,
399     CONSTANT_BUFFER_11 = 19,
400     CONSTANT_BUFFER_12 = 20,
401     CONSTANT_BUFFER_13 = 21,
402     CONSTANT_BUFFER_14 = 22,
403     CONSTANT_BUFFER_15 = 23,
404 
405     // Some places use this if the address space can't be determined.
406     UNKNOWN_ADDRESS_SPACE = ~0u,
407   };
408 }
409 
410 namespace AMDGPU {
411 
412 // FIXME: Missing constant_32bit
413 inline bool isFlatGlobalAddrSpace(unsigned AS) {
414   return AS == AMDGPUAS::GLOBAL_ADDRESS ||
415          AS == AMDGPUAS::FLAT_ADDRESS ||
416          AS == AMDGPUAS::CONSTANT_ADDRESS ||
417          AS > AMDGPUAS::MAX_AMDGPU_ADDRESS;
418 }
419 }
420 
421 } // End namespace llvm
422 
423 #endif
424