1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 13 14 #include "llvm/Target/TargetMachine.h" 15 16 namespace llvm { 17 18 class AMDGPUTargetMachine; 19 class FunctionPass; 20 class GCNTargetMachine; 21 class ModulePass; 22 class Pass; 23 class Target; 24 class TargetMachine; 25 class TargetOptions; 26 class PassRegistry; 27 class Module; 28 29 // R600 Passes 30 FunctionPass *createR600VectorRegMerger(); 31 FunctionPass *createR600ExpandSpecialInstrsPass(); 32 FunctionPass *createR600EmitClauseMarkers(); 33 FunctionPass *createR600ClauseMergePass(); 34 FunctionPass *createR600Packetizer(); 35 FunctionPass *createR600ControlFlowFinalizer(); 36 FunctionPass *createAMDGPUCFGStructurizerPass(); 37 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel); 38 39 // SI Passes 40 FunctionPass *createSIAnnotateControlFlowPass(); 41 FunctionPass *createSIFoldOperandsPass(); 42 FunctionPass *createSIPeepholeSDWAPass(); 43 FunctionPass *createSILowerI1CopiesPass(); 44 FunctionPass *createSIShrinkInstructionsPass(); 45 FunctionPass *createSILoadStoreOptimizerPass(); 46 FunctionPass *createSIWholeQuadModePass(); 47 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 48 FunctionPass *createSIOptimizeExecMaskingPreRAPass(); 49 FunctionPass *createSIFixSGPRCopiesPass(); 50 FunctionPass *createSIMemoryLegalizerPass(); 51 FunctionPass *createSIDebuggerInsertNopsPass(); 52 FunctionPass *createSIInsertWaitcntsPass(); 53 FunctionPass *createSIFixWWMLivenessPass(); 54 FunctionPass *createSIFormMemoryClausesPass(); 55 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &); 56 FunctionPass *createAMDGPUUseNativeCallsPass(); 57 FunctionPass *createAMDGPUCodeGenPreparePass(); 58 FunctionPass *createAMDGPUMachineCFGStructurizerPass(); 59 FunctionPass *createAMDGPURewriteOutArgumentsPass(); 60 61 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&); 62 63 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&); 64 extern char &AMDGPUMachineCFGStructurizerID; 65 66 void initializeAMDGPUAlwaysInlinePass(PassRegistry&); 67 68 Pass *createAMDGPUAnnotateKernelFeaturesPass(); 69 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 70 extern char &AMDGPUAnnotateKernelFeaturesID; 71 72 FunctionPass *createAMDGPUAtomicOptimizerPass(); 73 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &); 74 extern char &AMDGPUAtomicOptimizerID; 75 76 ModulePass *createAMDGPULowerIntrinsicsPass(); 77 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &); 78 extern char &AMDGPULowerIntrinsicsID; 79 80 ModulePass *createAMDGPUFixFunctionBitcastsPass(); 81 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &); 82 extern char &AMDGPUFixFunctionBitcastsID; 83 84 FunctionPass *createAMDGPULowerKernelArgumentsPass(); 85 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &); 86 extern char &AMDGPULowerKernelArgumentsID; 87 88 ModulePass *createAMDGPULowerKernelAttributesPass(); 89 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &); 90 extern char &AMDGPULowerKernelAttributesID; 91 92 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &); 93 extern char &AMDGPURewriteOutArgumentsID; 94 95 void initializeR600ClauseMergePassPass(PassRegistry &); 96 extern char &R600ClauseMergePassID; 97 98 void initializeR600ControlFlowFinalizerPass(PassRegistry &); 99 extern char &R600ControlFlowFinalizerID; 100 101 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &); 102 extern char &R600ExpandSpecialInstrsPassID; 103 104 void initializeR600VectorRegMergerPass(PassRegistry &); 105 extern char &R600VectorRegMergerID; 106 107 void initializeR600PacketizerPass(PassRegistry &); 108 extern char &R600PacketizerID; 109 110 void initializeSIFoldOperandsPass(PassRegistry &); 111 extern char &SIFoldOperandsID; 112 113 void initializeSIPeepholeSDWAPass(PassRegistry &); 114 extern char &SIPeepholeSDWAID; 115 116 void initializeSIShrinkInstructionsPass(PassRegistry&); 117 extern char &SIShrinkInstructionsID; 118 119 void initializeSIFixSGPRCopiesPass(PassRegistry &); 120 extern char &SIFixSGPRCopiesID; 121 122 void initializeSIFixVGPRCopiesPass(PassRegistry &); 123 extern char &SIFixVGPRCopiesID; 124 125 void initializeSILowerI1CopiesPass(PassRegistry &); 126 extern char &SILowerI1CopiesID; 127 128 void initializeSILoadStoreOptimizerPass(PassRegistry &); 129 extern char &SILoadStoreOptimizerID; 130 131 void initializeSIWholeQuadModePass(PassRegistry &); 132 extern char &SIWholeQuadModeID; 133 134 void initializeSILowerControlFlowPass(PassRegistry &); 135 extern char &SILowerControlFlowID; 136 137 void initializeSIInsertSkipsPass(PassRegistry &); 138 extern char &SIInsertSkipsPassID; 139 140 void initializeSIOptimizeExecMaskingPass(PassRegistry &); 141 extern char &SIOptimizeExecMaskingID; 142 143 void initializeSIFixWWMLivenessPass(PassRegistry &); 144 extern char &SIFixWWMLivenessID; 145 146 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &); 147 extern char &AMDGPUSimplifyLibCallsID; 148 149 void initializeAMDGPUUseNativeCallsPass(PassRegistry &); 150 extern char &AMDGPUUseNativeCallsID; 151 152 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &); 153 extern char &AMDGPUPerfHintAnalysisID; 154 155 // Passes common to R600 and SI 156 FunctionPass *createAMDGPUPromoteAlloca(); 157 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 158 extern char &AMDGPUPromoteAllocaID; 159 160 Pass *createAMDGPUStructurizeCFGPass(); 161 FunctionPass *createAMDGPUISelDag( 162 TargetMachine *TM = nullptr, 163 CodeGenOpt::Level OptLevel = CodeGenOpt::Default); 164 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true); 165 ModulePass *createR600OpenCLImageTypeLoweringPass(); 166 FunctionPass *createAMDGPUAnnotateUniformValues(); 167 168 ModulePass* createAMDGPUUnifyMetadataPass(); 169 void initializeAMDGPUUnifyMetadataPass(PassRegistry&); 170 extern char &AMDGPUUnifyMetadataID; 171 172 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&); 173 extern char &SIOptimizeExecMaskingPreRAID; 174 175 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 176 extern char &AMDGPUAnnotateUniformValuesPassID; 177 178 void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 179 extern char &AMDGPUCodeGenPrepareID; 180 181 void initializeSIAnnotateControlFlowPass(PassRegistry&); 182 extern char &SIAnnotateControlFlowPassID; 183 184 void initializeSIMemoryLegalizerPass(PassRegistry&); 185 extern char &SIMemoryLegalizerID; 186 187 void initializeSIDebuggerInsertNopsPass(PassRegistry&); 188 extern char &SIDebuggerInsertNopsID; 189 190 void initializeSIInsertWaitcntsPass(PassRegistry&); 191 extern char &SIInsertWaitcntsID; 192 193 void initializeSIFormMemoryClausesPass(PassRegistry&); 194 extern char &SIFormMemoryClausesID; 195 196 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&); 197 extern char &AMDGPUUnifyDivergentExitNodesID; 198 199 ImmutablePass *createAMDGPUAAWrapperPass(); 200 void initializeAMDGPUAAWrapperPassPass(PassRegistry&); 201 202 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &); 203 204 Pass *createAMDGPUFunctionInliningPass(); 205 void initializeAMDGPUInlinerPass(PassRegistry&); 206 207 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass(); 208 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &); 209 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID; 210 211 Target &getTheAMDGPUTarget(); 212 Target &getTheGCNTarget(); 213 214 namespace AMDGPU { 215 enum TargetIndex { 216 TI_CONSTDATA_START, 217 TI_SCRATCH_RSRC_DWORD0, 218 TI_SCRATCH_RSRC_DWORD1, 219 TI_SCRATCH_RSRC_DWORD2, 220 TI_SCRATCH_RSRC_DWORD3 221 }; 222 } 223 224 } // End namespace llvm 225 226 /// OpenCL uses address spaces to differentiate between 227 /// various memory regions on the hardware. On the CPU 228 /// all of the address spaces point to the same memory, 229 /// however on the GPU, each address space points to 230 /// a separate piece of memory that is unique from other 231 /// memory locations. 232 namespace AMDGPUAS { 233 enum : unsigned { 234 // The maximum value for flat, generic, local, private, constant and region. 235 MAX_AMDGPU_ADDRESS = 6, 236 237 FLAT_ADDRESS = 0, ///< Address space for flat memory. 238 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 239 REGION_ADDRESS = 2, ///< Address space for region memory. 240 241 CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2) 242 LOCAL_ADDRESS = 3, ///< Address space for local memory. 243 PRIVATE_ADDRESS = 5, ///< Address space for private memory. 244 245 CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory 246 247 /// Address space for direct addressible parameter memory (CONST0) 248 PARAM_D_ADDRESS = 6, 249 /// Address space for indirect addressible parameter memory (VTX1) 250 PARAM_I_ADDRESS = 7, 251 252 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on 253 // this order to be able to dynamically index a constant buffer, for 254 // example: 255 // 256 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 257 258 CONSTANT_BUFFER_0 = 8, 259 CONSTANT_BUFFER_1 = 9, 260 CONSTANT_BUFFER_2 = 10, 261 CONSTANT_BUFFER_3 = 11, 262 CONSTANT_BUFFER_4 = 12, 263 CONSTANT_BUFFER_5 = 13, 264 CONSTANT_BUFFER_6 = 14, 265 CONSTANT_BUFFER_7 = 15, 266 CONSTANT_BUFFER_8 = 16, 267 CONSTANT_BUFFER_9 = 17, 268 CONSTANT_BUFFER_10 = 18, 269 CONSTANT_BUFFER_11 = 19, 270 CONSTANT_BUFFER_12 = 20, 271 CONSTANT_BUFFER_13 = 21, 272 CONSTANT_BUFFER_14 = 22, 273 CONSTANT_BUFFER_15 = 23, 274 275 // Some places use this if the address space can't be determined. 276 UNKNOWN_ADDRESS_SPACE = ~0u, 277 }; 278 } 279 280 #endif 281