1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 /// \file 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12 13 #include "llvm/IR/IntrinsicsR600.h" // TODO: Sink this. 14 #include "llvm/IR/IntrinsicsAMDGPU.h" // TODO: Sink this. 15 #include "llvm/Support/CodeGen.h" 16 17 namespace llvm { 18 19 class AMDGPUTargetMachine; 20 class FunctionPass; 21 class GCNTargetMachine; 22 class ImmutablePass; 23 class ModulePass; 24 class Pass; 25 class Target; 26 class TargetMachine; 27 class TargetOptions; 28 class PassRegistry; 29 class Module; 30 31 // GlobalISel passes 32 void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &); 33 FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone); 34 void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &); 35 FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone); 36 37 // R600 Passes 38 FunctionPass *createR600VectorRegMerger(); 39 FunctionPass *createR600ExpandSpecialInstrsPass(); 40 FunctionPass *createR600EmitClauseMarkers(); 41 FunctionPass *createR600ClauseMergePass(); 42 FunctionPass *createR600Packetizer(); 43 FunctionPass *createR600ControlFlowFinalizer(); 44 FunctionPass *createAMDGPUCFGStructurizerPass(); 45 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel); 46 47 // SI Passes 48 FunctionPass *createGCNDPPCombinePass(); 49 FunctionPass *createSIAnnotateControlFlowPass(); 50 FunctionPass *createSIFoldOperandsPass(); 51 FunctionPass *createSIPeepholeSDWAPass(); 52 FunctionPass *createSILowerI1CopiesPass(); 53 FunctionPass *createSIFixupVectorISelPass(); 54 FunctionPass *createSIAddIMGInitPass(); 55 FunctionPass *createSIShrinkInstructionsPass(); 56 FunctionPass *createSILoadStoreOptimizerPass(); 57 FunctionPass *createSIWholeQuadModePass(); 58 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 59 FunctionPass *createSIOptimizeExecMaskingPreRAPass(); 60 FunctionPass *createSIFixSGPRCopiesPass(); 61 FunctionPass *createSIMemoryLegalizerPass(); 62 FunctionPass *createSIInsertWaitcntsPass(); 63 FunctionPass *createSIPreAllocateWWMRegsPass(); 64 FunctionPass *createSIFormMemoryClausesPass(); 65 66 FunctionPass *createSIPostRABundlerPass(); 67 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetMachine *); 68 FunctionPass *createAMDGPUUseNativeCallsPass(); 69 FunctionPass *createAMDGPUCodeGenPreparePass(); 70 FunctionPass *createAMDGPUMachineCFGStructurizerPass(); 71 FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *); 72 ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *); 73 FunctionPass *createAMDGPURewriteOutArgumentsPass(); 74 FunctionPass *createSIModeRegisterPass(); 75 76 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&); 77 78 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&); 79 extern char &AMDGPUMachineCFGStructurizerID; 80 81 void initializeAMDGPUAlwaysInlinePass(PassRegistry&); 82 83 Pass *createAMDGPUAnnotateKernelFeaturesPass(); 84 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 85 extern char &AMDGPUAnnotateKernelFeaturesID; 86 87 FunctionPass *createAMDGPUAtomicOptimizerPass(); 88 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &); 89 extern char &AMDGPUAtomicOptimizerID; 90 91 ModulePass *createAMDGPULowerIntrinsicsPass(); 92 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &); 93 extern char &AMDGPULowerIntrinsicsID; 94 95 ModulePass *createAMDGPUFixFunctionBitcastsPass(); 96 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &); 97 extern char &AMDGPUFixFunctionBitcastsID; 98 99 FunctionPass *createAMDGPULowerKernelArgumentsPass(); 100 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &); 101 extern char &AMDGPULowerKernelArgumentsID; 102 103 ModulePass *createAMDGPULowerKernelAttributesPass(); 104 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &); 105 extern char &AMDGPULowerKernelAttributesID; 106 107 void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &); 108 extern char &AMDGPUPropagateAttributesEarlyID; 109 110 void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &); 111 extern char &AMDGPUPropagateAttributesLateID; 112 113 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &); 114 extern char &AMDGPURewriteOutArgumentsID; 115 116 void initializeGCNDPPCombinePass(PassRegistry &); 117 extern char &GCNDPPCombineID; 118 119 void initializeR600ClauseMergePassPass(PassRegistry &); 120 extern char &R600ClauseMergePassID; 121 122 void initializeR600ControlFlowFinalizerPass(PassRegistry &); 123 extern char &R600ControlFlowFinalizerID; 124 125 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &); 126 extern char &R600ExpandSpecialInstrsPassID; 127 128 void initializeR600VectorRegMergerPass(PassRegistry &); 129 extern char &R600VectorRegMergerID; 130 131 void initializeR600PacketizerPass(PassRegistry &); 132 extern char &R600PacketizerID; 133 134 void initializeSIFoldOperandsPass(PassRegistry &); 135 extern char &SIFoldOperandsID; 136 137 void initializeSIPeepholeSDWAPass(PassRegistry &); 138 extern char &SIPeepholeSDWAID; 139 140 void initializeSIShrinkInstructionsPass(PassRegistry&); 141 extern char &SIShrinkInstructionsID; 142 143 void initializeSIFixSGPRCopiesPass(PassRegistry &); 144 extern char &SIFixSGPRCopiesID; 145 146 void initializeSIFixVGPRCopiesPass(PassRegistry &); 147 extern char &SIFixVGPRCopiesID; 148 149 void initializeSIFixupVectorISelPass(PassRegistry &); 150 extern char &SIFixupVectorISelID; 151 152 void initializeSILowerI1CopiesPass(PassRegistry &); 153 extern char &SILowerI1CopiesID; 154 155 void initializeSILowerSGPRSpillsPass(PassRegistry &); 156 extern char &SILowerSGPRSpillsID; 157 158 void initializeSILoadStoreOptimizerPass(PassRegistry &); 159 extern char &SILoadStoreOptimizerID; 160 161 void initializeSIWholeQuadModePass(PassRegistry &); 162 extern char &SIWholeQuadModeID; 163 164 void initializeSILowerControlFlowPass(PassRegistry &); 165 extern char &SILowerControlFlowID; 166 167 void initializeSIRemoveShortExecBranchesPass(PassRegistry &); 168 extern char &SIRemoveShortExecBranchesID; 169 170 void initializeSIPreEmitPeepholePass(PassRegistry &); 171 extern char &SIPreEmitPeepholeID; 172 173 void initializeSIInsertSkipsPass(PassRegistry &); 174 extern char &SIInsertSkipsPassID; 175 176 void initializeSIOptimizeExecMaskingPass(PassRegistry &); 177 extern char &SIOptimizeExecMaskingID; 178 179 void initializeSIPreAllocateWWMRegsPass(PassRegistry &); 180 extern char &SIPreAllocateWWMRegsID; 181 182 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &); 183 extern char &AMDGPUSimplifyLibCallsID; 184 185 void initializeAMDGPUUseNativeCallsPass(PassRegistry &); 186 extern char &AMDGPUUseNativeCallsID; 187 188 void initializeSIAddIMGInitPass(PassRegistry &); 189 extern char &SIAddIMGInitID; 190 191 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &); 192 extern char &AMDGPUPerfHintAnalysisID; 193 194 // Passes common to R600 and SI 195 FunctionPass *createAMDGPUPromoteAlloca(); 196 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 197 extern char &AMDGPUPromoteAllocaID; 198 199 FunctionPass *createAMDGPUPromoteAllocaToVector(); 200 void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry&); 201 extern char &AMDGPUPromoteAllocaToVectorID; 202 203 Pass *createAMDGPUStructurizeCFGPass(); 204 FunctionPass *createAMDGPUISelDag( 205 TargetMachine *TM = nullptr, 206 CodeGenOpt::Level OptLevel = CodeGenOpt::Default); 207 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true); 208 ModulePass *createR600OpenCLImageTypeLoweringPass(); 209 FunctionPass *createAMDGPUAnnotateUniformValues(); 210 211 ModulePass *createAMDGPUPrintfRuntimeBinding(); 212 void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&); 213 extern char &AMDGPUPrintfRuntimeBindingID; 214 215 ModulePass* createAMDGPUUnifyMetadataPass(); 216 void initializeAMDGPUUnifyMetadataPass(PassRegistry&); 217 extern char &AMDGPUUnifyMetadataID; 218 219 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&); 220 extern char &SIOptimizeExecMaskingPreRAID; 221 222 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 223 extern char &AMDGPUAnnotateUniformValuesPassID; 224 225 void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 226 extern char &AMDGPUCodeGenPrepareID; 227 228 void initializeSIAnnotateControlFlowPass(PassRegistry&); 229 extern char &SIAnnotateControlFlowPassID; 230 231 void initializeSIMemoryLegalizerPass(PassRegistry&); 232 extern char &SIMemoryLegalizerID; 233 234 void initializeSIModeRegisterPass(PassRegistry&); 235 extern char &SIModeRegisterID; 236 237 void initializeSIInsertHardClausesPass(PassRegistry &); 238 extern char &SIInsertHardClausesID; 239 240 void initializeSIInsertWaitcntsPass(PassRegistry&); 241 extern char &SIInsertWaitcntsID; 242 243 void initializeSIFormMemoryClausesPass(PassRegistry&); 244 extern char &SIFormMemoryClausesID; 245 246 void initializeSIPostRABundlerPass(PassRegistry&); 247 extern char &SIPostRABundlerID; 248 249 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&); 250 extern char &AMDGPUUnifyDivergentExitNodesID; 251 252 ImmutablePass *createAMDGPUAAWrapperPass(); 253 void initializeAMDGPUAAWrapperPassPass(PassRegistry&); 254 ImmutablePass *createAMDGPUExternalAAWrapperPass(); 255 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&); 256 257 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &); 258 259 Pass *createAMDGPUFunctionInliningPass(); 260 void initializeAMDGPUInlinerPass(PassRegistry&); 261 262 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass(); 263 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &); 264 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID; 265 266 void initializeGCNRegBankReassignPass(PassRegistry &); 267 extern char &GCNRegBankReassignID; 268 269 void initializeGCNNSAReassignPass(PassRegistry &); 270 extern char &GCNNSAReassignID; 271 272 namespace AMDGPU { 273 enum TargetIndex { 274 TI_CONSTDATA_START, 275 TI_SCRATCH_RSRC_DWORD0, 276 TI_SCRATCH_RSRC_DWORD1, 277 TI_SCRATCH_RSRC_DWORD2, 278 TI_SCRATCH_RSRC_DWORD3 279 }; 280 } 281 282 } // End namespace llvm 283 284 /// OpenCL uses address spaces to differentiate between 285 /// various memory regions on the hardware. On the CPU 286 /// all of the address spaces point to the same memory, 287 /// however on the GPU, each address space points to 288 /// a separate piece of memory that is unique from other 289 /// memory locations. 290 namespace AMDGPUAS { 291 enum : unsigned { 292 // The maximum value for flat, generic, local, private, constant and region. 293 MAX_AMDGPU_ADDRESS = 7, 294 295 FLAT_ADDRESS = 0, ///< Address space for flat memory. 296 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 297 REGION_ADDRESS = 2, ///< Address space for region memory. (GDS) 298 299 CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2). 300 LOCAL_ADDRESS = 3, ///< Address space for local memory. 301 PRIVATE_ADDRESS = 5, ///< Address space for private memory. 302 303 CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory. 304 305 BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers. 306 307 /// Address space for direct addressible parameter memory (CONST0). 308 PARAM_D_ADDRESS = 6, 309 /// Address space for indirect addressible parameter memory (VTX1). 310 PARAM_I_ADDRESS = 7, 311 312 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on 313 // this order to be able to dynamically index a constant buffer, for 314 // example: 315 // 316 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 317 318 CONSTANT_BUFFER_0 = 8, 319 CONSTANT_BUFFER_1 = 9, 320 CONSTANT_BUFFER_2 = 10, 321 CONSTANT_BUFFER_3 = 11, 322 CONSTANT_BUFFER_4 = 12, 323 CONSTANT_BUFFER_5 = 13, 324 CONSTANT_BUFFER_6 = 14, 325 CONSTANT_BUFFER_7 = 15, 326 CONSTANT_BUFFER_8 = 16, 327 CONSTANT_BUFFER_9 = 17, 328 CONSTANT_BUFFER_10 = 18, 329 CONSTANT_BUFFER_11 = 19, 330 CONSTANT_BUFFER_12 = 20, 331 CONSTANT_BUFFER_13 = 21, 332 CONSTANT_BUFFER_14 = 22, 333 CONSTANT_BUFFER_15 = 23, 334 335 // Some places use this if the address space can't be determined. 336 UNKNOWN_ADDRESS_SPACE = ~0u, 337 }; 338 } 339 340 #endif 341