1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 13 14 #include "llvm/Target/TargetMachine.h" 15 16 namespace llvm { 17 18 class AMDGPUTargetMachine; 19 class FunctionPass; 20 class GCNTargetMachine; 21 class ModulePass; 22 class Pass; 23 class Target; 24 class TargetMachine; 25 class PassRegistry; 26 27 // R600 Passes 28 FunctionPass *createR600VectorRegMerger(TargetMachine &tm); 29 FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm); 30 FunctionPass *createR600EmitClauseMarkers(); 31 FunctionPass *createR600ClauseMergePass(TargetMachine &tm); 32 FunctionPass *createR600Packetizer(TargetMachine &tm); 33 FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm); 34 FunctionPass *createAMDGPUCFGStructurizerPass(); 35 36 // SI Passes 37 FunctionPass *createSITypeRewriter(); 38 FunctionPass *createSIAnnotateControlFlowPass(); 39 FunctionPass *createSIFoldOperandsPass(); 40 FunctionPass *createSILowerI1CopiesPass(); 41 FunctionPass *createSIShrinkInstructionsPass(); 42 FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm); 43 FunctionPass *createSIWholeQuadModePass(); 44 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 45 FunctionPass *createSIFixSGPRCopiesPass(); 46 FunctionPass *createSIDebuggerInsertNopsPass(); 47 FunctionPass *createSIInsertWaitsPass(); 48 FunctionPass *createAMDGPUCodeGenPreparePass(const GCNTargetMachine *TM = nullptr); 49 50 ModulePass *createAMDGPUAnnotateKernelFeaturesPass(const TargetMachine *TM = nullptr); 51 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 52 extern char &AMDGPUAnnotateKernelFeaturesID; 53 54 ModulePass *createAMDGPULowerIntrinsicsPass(); 55 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &); 56 extern char &AMDGPULowerIntrinsicsID; 57 58 void initializeSIFoldOperandsPass(PassRegistry &); 59 extern char &SIFoldOperandsID; 60 61 void initializeSIShrinkInstructionsPass(PassRegistry&); 62 extern char &SIShrinkInstructionsID; 63 64 void initializeSIFixSGPRCopiesPass(PassRegistry &); 65 extern char &SIFixSGPRCopiesID; 66 67 void initializeSIFixVGPRCopiesPass(PassRegistry &); 68 extern char &SIFixVGPRCopiesID; 69 70 void initializeSILowerI1CopiesPass(PassRegistry &); 71 extern char &SILowerI1CopiesID; 72 73 void initializeSILoadStoreOptimizerPass(PassRegistry &); 74 extern char &SILoadStoreOptimizerID; 75 76 void initializeSIWholeQuadModePass(PassRegistry &); 77 extern char &SIWholeQuadModeID; 78 79 void initializeSILowerControlFlowPass(PassRegistry &); 80 extern char &SILowerControlFlowID; 81 82 void initializeSIInsertSkipsPass(PassRegistry &); 83 extern char &SIInsertSkipsPassID; 84 85 void initializeSIOptimizeExecMaskingPass(PassRegistry &); 86 extern char &SIOptimizeExecMaskingID; 87 88 // Passes common to R600 and SI 89 FunctionPass *createAMDGPUPromoteAlloca(const TargetMachine *TM = nullptr); 90 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 91 extern char &AMDGPUPromoteAllocaID; 92 93 Pass *createAMDGPUStructurizeCFGPass(); 94 FunctionPass *createAMDGPUISelDag(TargetMachine &TM, 95 CodeGenOpt::Level OptLevel); 96 ModulePass *createAMDGPUAlwaysInlinePass(); 97 ModulePass *createAMDGPUOpenCLImageTypeLoweringPass(); 98 FunctionPass *createAMDGPUAnnotateUniformValues(); 99 100 ModulePass* createAMDGPUUnifyMetadataPass(); 101 void initializeAMDGPUUnifyMetadataPass(PassRegistry&); 102 extern char &AMDGPUUnifyMetadataID; 103 104 void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&); 105 extern char &SIFixControlFlowLiveIntervalsID; 106 107 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 108 extern char &AMDGPUAnnotateUniformValuesPassID; 109 110 void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 111 extern char &AMDGPUCodeGenPrepareID; 112 113 void initializeSIAnnotateControlFlowPass(PassRegistry&); 114 extern char &SIAnnotateControlFlowPassID; 115 116 void initializeSIDebuggerInsertNopsPass(PassRegistry&); 117 extern char &SIDebuggerInsertNopsID; 118 119 void initializeSIInsertWaitsPass(PassRegistry&); 120 extern char &SIInsertWaitsID; 121 122 Target &getTheAMDGPUTarget(); 123 Target &getTheGCNTarget(); 124 125 namespace AMDGPU { 126 enum TargetIndex { 127 TI_CONSTDATA_START, 128 TI_SCRATCH_RSRC_DWORD0, 129 TI_SCRATCH_RSRC_DWORD1, 130 TI_SCRATCH_RSRC_DWORD2, 131 TI_SCRATCH_RSRC_DWORD3 132 }; 133 } 134 135 } // End namespace llvm 136 137 /// OpenCL uses address spaces to differentiate between 138 /// various memory regions on the hardware. On the CPU 139 /// all of the address spaces point to the same memory, 140 /// however on the GPU, each address space points to 141 /// a separate piece of memory that is unique from other 142 /// memory locations. 143 namespace AMDGPUAS { 144 enum AddressSpaces : unsigned { 145 PRIVATE_ADDRESS = 0, ///< Address space for private memory. 146 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 147 CONSTANT_ADDRESS = 2, ///< Address space for constant memory (VTX2) 148 LOCAL_ADDRESS = 3, ///< Address space for local memory. 149 FLAT_ADDRESS = 4, ///< Address space for flat memory. 150 REGION_ADDRESS = 5, ///< Address space for region memory. 151 PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0) 152 PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1) 153 154 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this 155 // order to be able to dynamically index a constant buffer, for example: 156 // 157 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 158 159 CONSTANT_BUFFER_0 = 8, 160 CONSTANT_BUFFER_1 = 9, 161 CONSTANT_BUFFER_2 = 10, 162 CONSTANT_BUFFER_3 = 11, 163 CONSTANT_BUFFER_4 = 12, 164 CONSTANT_BUFFER_5 = 13, 165 CONSTANT_BUFFER_6 = 14, 166 CONSTANT_BUFFER_7 = 15, 167 CONSTANT_BUFFER_8 = 16, 168 CONSTANT_BUFFER_9 = 17, 169 CONSTANT_BUFFER_10 = 18, 170 CONSTANT_BUFFER_11 = 19, 171 CONSTANT_BUFFER_12 = 20, 172 CONSTANT_BUFFER_13 = 21, 173 CONSTANT_BUFFER_14 = 22, 174 CONSTANT_BUFFER_15 = 23, 175 176 // Some places use this if the address space can't be determined. 177 UNKNOWN_ADDRESS_SPACE = ~0u 178 }; 179 180 } // namespace AMDGPUAS 181 182 #endif 183