1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 /// \file 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12 13 #include "llvm/IR/PassManager.h" 14 #include "llvm/Support/CodeGen.h" 15 16 namespace llvm { 17 18 class TargetMachine; 19 20 // GlobalISel passes 21 void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &); 22 FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone); 23 void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &); 24 FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone); 25 FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone); 26 void initializeAMDGPURegBankCombinerPass(PassRegistry &); 27 28 // SI Passes 29 FunctionPass *createGCNDPPCombinePass(); 30 FunctionPass *createSIAnnotateControlFlowPass(); 31 FunctionPass *createSIFoldOperandsPass(); 32 FunctionPass *createSIPeepholeSDWAPass(); 33 FunctionPass *createSILowerI1CopiesPass(); 34 FunctionPass *createSIShrinkInstructionsPass(); 35 FunctionPass *createSILoadStoreOptimizerPass(); 36 FunctionPass *createSIWholeQuadModePass(); 37 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 38 FunctionPass *createSIOptimizeExecMaskingPreRAPass(); 39 FunctionPass *createSIOptimizeVGPRLiveRangePass(); 40 FunctionPass *createSIFixSGPRCopiesPass(); 41 FunctionPass *createSIMemoryLegalizerPass(); 42 FunctionPass *createSIInsertWaitcntsPass(); 43 FunctionPass *createSIPreAllocateWWMRegsPass(); 44 FunctionPass *createSIFormMemoryClausesPass(); 45 46 FunctionPass *createSIPostRABundlerPass(); 47 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetMachine *); 48 FunctionPass *createAMDGPUUseNativeCallsPass(); 49 FunctionPass *createAMDGPUCodeGenPreparePass(); 50 FunctionPass *createAMDGPULateCodeGenPreparePass(); 51 FunctionPass *createAMDGPUMachineCFGStructurizerPass(); 52 FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *); 53 ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *); 54 FunctionPass *createAMDGPURewriteOutArgumentsPass(); 55 ModulePass *createAMDGPUReplaceLDSUseWithPointerPass(); 56 ModulePass *createAMDGPULowerModuleLDSPass(); 57 FunctionPass *createSIModeRegisterPass(); 58 FunctionPass *createGCNPreRAOptimizationsPass(); 59 60 struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> { 61 AMDGPUSimplifyLibCallsPass(TargetMachine &TM) : TM(TM) {} 62 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); 63 64 private: 65 TargetMachine &TM; 66 }; 67 68 struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> { 69 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); 70 }; 71 72 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&); 73 74 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&); 75 extern char &AMDGPUMachineCFGStructurizerID; 76 77 void initializeAMDGPUAlwaysInlinePass(PassRegistry&); 78 79 Pass *createAMDGPUAnnotateKernelFeaturesPass(); 80 Pass *createAMDGPUAttributorPass(); 81 void initializeAMDGPUAttributorPass(PassRegistry &); 82 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 83 extern char &AMDGPUAnnotateKernelFeaturesID; 84 85 FunctionPass *createAMDGPUAtomicOptimizerPass(); 86 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &); 87 extern char &AMDGPUAtomicOptimizerID; 88 89 ModulePass *createAMDGPULowerIntrinsicsPass(); 90 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &); 91 extern char &AMDGPULowerIntrinsicsID; 92 93 ModulePass *createAMDGPUFixFunctionBitcastsPass(); 94 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &); 95 extern char &AMDGPUFixFunctionBitcastsID; 96 97 ModulePass *createAMDGPUCtorDtorLoweringPass(); 98 void initializeAMDGPUCtorDtorLoweringPass(PassRegistry &); 99 extern char &AMDGPUCtorDtorLoweringID; 100 101 FunctionPass *createAMDGPULowerKernelArgumentsPass(); 102 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &); 103 extern char &AMDGPULowerKernelArgumentsID; 104 105 ModulePass *createAMDGPULowerKernelAttributesPass(); 106 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &); 107 extern char &AMDGPULowerKernelAttributesID; 108 109 struct AMDGPULowerKernelAttributesPass 110 : PassInfoMixin<AMDGPULowerKernelAttributesPass> { 111 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); 112 }; 113 114 void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &); 115 extern char &AMDGPUPropagateAttributesEarlyID; 116 117 struct AMDGPUPropagateAttributesEarlyPass 118 : PassInfoMixin<AMDGPUPropagateAttributesEarlyPass> { 119 AMDGPUPropagateAttributesEarlyPass(TargetMachine &TM) : TM(TM) {} 120 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); 121 122 private: 123 TargetMachine &TM; 124 }; 125 126 void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &); 127 extern char &AMDGPUPropagateAttributesLateID; 128 129 struct AMDGPUPropagateAttributesLatePass 130 : PassInfoMixin<AMDGPUPropagateAttributesLatePass> { 131 AMDGPUPropagateAttributesLatePass(TargetMachine &TM) : TM(TM) {} 132 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); 133 134 private: 135 TargetMachine &TM; 136 }; 137 138 void initializeAMDGPUReplaceLDSUseWithPointerPass(PassRegistry &); 139 extern char &AMDGPUReplaceLDSUseWithPointerID; 140 141 struct AMDGPUReplaceLDSUseWithPointerPass 142 : PassInfoMixin<AMDGPUReplaceLDSUseWithPointerPass> { 143 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); 144 }; 145 146 void initializeAMDGPULowerModuleLDSPass(PassRegistry &); 147 extern char &AMDGPULowerModuleLDSID; 148 149 struct AMDGPULowerModuleLDSPass : PassInfoMixin<AMDGPULowerModuleLDSPass> { 150 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); 151 }; 152 153 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &); 154 extern char &AMDGPURewriteOutArgumentsID; 155 156 void initializeGCNDPPCombinePass(PassRegistry &); 157 extern char &GCNDPPCombineID; 158 159 void initializeSIFoldOperandsPass(PassRegistry &); 160 extern char &SIFoldOperandsID; 161 162 void initializeSIPeepholeSDWAPass(PassRegistry &); 163 extern char &SIPeepholeSDWAID; 164 165 void initializeSIShrinkInstructionsPass(PassRegistry&); 166 extern char &SIShrinkInstructionsID; 167 168 void initializeSIFixSGPRCopiesPass(PassRegistry &); 169 extern char &SIFixSGPRCopiesID; 170 171 void initializeSIFixVGPRCopiesPass(PassRegistry &); 172 extern char &SIFixVGPRCopiesID; 173 174 void initializeSILowerI1CopiesPass(PassRegistry &); 175 extern char &SILowerI1CopiesID; 176 177 void initializeSILowerSGPRSpillsPass(PassRegistry &); 178 extern char &SILowerSGPRSpillsID; 179 180 void initializeSILoadStoreOptimizerPass(PassRegistry &); 181 extern char &SILoadStoreOptimizerID; 182 183 void initializeSIWholeQuadModePass(PassRegistry &); 184 extern char &SIWholeQuadModeID; 185 186 void initializeSILowerControlFlowPass(PassRegistry &); 187 extern char &SILowerControlFlowID; 188 189 void initializeSIPreEmitPeepholePass(PassRegistry &); 190 extern char &SIPreEmitPeepholeID; 191 192 void initializeSILateBranchLoweringPass(PassRegistry &); 193 extern char &SILateBranchLoweringPassID; 194 195 void initializeSIOptimizeExecMaskingPass(PassRegistry &); 196 extern char &SIOptimizeExecMaskingID; 197 198 void initializeSIPreAllocateWWMRegsPass(PassRegistry &); 199 extern char &SIPreAllocateWWMRegsID; 200 201 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &); 202 extern char &AMDGPUSimplifyLibCallsID; 203 204 void initializeAMDGPUUseNativeCallsPass(PassRegistry &); 205 extern char &AMDGPUUseNativeCallsID; 206 207 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &); 208 extern char &AMDGPUPerfHintAnalysisID; 209 210 // Passes common to R600 and SI 211 FunctionPass *createAMDGPUPromoteAlloca(); 212 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 213 extern char &AMDGPUPromoteAllocaID; 214 215 FunctionPass *createAMDGPUPromoteAllocaToVector(); 216 void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry&); 217 extern char &AMDGPUPromoteAllocaToVectorID; 218 219 struct AMDGPUPromoteAllocaPass : PassInfoMixin<AMDGPUPromoteAllocaPass> { 220 AMDGPUPromoteAllocaPass(TargetMachine &TM) : TM(TM) {} 221 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); 222 223 private: 224 TargetMachine &TM; 225 }; 226 227 struct AMDGPUPromoteAllocaToVectorPass 228 : PassInfoMixin<AMDGPUPromoteAllocaToVectorPass> { 229 AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM) : TM(TM) {} 230 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); 231 232 private: 233 TargetMachine &TM; 234 }; 235 236 Pass *createAMDGPUStructurizeCFGPass(); 237 FunctionPass *createAMDGPUISelDag( 238 TargetMachine *TM = nullptr, 239 CodeGenOpt::Level OptLevel = CodeGenOpt::Default); 240 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true); 241 242 struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> { 243 AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {} 244 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); 245 246 private: 247 bool GlobalOpt; 248 }; 249 250 FunctionPass *createAMDGPUAnnotateUniformValues(); 251 252 ModulePass *createAMDGPUPrintfRuntimeBinding(); 253 void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&); 254 extern char &AMDGPUPrintfRuntimeBindingID; 255 256 void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &); 257 extern char &AMDGPUResourceUsageAnalysisID; 258 259 struct AMDGPUPrintfRuntimeBindingPass 260 : PassInfoMixin<AMDGPUPrintfRuntimeBindingPass> { 261 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); 262 }; 263 264 ModulePass* createAMDGPUUnifyMetadataPass(); 265 void initializeAMDGPUUnifyMetadataPass(PassRegistry&); 266 extern char &AMDGPUUnifyMetadataID; 267 268 struct AMDGPUUnifyMetadataPass : PassInfoMixin<AMDGPUUnifyMetadataPass> { 269 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); 270 }; 271 272 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&); 273 extern char &SIOptimizeExecMaskingPreRAID; 274 275 void initializeSIOptimizeVGPRLiveRangePass(PassRegistry &); 276 extern char &SIOptimizeVGPRLiveRangeID; 277 278 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 279 extern char &AMDGPUAnnotateUniformValuesPassID; 280 281 void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 282 extern char &AMDGPUCodeGenPrepareID; 283 284 void initializeAMDGPULateCodeGenPreparePass(PassRegistry &); 285 extern char &AMDGPULateCodeGenPrepareID; 286 287 void initializeSIAnnotateControlFlowPass(PassRegistry&); 288 extern char &SIAnnotateControlFlowPassID; 289 290 void initializeSIMemoryLegalizerPass(PassRegistry&); 291 extern char &SIMemoryLegalizerID; 292 293 void initializeSIModeRegisterPass(PassRegistry&); 294 extern char &SIModeRegisterID; 295 296 void initializeSIInsertHardClausesPass(PassRegistry &); 297 extern char &SIInsertHardClausesID; 298 299 void initializeSIInsertWaitcntsPass(PassRegistry&); 300 extern char &SIInsertWaitcntsID; 301 302 void initializeSIFormMemoryClausesPass(PassRegistry&); 303 extern char &SIFormMemoryClausesID; 304 305 void initializeSIPostRABundlerPass(PassRegistry&); 306 extern char &SIPostRABundlerID; 307 308 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&); 309 extern char &AMDGPUUnifyDivergentExitNodesID; 310 311 ImmutablePass *createAMDGPUAAWrapperPass(); 312 void initializeAMDGPUAAWrapperPassPass(PassRegistry&); 313 ImmutablePass *createAMDGPUExternalAAWrapperPass(); 314 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&); 315 316 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &); 317 318 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass(); 319 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &); 320 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID; 321 322 void initializeGCNNSAReassignPass(PassRegistry &); 323 extern char &GCNNSAReassignID; 324 325 void initializeGCNPreRAOptimizationsPass(PassRegistry &); 326 extern char &GCNPreRAOptimizationsID; 327 328 namespace AMDGPU { 329 enum TargetIndex { 330 TI_CONSTDATA_START, 331 TI_SCRATCH_RSRC_DWORD0, 332 TI_SCRATCH_RSRC_DWORD1, 333 TI_SCRATCH_RSRC_DWORD2, 334 TI_SCRATCH_RSRC_DWORD3 335 }; 336 } 337 338 /// OpenCL uses address spaces to differentiate between 339 /// various memory regions on the hardware. On the CPU 340 /// all of the address spaces point to the same memory, 341 /// however on the GPU, each address space points to 342 /// a separate piece of memory that is unique from other 343 /// memory locations. 344 namespace AMDGPUAS { 345 enum : unsigned { 346 // The maximum value for flat, generic, local, private, constant and region. 347 MAX_AMDGPU_ADDRESS = 7, 348 349 FLAT_ADDRESS = 0, ///< Address space for flat memory. 350 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 351 REGION_ADDRESS = 2, ///< Address space for region memory. (GDS) 352 353 CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2). 354 LOCAL_ADDRESS = 3, ///< Address space for local memory. 355 PRIVATE_ADDRESS = 5, ///< Address space for private memory. 356 357 CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory. 358 359 BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers. 360 361 /// Address space for direct addressable parameter memory (CONST0). 362 PARAM_D_ADDRESS = 6, 363 /// Address space for indirect addressable parameter memory (VTX1). 364 PARAM_I_ADDRESS = 7, 365 366 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on 367 // this order to be able to dynamically index a constant buffer, for 368 // example: 369 // 370 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 371 372 CONSTANT_BUFFER_0 = 8, 373 CONSTANT_BUFFER_1 = 9, 374 CONSTANT_BUFFER_2 = 10, 375 CONSTANT_BUFFER_3 = 11, 376 CONSTANT_BUFFER_4 = 12, 377 CONSTANT_BUFFER_5 = 13, 378 CONSTANT_BUFFER_6 = 14, 379 CONSTANT_BUFFER_7 = 15, 380 CONSTANT_BUFFER_8 = 16, 381 CONSTANT_BUFFER_9 = 17, 382 CONSTANT_BUFFER_10 = 18, 383 CONSTANT_BUFFER_11 = 19, 384 CONSTANT_BUFFER_12 = 20, 385 CONSTANT_BUFFER_13 = 21, 386 CONSTANT_BUFFER_14 = 22, 387 CONSTANT_BUFFER_15 = 23, 388 389 // Some places use this if the address space can't be determined. 390 UNKNOWN_ADDRESS_SPACE = ~0u, 391 }; 392 } 393 394 namespace AMDGPU { 395 396 // FIXME: Missing constant_32bit 397 inline bool isFlatGlobalAddrSpace(unsigned AS) { 398 return AS == AMDGPUAS::GLOBAL_ADDRESS || 399 AS == AMDGPUAS::FLAT_ADDRESS || 400 AS == AMDGPUAS::CONSTANT_ADDRESS || 401 AS > AMDGPUAS::MAX_AMDGPU_ADDRESS; 402 } 403 } 404 405 } // End namespace llvm 406 407 #endif 408