1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 /// \file 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12 13 #include "llvm/IR/IntrinsicsR600.h" // TODO: Sink this. 14 #include "llvm/IR/IntrinsicsAMDGPU.h" // TODO: Sink this. 15 #include "llvm/Support/CodeGen.h" 16 17 namespace llvm { 18 19 class AMDGPUTargetMachine; 20 class FunctionPass; 21 class GCNTargetMachine; 22 class ImmutablePass; 23 class ModulePass; 24 class Pass; 25 class Target; 26 class TargetMachine; 27 class TargetOptions; 28 class PassRegistry; 29 class Module; 30 31 // GlobalISel passes 32 void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &); 33 FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone); 34 void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &); 35 FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone); 36 FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone); 37 void initializeAMDGPURegBankCombinerPass(PassRegistry &); 38 39 // R600 Passes 40 FunctionPass *createR600VectorRegMerger(); 41 FunctionPass *createR600ExpandSpecialInstrsPass(); 42 FunctionPass *createR600EmitClauseMarkers(); 43 FunctionPass *createR600ClauseMergePass(); 44 FunctionPass *createR600Packetizer(); 45 FunctionPass *createR600ControlFlowFinalizer(); 46 FunctionPass *createAMDGPUCFGStructurizerPass(); 47 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel); 48 49 // SI Passes 50 FunctionPass *createGCNDPPCombinePass(); 51 FunctionPass *createSIAnnotateControlFlowPass(); 52 FunctionPass *createSIFoldOperandsPass(); 53 FunctionPass *createSIPeepholeSDWAPass(); 54 FunctionPass *createSILowerI1CopiesPass(); 55 FunctionPass *createSIAddIMGInitPass(); 56 FunctionPass *createSIShrinkInstructionsPass(); 57 FunctionPass *createSILoadStoreOptimizerPass(); 58 FunctionPass *createSIWholeQuadModePass(); 59 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 60 FunctionPass *createSIOptimizeExecMaskingPreRAPass(); 61 FunctionPass *createSIFixSGPRCopiesPass(); 62 FunctionPass *createSIMemoryLegalizerPass(); 63 FunctionPass *createSIInsertWaitcntsPass(); 64 FunctionPass *createSIPreAllocateWWMRegsPass(); 65 FunctionPass *createSIFormMemoryClausesPass(); 66 67 FunctionPass *createSIPostRABundlerPass(); 68 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetMachine *); 69 FunctionPass *createAMDGPUUseNativeCallsPass(); 70 FunctionPass *createAMDGPUCodeGenPreparePass(); 71 FunctionPass *createAMDGPULateCodeGenPreparePass(); 72 FunctionPass *createAMDGPUMachineCFGStructurizerPass(); 73 FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *); 74 ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *); 75 FunctionPass *createAMDGPURewriteOutArgumentsPass(); 76 FunctionPass *createSIModeRegisterPass(); 77 78 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&); 79 80 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&); 81 extern char &AMDGPUMachineCFGStructurizerID; 82 83 void initializeAMDGPUAlwaysInlinePass(PassRegistry&); 84 85 Pass *createAMDGPUAnnotateKernelFeaturesPass(); 86 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 87 extern char &AMDGPUAnnotateKernelFeaturesID; 88 89 FunctionPass *createAMDGPUAtomicOptimizerPass(); 90 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &); 91 extern char &AMDGPUAtomicOptimizerID; 92 93 ModulePass *createAMDGPULowerIntrinsicsPass(); 94 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &); 95 extern char &AMDGPULowerIntrinsicsID; 96 97 ModulePass *createAMDGPUFixFunctionBitcastsPass(); 98 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &); 99 extern char &AMDGPUFixFunctionBitcastsID; 100 101 FunctionPass *createAMDGPULowerKernelArgumentsPass(); 102 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &); 103 extern char &AMDGPULowerKernelArgumentsID; 104 105 ModulePass *createAMDGPULowerKernelAttributesPass(); 106 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &); 107 extern char &AMDGPULowerKernelAttributesID; 108 109 void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &); 110 extern char &AMDGPUPropagateAttributesEarlyID; 111 112 void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &); 113 extern char &AMDGPUPropagateAttributesLateID; 114 115 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &); 116 extern char &AMDGPURewriteOutArgumentsID; 117 118 void initializeGCNDPPCombinePass(PassRegistry &); 119 extern char &GCNDPPCombineID; 120 121 void initializeR600ClauseMergePassPass(PassRegistry &); 122 extern char &R600ClauseMergePassID; 123 124 void initializeR600ControlFlowFinalizerPass(PassRegistry &); 125 extern char &R600ControlFlowFinalizerID; 126 127 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &); 128 extern char &R600ExpandSpecialInstrsPassID; 129 130 void initializeR600VectorRegMergerPass(PassRegistry &); 131 extern char &R600VectorRegMergerID; 132 133 void initializeR600PacketizerPass(PassRegistry &); 134 extern char &R600PacketizerID; 135 136 void initializeSIFoldOperandsPass(PassRegistry &); 137 extern char &SIFoldOperandsID; 138 139 void initializeSIPeepholeSDWAPass(PassRegistry &); 140 extern char &SIPeepholeSDWAID; 141 142 void initializeSIShrinkInstructionsPass(PassRegistry&); 143 extern char &SIShrinkInstructionsID; 144 145 void initializeSIFixSGPRCopiesPass(PassRegistry &); 146 extern char &SIFixSGPRCopiesID; 147 148 void initializeSIFixVGPRCopiesPass(PassRegistry &); 149 extern char &SIFixVGPRCopiesID; 150 151 void initializeSILowerI1CopiesPass(PassRegistry &); 152 extern char &SILowerI1CopiesID; 153 154 void initializeSILowerSGPRSpillsPass(PassRegistry &); 155 extern char &SILowerSGPRSpillsID; 156 157 void initializeSILoadStoreOptimizerPass(PassRegistry &); 158 extern char &SILoadStoreOptimizerID; 159 160 void initializeSIWholeQuadModePass(PassRegistry &); 161 extern char &SIWholeQuadModeID; 162 163 void initializeSILowerControlFlowPass(PassRegistry &); 164 extern char &SILowerControlFlowID; 165 166 void initializeSIRemoveShortExecBranchesPass(PassRegistry &); 167 extern char &SIRemoveShortExecBranchesID; 168 169 void initializeSIPreEmitPeepholePass(PassRegistry &); 170 extern char &SIPreEmitPeepholeID; 171 172 void initializeSIInsertSkipsPass(PassRegistry &); 173 extern char &SIInsertSkipsPassID; 174 175 void initializeSIOptimizeExecMaskingPass(PassRegistry &); 176 extern char &SIOptimizeExecMaskingID; 177 178 void initializeSIPreAllocateWWMRegsPass(PassRegistry &); 179 extern char &SIPreAllocateWWMRegsID; 180 181 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &); 182 extern char &AMDGPUSimplifyLibCallsID; 183 184 void initializeAMDGPUUseNativeCallsPass(PassRegistry &); 185 extern char &AMDGPUUseNativeCallsID; 186 187 void initializeSIAddIMGInitPass(PassRegistry &); 188 extern char &SIAddIMGInitID; 189 190 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &); 191 extern char &AMDGPUPerfHintAnalysisID; 192 193 // Passes common to R600 and SI 194 FunctionPass *createAMDGPUPromoteAlloca(); 195 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 196 extern char &AMDGPUPromoteAllocaID; 197 198 FunctionPass *createAMDGPUPromoteAllocaToVector(); 199 void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry&); 200 extern char &AMDGPUPromoteAllocaToVectorID; 201 202 Pass *createAMDGPUStructurizeCFGPass(); 203 FunctionPass *createAMDGPUISelDag( 204 TargetMachine *TM = nullptr, 205 CodeGenOpt::Level OptLevel = CodeGenOpt::Default); 206 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true); 207 ModulePass *createR600OpenCLImageTypeLoweringPass(); 208 FunctionPass *createAMDGPUAnnotateUniformValues(); 209 210 ModulePass *createAMDGPUPrintfRuntimeBinding(); 211 void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&); 212 extern char &AMDGPUPrintfRuntimeBindingID; 213 214 ModulePass* createAMDGPUUnifyMetadataPass(); 215 void initializeAMDGPUUnifyMetadataPass(PassRegistry&); 216 extern char &AMDGPUUnifyMetadataID; 217 218 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&); 219 extern char &SIOptimizeExecMaskingPreRAID; 220 221 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 222 extern char &AMDGPUAnnotateUniformValuesPassID; 223 224 void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 225 extern char &AMDGPUCodeGenPrepareID; 226 227 void initializeAMDGPULateCodeGenPreparePass(PassRegistry &); 228 extern char &AMDGPULateCodeGenPrepareID; 229 230 void initializeSIAnnotateControlFlowPass(PassRegistry&); 231 extern char &SIAnnotateControlFlowPassID; 232 233 void initializeSIMemoryLegalizerPass(PassRegistry&); 234 extern char &SIMemoryLegalizerID; 235 236 void initializeSIModeRegisterPass(PassRegistry&); 237 extern char &SIModeRegisterID; 238 239 void initializeSIInsertHardClausesPass(PassRegistry &); 240 extern char &SIInsertHardClausesID; 241 242 void initializeSIInsertWaitcntsPass(PassRegistry&); 243 extern char &SIInsertWaitcntsID; 244 245 void initializeSIFormMemoryClausesPass(PassRegistry&); 246 extern char &SIFormMemoryClausesID; 247 248 void initializeSIPostRABundlerPass(PassRegistry&); 249 extern char &SIPostRABundlerID; 250 251 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&); 252 extern char &AMDGPUUnifyDivergentExitNodesID; 253 254 ImmutablePass *createAMDGPUAAWrapperPass(); 255 void initializeAMDGPUAAWrapperPassPass(PassRegistry&); 256 ImmutablePass *createAMDGPUExternalAAWrapperPass(); 257 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&); 258 259 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &); 260 261 Pass *createAMDGPUFunctionInliningPass(); 262 void initializeAMDGPUInlinerPass(PassRegistry&); 263 264 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass(); 265 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &); 266 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID; 267 268 void initializeGCNRegBankReassignPass(PassRegistry &); 269 extern char &GCNRegBankReassignID; 270 271 void initializeGCNNSAReassignPass(PassRegistry &); 272 extern char &GCNNSAReassignID; 273 274 namespace AMDGPU { 275 enum TargetIndex { 276 TI_CONSTDATA_START, 277 TI_SCRATCH_RSRC_DWORD0, 278 TI_SCRATCH_RSRC_DWORD1, 279 TI_SCRATCH_RSRC_DWORD2, 280 TI_SCRATCH_RSRC_DWORD3 281 }; 282 } 283 284 /// OpenCL uses address spaces to differentiate between 285 /// various memory regions on the hardware. On the CPU 286 /// all of the address spaces point to the same memory, 287 /// however on the GPU, each address space points to 288 /// a separate piece of memory that is unique from other 289 /// memory locations. 290 namespace AMDGPUAS { 291 enum : unsigned { 292 // The maximum value for flat, generic, local, private, constant and region. 293 MAX_AMDGPU_ADDRESS = 7, 294 295 FLAT_ADDRESS = 0, ///< Address space for flat memory. 296 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 297 REGION_ADDRESS = 2, ///< Address space for region memory. (GDS) 298 299 CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2). 300 LOCAL_ADDRESS = 3, ///< Address space for local memory. 301 PRIVATE_ADDRESS = 5, ///< Address space for private memory. 302 303 CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory. 304 305 BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers. 306 307 /// Address space for direct addressible parameter memory (CONST0). 308 PARAM_D_ADDRESS = 6, 309 /// Address space for indirect addressible parameter memory (VTX1). 310 PARAM_I_ADDRESS = 7, 311 312 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on 313 // this order to be able to dynamically index a constant buffer, for 314 // example: 315 // 316 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 317 318 CONSTANT_BUFFER_0 = 8, 319 CONSTANT_BUFFER_1 = 9, 320 CONSTANT_BUFFER_2 = 10, 321 CONSTANT_BUFFER_3 = 11, 322 CONSTANT_BUFFER_4 = 12, 323 CONSTANT_BUFFER_5 = 13, 324 CONSTANT_BUFFER_6 = 14, 325 CONSTANT_BUFFER_7 = 15, 326 CONSTANT_BUFFER_8 = 16, 327 CONSTANT_BUFFER_9 = 17, 328 CONSTANT_BUFFER_10 = 18, 329 CONSTANT_BUFFER_11 = 19, 330 CONSTANT_BUFFER_12 = 20, 331 CONSTANT_BUFFER_13 = 21, 332 CONSTANT_BUFFER_14 = 22, 333 CONSTANT_BUFFER_15 = 23, 334 335 // Some places use this if the address space can't be determined. 336 UNKNOWN_ADDRESS_SPACE = ~0u, 337 }; 338 } 339 340 namespace AMDGPU { 341 342 // FIXME: Missing constant_32bit 343 inline bool isFlatGlobalAddrSpace(unsigned AS) { 344 return AS == AMDGPUAS::GLOBAL_ADDRESS || 345 AS == AMDGPUAS::FLAT_ADDRESS || 346 AS == AMDGPUAS::CONSTANT_ADDRESS || 347 AS > AMDGPUAS::MAX_AMDGPU_ADDRESS; 348 } 349 } 350 351 } // End namespace llvm 352 353 #endif 354