1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 13 14 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 15 #include "llvm/Target/TargetMachine.h" 16 17 namespace llvm { 18 19 class AMDGPUTargetMachine; 20 class FunctionPass; 21 class GCNTargetMachine; 22 class ModulePass; 23 class Pass; 24 class Target; 25 class TargetMachine; 26 class PassRegistry; 27 class Module; 28 29 // R600 Passes 30 FunctionPass *createR600VectorRegMerger(); 31 FunctionPass *createR600ExpandSpecialInstrsPass(); 32 FunctionPass *createR600EmitClauseMarkers(); 33 FunctionPass *createR600ClauseMergePass(); 34 FunctionPass *createR600Packetizer(); 35 FunctionPass *createR600ControlFlowFinalizer(); 36 FunctionPass *createAMDGPUCFGStructurizerPass(); 37 38 // SI Passes 39 FunctionPass *createSITypeRewriter(); 40 FunctionPass *createSIAnnotateControlFlowPass(); 41 FunctionPass *createSIFoldOperandsPass(); 42 FunctionPass *createSIPeepholeSDWAPass(); 43 FunctionPass *createSILowerI1CopiesPass(); 44 FunctionPass *createSIShrinkInstructionsPass(); 45 FunctionPass *createSILoadStoreOptimizerPass(); 46 FunctionPass *createSIWholeQuadModePass(); 47 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 48 FunctionPass *createSIFixSGPRCopiesPass(); 49 FunctionPass *createSIDebuggerInsertNopsPass(); 50 FunctionPass *createSIInsertWaitsPass(); 51 FunctionPass *createSIInsertWaitcntsPass(); 52 FunctionPass *createAMDGPUCodeGenPreparePass(); 53 FunctionPass *createAMDGPUMachineCFGStructurizerPass(); 54 55 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&); 56 extern char &AMDGPUMachineCFGStructurizerID; 57 58 void initializeAMDGPUAlwaysInlinePass(PassRegistry&); 59 60 ModulePass *createAMDGPUAnnotateKernelFeaturesPass(); 61 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 62 extern char &AMDGPUAnnotateKernelFeaturesID; 63 64 ModulePass *createAMDGPULowerIntrinsicsPass(); 65 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &); 66 extern char &AMDGPULowerIntrinsicsID; 67 68 void initializeSIFoldOperandsPass(PassRegistry &); 69 extern char &SIFoldOperandsID; 70 71 void initializeSIPeepholeSDWAPass(PassRegistry &); 72 extern char &SIPeepholeSDWAID; 73 74 void initializeSIShrinkInstructionsPass(PassRegistry&); 75 extern char &SIShrinkInstructionsID; 76 77 void initializeSIFixSGPRCopiesPass(PassRegistry &); 78 extern char &SIFixSGPRCopiesID; 79 80 void initializeSIFixVGPRCopiesPass(PassRegistry &); 81 extern char &SIFixVGPRCopiesID; 82 83 void initializeSILowerI1CopiesPass(PassRegistry &); 84 extern char &SILowerI1CopiesID; 85 86 void initializeSILoadStoreOptimizerPass(PassRegistry &); 87 extern char &SILoadStoreOptimizerID; 88 89 void initializeSIWholeQuadModePass(PassRegistry &); 90 extern char &SIWholeQuadModeID; 91 92 void initializeSILowerControlFlowPass(PassRegistry &); 93 extern char &SILowerControlFlowID; 94 95 void initializeSIInsertSkipsPass(PassRegistry &); 96 extern char &SIInsertSkipsPassID; 97 98 void initializeSIOptimizeExecMaskingPass(PassRegistry &); 99 extern char &SIOptimizeExecMaskingID; 100 101 // Passes common to R600 and SI 102 FunctionPass *createAMDGPUPromoteAlloca(); 103 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 104 extern char &AMDGPUPromoteAllocaID; 105 106 Pass *createAMDGPUStructurizeCFGPass(); 107 FunctionPass *createAMDGPUISelDag(TargetMachine &TM, 108 CodeGenOpt::Level OptLevel); 109 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true); 110 ModulePass *createAMDGPUOpenCLImageTypeLoweringPass(); 111 FunctionPass *createAMDGPUAnnotateUniformValues(); 112 113 ModulePass* createAMDGPUUnifyMetadataPass(); 114 void initializeAMDGPUUnifyMetadataPass(PassRegistry&); 115 extern char &AMDGPUUnifyMetadataID; 116 117 void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&); 118 extern char &SIFixControlFlowLiveIntervalsID; 119 120 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 121 extern char &AMDGPUAnnotateUniformValuesPassID; 122 123 void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 124 extern char &AMDGPUCodeGenPrepareID; 125 126 void initializeSIAnnotateControlFlowPass(PassRegistry&); 127 extern char &SIAnnotateControlFlowPassID; 128 129 void initializeSIDebuggerInsertNopsPass(PassRegistry&); 130 extern char &SIDebuggerInsertNopsID; 131 132 void initializeSIInsertWaitsPass(PassRegistry&); 133 extern char &SIInsertWaitsID; 134 135 void initializeSIInsertWaitcntsPass(PassRegistry&); 136 extern char &SIInsertWaitcntsID; 137 138 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&); 139 extern char &AMDGPUUnifyDivergentExitNodesID; 140 141 ImmutablePass *createAMDGPUAAWrapperPass(); 142 void initializeAMDGPUAAWrapperPassPass(PassRegistry&); 143 144 Target &getTheAMDGPUTarget(); 145 Target &getTheGCNTarget(); 146 147 namespace AMDGPU { 148 enum TargetIndex { 149 TI_CONSTDATA_START, 150 TI_SCRATCH_RSRC_DWORD0, 151 TI_SCRATCH_RSRC_DWORD1, 152 TI_SCRATCH_RSRC_DWORD2, 153 TI_SCRATCH_RSRC_DWORD3 154 }; 155 } 156 157 } // End namespace llvm 158 159 /// OpenCL uses address spaces to differentiate between 160 /// various memory regions on the hardware. On the CPU 161 /// all of the address spaces point to the same memory, 162 /// however on the GPU, each address space points to 163 /// a separate piece of memory that is unique from other 164 /// memory locations. 165 struct AMDGPUAS { 166 // The following address space values depend on the triple environment. 167 unsigned PRIVATE_ADDRESS; ///< Address space for private memory. 168 unsigned FLAT_ADDRESS; ///< Address space for flat memory. 169 unsigned REGION_ADDRESS; ///< Address space for region memory. 170 171 // The maximum value for flat, generic, local, private, constant and region. 172 const static unsigned MAX_COMMON_ADDRESS = 5; 173 174 const static unsigned GLOBAL_ADDRESS = 1; ///< Address space for global memory (RAT0, VTX0). 175 const static unsigned CONSTANT_ADDRESS = 2; ///< Address space for constant memory (VTX2) 176 const static unsigned LOCAL_ADDRESS = 3; ///< Address space for local memory. 177 const static unsigned PARAM_D_ADDRESS = 6; ///< Address space for direct addressible parameter memory (CONST0) 178 const static unsigned PARAM_I_ADDRESS = 7; ///< Address space for indirect addressible parameter memory (VTX1) 179 180 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this 181 // order to be able to dynamically index a constant buffer, for example: 182 // 183 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 184 185 const static unsigned CONSTANT_BUFFER_0 = 8; 186 const static unsigned CONSTANT_BUFFER_1 = 9; 187 const static unsigned CONSTANT_BUFFER_2 = 10; 188 const static unsigned CONSTANT_BUFFER_3 = 11; 189 const static unsigned CONSTANT_BUFFER_4 = 12; 190 const static unsigned CONSTANT_BUFFER_5 = 13; 191 const static unsigned CONSTANT_BUFFER_6 = 14; 192 const static unsigned CONSTANT_BUFFER_7 = 15; 193 const static unsigned CONSTANT_BUFFER_8 = 16; 194 const static unsigned CONSTANT_BUFFER_9 = 17; 195 const static unsigned CONSTANT_BUFFER_10 = 18; 196 const static unsigned CONSTANT_BUFFER_11 = 19; 197 const static unsigned CONSTANT_BUFFER_12 = 20; 198 const static unsigned CONSTANT_BUFFER_13 = 21; 199 const static unsigned CONSTANT_BUFFER_14 = 22; 200 const static unsigned CONSTANT_BUFFER_15 = 23; 201 202 // Some places use this if the address space can't be determined. 203 const static unsigned UNKNOWN_ADDRESS_SPACE = ~0u; 204 }; 205 206 namespace llvm { 207 namespace AMDGPU { 208 AMDGPUAS getAMDGPUAS(const Module &M); 209 AMDGPUAS getAMDGPUAS(const TargetMachine &TM); 210 AMDGPUAS getAMDGPUAS(Triple T); 211 } // namespace AMDGPU 212 } // namespace llvm 213 214 #endif 215