1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 13 14 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 15 #include "llvm/Target/TargetMachine.h" 16 17 namespace llvm { 18 19 class AMDGPUTargetMachine; 20 class FunctionPass; 21 class GCNTargetMachine; 22 class ModulePass; 23 class Pass; 24 class Target; 25 class TargetMachine; 26 class PassRegistry; 27 class Module; 28 29 // R600 Passes 30 FunctionPass *createR600VectorRegMerger(); 31 FunctionPass *createR600ExpandSpecialInstrsPass(); 32 FunctionPass *createR600EmitClauseMarkers(); 33 FunctionPass *createR600ClauseMergePass(); 34 FunctionPass *createR600Packetizer(); 35 FunctionPass *createR600ControlFlowFinalizer(); 36 FunctionPass *createAMDGPUCFGStructurizerPass(); 37 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel); 38 39 // SI Passes 40 FunctionPass *createSIAnnotateControlFlowPass(); 41 FunctionPass *createSIFoldOperandsPass(); 42 FunctionPass *createSIPeepholeSDWAPass(); 43 FunctionPass *createSILowerI1CopiesPass(); 44 FunctionPass *createSIShrinkInstructionsPass(); 45 FunctionPass *createSILoadStoreOptimizerPass(); 46 FunctionPass *createSIWholeQuadModePass(); 47 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 48 FunctionPass *createSIOptimizeExecMaskingPreRAPass(); 49 FunctionPass *createSIFixSGPRCopiesPass(); 50 FunctionPass *createSIMemoryLegalizerPass(); 51 FunctionPass *createSIDebuggerInsertNopsPass(); 52 FunctionPass *createSIInsertWaitsPass(); 53 FunctionPass *createSIInsertWaitcntsPass(); 54 FunctionPass *createSIFixWWMLivenessPass(); 55 FunctionPass *createAMDGPUSimplifyLibCallsPass(); 56 FunctionPass *createAMDGPUUseNativeCallsPass(); 57 FunctionPass *createAMDGPUCodeGenPreparePass(); 58 FunctionPass *createAMDGPUMachineCFGStructurizerPass(); 59 FunctionPass *createAMDGPURewriteOutArgumentsPass(); 60 61 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&); 62 63 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&); 64 extern char &AMDGPUMachineCFGStructurizerID; 65 66 void initializeAMDGPUAlwaysInlinePass(PassRegistry&); 67 68 Pass *createAMDGPUAnnotateKernelFeaturesPass(); 69 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 70 extern char &AMDGPUAnnotateKernelFeaturesID; 71 72 ModulePass *createAMDGPULowerIntrinsicsPass(); 73 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &); 74 extern char &AMDGPULowerIntrinsicsID; 75 76 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &); 77 extern char &AMDGPURewriteOutArgumentsID; 78 79 void initializeR600ClauseMergePassPass(PassRegistry &); 80 extern char &R600ClauseMergePassID; 81 82 void initializeR600ControlFlowFinalizerPass(PassRegistry &); 83 extern char &R600ControlFlowFinalizerID; 84 85 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &); 86 extern char &R600ExpandSpecialInstrsPassID; 87 88 void initializeR600VectorRegMergerPass(PassRegistry &); 89 extern char &R600VectorRegMergerID; 90 91 void initializeR600PacketizerPass(PassRegistry &); 92 extern char &R600PacketizerID; 93 94 void initializeSIFoldOperandsPass(PassRegistry &); 95 extern char &SIFoldOperandsID; 96 97 void initializeSIPeepholeSDWAPass(PassRegistry &); 98 extern char &SIPeepholeSDWAID; 99 100 void initializeSIShrinkInstructionsPass(PassRegistry&); 101 extern char &SIShrinkInstructionsID; 102 103 void initializeSIFixSGPRCopiesPass(PassRegistry &); 104 extern char &SIFixSGPRCopiesID; 105 106 void initializeSIFixVGPRCopiesPass(PassRegistry &); 107 extern char &SIFixVGPRCopiesID; 108 109 void initializeSILowerI1CopiesPass(PassRegistry &); 110 extern char &SILowerI1CopiesID; 111 112 void initializeSILoadStoreOptimizerPass(PassRegistry &); 113 extern char &SILoadStoreOptimizerID; 114 115 void initializeSIWholeQuadModePass(PassRegistry &); 116 extern char &SIWholeQuadModeID; 117 118 void initializeSILowerControlFlowPass(PassRegistry &); 119 extern char &SILowerControlFlowID; 120 121 void initializeSIInsertSkipsPass(PassRegistry &); 122 extern char &SIInsertSkipsPassID; 123 124 void initializeSIOptimizeExecMaskingPass(PassRegistry &); 125 extern char &SIOptimizeExecMaskingID; 126 127 void initializeSIFixWWMLivenessPass(PassRegistry &); 128 extern char &SIFixWWMLivenessID; 129 130 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &); 131 extern char &AMDGPUSimplifyLibCallsID; 132 133 void initializeAMDGPUUseNativeCallsPass(PassRegistry &); 134 extern char &AMDGPUUseNativeCallsID; 135 136 // Passes common to R600 and SI 137 FunctionPass *createAMDGPUPromoteAlloca(); 138 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 139 extern char &AMDGPUPromoteAllocaID; 140 141 Pass *createAMDGPUStructurizeCFGPass(); 142 FunctionPass *createAMDGPUISelDag( 143 TargetMachine *TM = nullptr, 144 CodeGenOpt::Level OptLevel = CodeGenOpt::Default); 145 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true); 146 ModulePass *createAMDGPUOpenCLImageTypeLoweringPass(); 147 FunctionPass *createAMDGPUAnnotateUniformValues(); 148 149 ModulePass* createAMDGPUUnifyMetadataPass(); 150 void initializeAMDGPUUnifyMetadataPass(PassRegistry&); 151 extern char &AMDGPUUnifyMetadataID; 152 153 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&); 154 extern char &SIOptimizeExecMaskingPreRAID; 155 156 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 157 extern char &AMDGPUAnnotateUniformValuesPassID; 158 159 void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 160 extern char &AMDGPUCodeGenPrepareID; 161 162 void initializeSIAnnotateControlFlowPass(PassRegistry&); 163 extern char &SIAnnotateControlFlowPassID; 164 165 void initializeSIMemoryLegalizerPass(PassRegistry&); 166 extern char &SIMemoryLegalizerID; 167 168 void initializeSIDebuggerInsertNopsPass(PassRegistry&); 169 extern char &SIDebuggerInsertNopsID; 170 171 void initializeSIInsertWaitsPass(PassRegistry&); 172 extern char &SIInsertWaitsID; 173 174 void initializeSIInsertWaitcntsPass(PassRegistry&); 175 extern char &SIInsertWaitcntsID; 176 177 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&); 178 extern char &AMDGPUUnifyDivergentExitNodesID; 179 180 ImmutablePass *createAMDGPUAAWrapperPass(); 181 void initializeAMDGPUAAWrapperPassPass(PassRegistry&); 182 183 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &); 184 185 Pass *createAMDGPUFunctionInliningPass(); 186 void initializeAMDGPUInlinerPass(PassRegistry&); 187 188 Target &getTheAMDGPUTarget(); 189 Target &getTheGCNTarget(); 190 191 namespace AMDGPU { 192 enum TargetIndex { 193 TI_CONSTDATA_START, 194 TI_SCRATCH_RSRC_DWORD0, 195 TI_SCRATCH_RSRC_DWORD1, 196 TI_SCRATCH_RSRC_DWORD2, 197 TI_SCRATCH_RSRC_DWORD3 198 }; 199 } 200 201 } // End namespace llvm 202 203 /// OpenCL uses address spaces to differentiate between 204 /// various memory regions on the hardware. On the CPU 205 /// all of the address spaces point to the same memory, 206 /// however on the GPU, each address space points to 207 /// a separate piece of memory that is unique from other 208 /// memory locations. 209 struct AMDGPUAS { 210 // The following address space values depend on the triple environment. 211 unsigned PRIVATE_ADDRESS; ///< Address space for private memory. 212 unsigned FLAT_ADDRESS; ///< Address space for flat memory. 213 unsigned REGION_ADDRESS; ///< Address space for region memory. 214 215 // The maximum value for flat, generic, local, private, constant and region. 216 const static unsigned MAX_COMMON_ADDRESS = 5; 217 218 const static unsigned GLOBAL_ADDRESS = 1; ///< Address space for global memory (RAT0, VTX0). 219 const static unsigned CONSTANT_ADDRESS = 2; ///< Address space for constant memory (VTX2) 220 const static unsigned LOCAL_ADDRESS = 3; ///< Address space for local memory. 221 const static unsigned PARAM_D_ADDRESS = 6; ///< Address space for direct addressible parameter memory (CONST0) 222 const static unsigned PARAM_I_ADDRESS = 7; ///< Address space for indirect addressible parameter memory (VTX1) 223 224 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this 225 // order to be able to dynamically index a constant buffer, for example: 226 // 227 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 228 229 const static unsigned CONSTANT_BUFFER_0 = 8; 230 const static unsigned CONSTANT_BUFFER_1 = 9; 231 const static unsigned CONSTANT_BUFFER_2 = 10; 232 const static unsigned CONSTANT_BUFFER_3 = 11; 233 const static unsigned CONSTANT_BUFFER_4 = 12; 234 const static unsigned CONSTANT_BUFFER_5 = 13; 235 const static unsigned CONSTANT_BUFFER_6 = 14; 236 const static unsigned CONSTANT_BUFFER_7 = 15; 237 const static unsigned CONSTANT_BUFFER_8 = 16; 238 const static unsigned CONSTANT_BUFFER_9 = 17; 239 const static unsigned CONSTANT_BUFFER_10 = 18; 240 const static unsigned CONSTANT_BUFFER_11 = 19; 241 const static unsigned CONSTANT_BUFFER_12 = 20; 242 const static unsigned CONSTANT_BUFFER_13 = 21; 243 const static unsigned CONSTANT_BUFFER_14 = 22; 244 const static unsigned CONSTANT_BUFFER_15 = 23; 245 246 // Some places use this if the address space can't be determined. 247 const static unsigned UNKNOWN_ADDRESS_SPACE = ~0u; 248 }; 249 250 namespace llvm { 251 namespace AMDGPU { 252 AMDGPUAS getAMDGPUAS(const Module &M); 253 AMDGPUAS getAMDGPUAS(const TargetMachine &TM); 254 AMDGPUAS getAMDGPUAS(Triple T); 255 } // namespace AMDGPU 256 } // namespace llvm 257 258 #endif 259