1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 13 14 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 15 #include "llvm/Target/TargetMachine.h" 16 17 namespace llvm { 18 19 class AMDGPUTargetMachine; 20 class FunctionPass; 21 class GCNTargetMachine; 22 class ModulePass; 23 class Pass; 24 class Target; 25 class TargetMachine; 26 class TargetOptions; 27 class PassRegistry; 28 class Module; 29 30 // R600 Passes 31 FunctionPass *createR600VectorRegMerger(); 32 FunctionPass *createR600ExpandSpecialInstrsPass(); 33 FunctionPass *createR600EmitClauseMarkers(); 34 FunctionPass *createR600ClauseMergePass(); 35 FunctionPass *createR600Packetizer(); 36 FunctionPass *createR600ControlFlowFinalizer(); 37 FunctionPass *createAMDGPUCFGStructurizerPass(); 38 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel); 39 40 // SI Passes 41 FunctionPass *createSIAnnotateControlFlowPass(); 42 FunctionPass *createSIFoldOperandsPass(); 43 FunctionPass *createSIPeepholeSDWAPass(); 44 FunctionPass *createSILowerI1CopiesPass(); 45 FunctionPass *createSIShrinkInstructionsPass(); 46 FunctionPass *createSILoadStoreOptimizerPass(); 47 FunctionPass *createSIWholeQuadModePass(); 48 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 49 FunctionPass *createSIOptimizeExecMaskingPreRAPass(); 50 FunctionPass *createSIFixSGPRCopiesPass(); 51 FunctionPass *createSIMemoryLegalizerPass(); 52 FunctionPass *createSIDebuggerInsertNopsPass(); 53 FunctionPass *createSIInsertWaitsPass(); 54 FunctionPass *createSIInsertWaitcntsPass(); 55 FunctionPass *createSIFixWWMLivenessPass(); 56 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &); 57 FunctionPass *createAMDGPUUseNativeCallsPass(); 58 FunctionPass *createAMDGPUCodeGenPreparePass(); 59 FunctionPass *createAMDGPUMachineCFGStructurizerPass(); 60 FunctionPass *createAMDGPURewriteOutArgumentsPass(); 61 62 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&); 63 64 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&); 65 extern char &AMDGPUMachineCFGStructurizerID; 66 67 void initializeAMDGPUAlwaysInlinePass(PassRegistry&); 68 69 Pass *createAMDGPUAnnotateKernelFeaturesPass(); 70 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 71 extern char &AMDGPUAnnotateKernelFeaturesID; 72 73 ModulePass *createAMDGPULowerIntrinsicsPass(); 74 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &); 75 extern char &AMDGPULowerIntrinsicsID; 76 77 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &); 78 extern char &AMDGPURewriteOutArgumentsID; 79 80 void initializeR600ClauseMergePassPass(PassRegistry &); 81 extern char &R600ClauseMergePassID; 82 83 void initializeR600ControlFlowFinalizerPass(PassRegistry &); 84 extern char &R600ControlFlowFinalizerID; 85 86 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &); 87 extern char &R600ExpandSpecialInstrsPassID; 88 89 void initializeR600VectorRegMergerPass(PassRegistry &); 90 extern char &R600VectorRegMergerID; 91 92 void initializeR600PacketizerPass(PassRegistry &); 93 extern char &R600PacketizerID; 94 95 void initializeSIFoldOperandsPass(PassRegistry &); 96 extern char &SIFoldOperandsID; 97 98 void initializeSIPeepholeSDWAPass(PassRegistry &); 99 extern char &SIPeepholeSDWAID; 100 101 void initializeSIShrinkInstructionsPass(PassRegistry&); 102 extern char &SIShrinkInstructionsID; 103 104 void initializeSIFixSGPRCopiesPass(PassRegistry &); 105 extern char &SIFixSGPRCopiesID; 106 107 void initializeSIFixVGPRCopiesPass(PassRegistry &); 108 extern char &SIFixVGPRCopiesID; 109 110 void initializeSILowerI1CopiesPass(PassRegistry &); 111 extern char &SILowerI1CopiesID; 112 113 void initializeSILoadStoreOptimizerPass(PassRegistry &); 114 extern char &SILoadStoreOptimizerID; 115 116 void initializeSIWholeQuadModePass(PassRegistry &); 117 extern char &SIWholeQuadModeID; 118 119 void initializeSILowerControlFlowPass(PassRegistry &); 120 extern char &SILowerControlFlowID; 121 122 void initializeSIInsertSkipsPass(PassRegistry &); 123 extern char &SIInsertSkipsPassID; 124 125 void initializeSIOptimizeExecMaskingPass(PassRegistry &); 126 extern char &SIOptimizeExecMaskingID; 127 128 void initializeSIFixWWMLivenessPass(PassRegistry &); 129 extern char &SIFixWWMLivenessID; 130 131 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &); 132 extern char &AMDGPUSimplifyLibCallsID; 133 134 void initializeAMDGPUUseNativeCallsPass(PassRegistry &); 135 extern char &AMDGPUUseNativeCallsID; 136 137 // Passes common to R600 and SI 138 FunctionPass *createAMDGPUPromoteAlloca(); 139 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 140 extern char &AMDGPUPromoteAllocaID; 141 142 Pass *createAMDGPUStructurizeCFGPass(); 143 FunctionPass *createAMDGPUISelDag( 144 TargetMachine *TM = nullptr, 145 CodeGenOpt::Level OptLevel = CodeGenOpt::Default); 146 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true); 147 ModulePass *createAMDGPUOpenCLImageTypeLoweringPass(); 148 FunctionPass *createAMDGPUAnnotateUniformValues(); 149 150 ModulePass* createAMDGPUUnifyMetadataPass(); 151 void initializeAMDGPUUnifyMetadataPass(PassRegistry&); 152 extern char &AMDGPUUnifyMetadataID; 153 154 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&); 155 extern char &SIOptimizeExecMaskingPreRAID; 156 157 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 158 extern char &AMDGPUAnnotateUniformValuesPassID; 159 160 void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 161 extern char &AMDGPUCodeGenPrepareID; 162 163 void initializeSIAnnotateControlFlowPass(PassRegistry&); 164 extern char &SIAnnotateControlFlowPassID; 165 166 void initializeSIMemoryLegalizerPass(PassRegistry&); 167 extern char &SIMemoryLegalizerID; 168 169 void initializeSIDebuggerInsertNopsPass(PassRegistry&); 170 extern char &SIDebuggerInsertNopsID; 171 172 void initializeSIInsertWaitsPass(PassRegistry&); 173 extern char &SIInsertWaitsID; 174 175 void initializeSIInsertWaitcntsPass(PassRegistry&); 176 extern char &SIInsertWaitcntsID; 177 178 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&); 179 extern char &AMDGPUUnifyDivergentExitNodesID; 180 181 ImmutablePass *createAMDGPUAAWrapperPass(); 182 void initializeAMDGPUAAWrapperPassPass(PassRegistry&); 183 184 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &); 185 186 Pass *createAMDGPUFunctionInliningPass(); 187 void initializeAMDGPUInlinerPass(PassRegistry&); 188 189 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass(); 190 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &); 191 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID; 192 193 Target &getTheAMDGPUTarget(); 194 Target &getTheGCNTarget(); 195 196 namespace AMDGPU { 197 enum TargetIndex { 198 TI_CONSTDATA_START, 199 TI_SCRATCH_RSRC_DWORD0, 200 TI_SCRATCH_RSRC_DWORD1, 201 TI_SCRATCH_RSRC_DWORD2, 202 TI_SCRATCH_RSRC_DWORD3 203 }; 204 } 205 206 } // End namespace llvm 207 208 /// OpenCL uses address spaces to differentiate between 209 /// various memory regions on the hardware. On the CPU 210 /// all of the address spaces point to the same memory, 211 /// however on the GPU, each address space points to 212 /// a separate piece of memory that is unique from other 213 /// memory locations. 214 struct AMDGPUAS { 215 // The following address space values depend on the triple environment. 216 unsigned PRIVATE_ADDRESS; ///< Address space for private memory. 217 unsigned FLAT_ADDRESS; ///< Address space for flat memory. 218 unsigned REGION_ADDRESS; ///< Address space for region memory. 219 220 enum : unsigned { 221 // The maximum value for flat, generic, local, private, constant and region. 222 MAX_COMMON_ADDRESS = 5, 223 224 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 225 CONSTANT_ADDRESS = 2, ///< Address space for constant memory (VTX2) 226 LOCAL_ADDRESS = 3, ///< Address space for local memory. 227 228 CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory 229 230 /// Address space for direct addressible parameter memory (CONST0) 231 PARAM_D_ADDRESS = 6, 232 /// Address space for indirect addressible parameter memory (VTX1) 233 PARAM_I_ADDRESS = 7, 234 235 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on 236 // this order to be able to dynamically index a constant buffer, for 237 // example: 238 // 239 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 240 241 CONSTANT_BUFFER_0 = 8, 242 CONSTANT_BUFFER_1 = 9, 243 CONSTANT_BUFFER_2 = 10, 244 CONSTANT_BUFFER_3 = 11, 245 CONSTANT_BUFFER_4 = 12, 246 CONSTANT_BUFFER_5 = 13, 247 CONSTANT_BUFFER_6 = 14, 248 CONSTANT_BUFFER_7 = 15, 249 CONSTANT_BUFFER_8 = 16, 250 CONSTANT_BUFFER_9 = 17, 251 CONSTANT_BUFFER_10 = 18, 252 CONSTANT_BUFFER_11 = 19, 253 CONSTANT_BUFFER_12 = 20, 254 CONSTANT_BUFFER_13 = 21, 255 CONSTANT_BUFFER_14 = 22, 256 CONSTANT_BUFFER_15 = 23, 257 258 // Some places use this if the address space can't be determined. 259 UNKNOWN_ADDRESS_SPACE = ~0u, 260 }; 261 }; 262 263 namespace llvm { 264 namespace AMDGPU { 265 AMDGPUAS getAMDGPUAS(const Module &M); 266 AMDGPUAS getAMDGPUAS(const TargetMachine &TM); 267 AMDGPUAS getAMDGPUAS(Triple T); 268 } // namespace AMDGPU 269 } // namespace llvm 270 271 #endif 272