1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 /// \file 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12 13 #include "llvm/Target/TargetMachine.h" 14 #include "llvm/IR/IntrinsicsR600.h" // TODO: Sink this. 15 #include "llvm/IR/IntrinsicsAMDGPU.h" // TODO: Sink this. 16 17 namespace llvm { 18 19 class AMDGPUTargetMachine; 20 class FunctionPass; 21 class GCNTargetMachine; 22 class ModulePass; 23 class Pass; 24 class Target; 25 class TargetMachine; 26 class TargetOptions; 27 class PassRegistry; 28 class Module; 29 30 // GlobalISel passes 31 void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &); 32 FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone); 33 34 // R600 Passes 35 FunctionPass *createR600VectorRegMerger(); 36 FunctionPass *createR600ExpandSpecialInstrsPass(); 37 FunctionPass *createR600EmitClauseMarkers(); 38 FunctionPass *createR600ClauseMergePass(); 39 FunctionPass *createR600Packetizer(); 40 FunctionPass *createR600ControlFlowFinalizer(); 41 FunctionPass *createAMDGPUCFGStructurizerPass(); 42 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel); 43 44 // SI Passes 45 FunctionPass *createGCNDPPCombinePass(); 46 FunctionPass *createSIAnnotateControlFlowPass(); 47 FunctionPass *createSIFoldOperandsPass(); 48 FunctionPass *createSIPeepholeSDWAPass(); 49 FunctionPass *createSILowerI1CopiesPass(); 50 FunctionPass *createSIFixupVectorISelPass(); 51 FunctionPass *createSIAddIMGInitPass(); 52 FunctionPass *createSIShrinkInstructionsPass(); 53 FunctionPass *createSILoadStoreOptimizerPass(); 54 FunctionPass *createSIWholeQuadModePass(); 55 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 56 FunctionPass *createSIOptimizeExecMaskingPreRAPass(); 57 FunctionPass *createSIFixSGPRCopiesPass(); 58 FunctionPass *createSIMemoryLegalizerPass(); 59 FunctionPass *createSIInsertWaitcntsPass(); 60 FunctionPass *createSIPreAllocateWWMRegsPass(); 61 FunctionPass *createSIFormMemoryClausesPass(); 62 FunctionPass *createSIPostRABundlerPass(); 63 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &, 64 const TargetMachine *); 65 FunctionPass *createAMDGPUUseNativeCallsPass(); 66 FunctionPass *createAMDGPUCodeGenPreparePass(); 67 FunctionPass *createAMDGPUMachineCFGStructurizerPass(); 68 FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *); 69 ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *); 70 FunctionPass *createAMDGPURewriteOutArgumentsPass(); 71 FunctionPass *createSIModeRegisterPass(); 72 73 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&); 74 75 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&); 76 extern char &AMDGPUMachineCFGStructurizerID; 77 78 void initializeAMDGPUAlwaysInlinePass(PassRegistry&); 79 80 Pass *createAMDGPUAnnotateKernelFeaturesPass(); 81 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 82 extern char &AMDGPUAnnotateKernelFeaturesID; 83 84 FunctionPass *createAMDGPUAtomicOptimizerPass(); 85 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &); 86 extern char &AMDGPUAtomicOptimizerID; 87 88 ModulePass *createAMDGPULowerIntrinsicsPass(); 89 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &); 90 extern char &AMDGPULowerIntrinsicsID; 91 92 ModulePass *createAMDGPUFixFunctionBitcastsPass(); 93 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &); 94 extern char &AMDGPUFixFunctionBitcastsID; 95 96 FunctionPass *createAMDGPULowerKernelArgumentsPass(); 97 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &); 98 extern char &AMDGPULowerKernelArgumentsID; 99 100 ModulePass *createAMDGPULowerKernelAttributesPass(); 101 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &); 102 extern char &AMDGPULowerKernelAttributesID; 103 104 void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &); 105 extern char &AMDGPUPropagateAttributesEarlyID; 106 107 void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &); 108 extern char &AMDGPUPropagateAttributesLateID; 109 110 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &); 111 extern char &AMDGPURewriteOutArgumentsID; 112 113 void initializeGCNDPPCombinePass(PassRegistry &); 114 extern char &GCNDPPCombineID; 115 116 void initializeR600ClauseMergePassPass(PassRegistry &); 117 extern char &R600ClauseMergePassID; 118 119 void initializeR600ControlFlowFinalizerPass(PassRegistry &); 120 extern char &R600ControlFlowFinalizerID; 121 122 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &); 123 extern char &R600ExpandSpecialInstrsPassID; 124 125 void initializeR600VectorRegMergerPass(PassRegistry &); 126 extern char &R600VectorRegMergerID; 127 128 void initializeR600PacketizerPass(PassRegistry &); 129 extern char &R600PacketizerID; 130 131 void initializeSIFoldOperandsPass(PassRegistry &); 132 extern char &SIFoldOperandsID; 133 134 void initializeSIPeepholeSDWAPass(PassRegistry &); 135 extern char &SIPeepholeSDWAID; 136 137 void initializeSIShrinkInstructionsPass(PassRegistry&); 138 extern char &SIShrinkInstructionsID; 139 140 void initializeSIFixSGPRCopiesPass(PassRegistry &); 141 extern char &SIFixSGPRCopiesID; 142 143 void initializeSIFixVGPRCopiesPass(PassRegistry &); 144 extern char &SIFixVGPRCopiesID; 145 146 void initializeSIFixupVectorISelPass(PassRegistry &); 147 extern char &SIFixupVectorISelID; 148 149 void initializeSILowerI1CopiesPass(PassRegistry &); 150 extern char &SILowerI1CopiesID; 151 152 void initializeSILowerSGPRSpillsPass(PassRegistry &); 153 extern char &SILowerSGPRSpillsID; 154 155 void initializeSILoadStoreOptimizerPass(PassRegistry &); 156 extern char &SILoadStoreOptimizerID; 157 158 void initializeSIWholeQuadModePass(PassRegistry &); 159 extern char &SIWholeQuadModeID; 160 161 void initializeSILowerControlFlowPass(PassRegistry &); 162 extern char &SILowerControlFlowID; 163 164 void initializeSIRemoveShortExecBranchesPass(PassRegistry &); 165 extern char &SIRemoveShortExecBranchesID; 166 167 void initializeSIInsertSkipsPass(PassRegistry &); 168 extern char &SIInsertSkipsPassID; 169 170 void initializeSIOptimizeExecMaskingPass(PassRegistry &); 171 extern char &SIOptimizeExecMaskingID; 172 173 void initializeSIPreAllocateWWMRegsPass(PassRegistry &); 174 extern char &SIPreAllocateWWMRegsID; 175 176 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &); 177 extern char &AMDGPUSimplifyLibCallsID; 178 179 void initializeAMDGPUUseNativeCallsPass(PassRegistry &); 180 extern char &AMDGPUUseNativeCallsID; 181 182 void initializeSIAddIMGInitPass(PassRegistry &); 183 extern char &SIAddIMGInitID; 184 185 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &); 186 extern char &AMDGPUPerfHintAnalysisID; 187 188 // Passes common to R600 and SI 189 FunctionPass *createAMDGPUPromoteAlloca(); 190 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 191 extern char &AMDGPUPromoteAllocaID; 192 193 Pass *createAMDGPUStructurizeCFGPass(); 194 FunctionPass *createAMDGPUISelDag( 195 TargetMachine *TM = nullptr, 196 CodeGenOpt::Level OptLevel = CodeGenOpt::Default); 197 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true); 198 ModulePass *createR600OpenCLImageTypeLoweringPass(); 199 FunctionPass *createAMDGPUAnnotateUniformValues(); 200 201 ModulePass *createAMDGPUPrintfRuntimeBinding(); 202 void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&); 203 extern char &AMDGPUPrintfRuntimeBindingID; 204 205 ModulePass* createAMDGPUUnifyMetadataPass(); 206 void initializeAMDGPUUnifyMetadataPass(PassRegistry&); 207 extern char &AMDGPUUnifyMetadataID; 208 209 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&); 210 extern char &SIOptimizeExecMaskingPreRAID; 211 212 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 213 extern char &AMDGPUAnnotateUniformValuesPassID; 214 215 void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 216 extern char &AMDGPUCodeGenPrepareID; 217 218 void initializeSIAnnotateControlFlowPass(PassRegistry&); 219 extern char &SIAnnotateControlFlowPassID; 220 221 void initializeSIMemoryLegalizerPass(PassRegistry&); 222 extern char &SIMemoryLegalizerID; 223 224 void initializeSIModeRegisterPass(PassRegistry&); 225 extern char &SIModeRegisterID; 226 227 void initializeSIInsertWaitcntsPass(PassRegistry&); 228 extern char &SIInsertWaitcntsID; 229 230 void initializeSIFormMemoryClausesPass(PassRegistry&); 231 extern char &SIFormMemoryClausesID; 232 233 void initializeSIPostRABundlerPass(PassRegistry&); 234 extern char &SIPostRABundlerID; 235 236 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&); 237 extern char &AMDGPUUnifyDivergentExitNodesID; 238 239 ImmutablePass *createAMDGPUAAWrapperPass(); 240 void initializeAMDGPUAAWrapperPassPass(PassRegistry&); 241 ImmutablePass *createAMDGPUExternalAAWrapperPass(); 242 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&); 243 244 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &); 245 246 Pass *createAMDGPUFunctionInliningPass(); 247 void initializeAMDGPUInlinerPass(PassRegistry&); 248 249 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass(); 250 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &); 251 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID; 252 253 void initializeGCNRegBankReassignPass(PassRegistry &); 254 extern char &GCNRegBankReassignID; 255 256 void initializeGCNNSAReassignPass(PassRegistry &); 257 extern char &GCNNSAReassignID; 258 259 namespace AMDGPU { 260 enum TargetIndex { 261 TI_CONSTDATA_START, 262 TI_SCRATCH_RSRC_DWORD0, 263 TI_SCRATCH_RSRC_DWORD1, 264 TI_SCRATCH_RSRC_DWORD2, 265 TI_SCRATCH_RSRC_DWORD3 266 }; 267 } 268 269 } // End namespace llvm 270 271 /// OpenCL uses address spaces to differentiate between 272 /// various memory regions on the hardware. On the CPU 273 /// all of the address spaces point to the same memory, 274 /// however on the GPU, each address space points to 275 /// a separate piece of memory that is unique from other 276 /// memory locations. 277 namespace AMDGPUAS { 278 enum : unsigned { 279 // The maximum value for flat, generic, local, private, constant and region. 280 MAX_AMDGPU_ADDRESS = 7, 281 282 FLAT_ADDRESS = 0, ///< Address space for flat memory. 283 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 284 REGION_ADDRESS = 2, ///< Address space for region memory. (GDS) 285 286 CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2). 287 LOCAL_ADDRESS = 3, ///< Address space for local memory. 288 PRIVATE_ADDRESS = 5, ///< Address space for private memory. 289 290 CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory. 291 292 BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers. 293 294 /// Address space for direct addressible parameter memory (CONST0). 295 PARAM_D_ADDRESS = 6, 296 /// Address space for indirect addressible parameter memory (VTX1). 297 PARAM_I_ADDRESS = 7, 298 299 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on 300 // this order to be able to dynamically index a constant buffer, for 301 // example: 302 // 303 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 304 305 CONSTANT_BUFFER_0 = 8, 306 CONSTANT_BUFFER_1 = 9, 307 CONSTANT_BUFFER_2 = 10, 308 CONSTANT_BUFFER_3 = 11, 309 CONSTANT_BUFFER_4 = 12, 310 CONSTANT_BUFFER_5 = 13, 311 CONSTANT_BUFFER_6 = 14, 312 CONSTANT_BUFFER_7 = 15, 313 CONSTANT_BUFFER_8 = 16, 314 CONSTANT_BUFFER_9 = 17, 315 CONSTANT_BUFFER_10 = 18, 316 CONSTANT_BUFFER_11 = 19, 317 CONSTANT_BUFFER_12 = 20, 318 CONSTANT_BUFFER_13 = 21, 319 CONSTANT_BUFFER_14 = 22, 320 CONSTANT_BUFFER_15 = 23, 321 322 // Some places use this if the address space can't be determined. 323 UNKNOWN_ADDRESS_SPACE = ~0u, 324 }; 325 } 326 327 #endif 328