1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 13 14 #include "llvm/Target/TargetMachine.h" 15 16 namespace llvm { 17 18 class AMDGPUTargetMachine; 19 class FunctionPass; 20 class GCNTargetMachine; 21 class ModulePass; 22 class Pass; 23 class Target; 24 class TargetMachine; 25 class TargetOptions; 26 class PassRegistry; 27 class Module; 28 29 // R600 Passes 30 FunctionPass *createR600VectorRegMerger(); 31 FunctionPass *createR600ExpandSpecialInstrsPass(); 32 FunctionPass *createR600EmitClauseMarkers(); 33 FunctionPass *createR600ClauseMergePass(); 34 FunctionPass *createR600Packetizer(); 35 FunctionPass *createR600ControlFlowFinalizer(); 36 FunctionPass *createAMDGPUCFGStructurizerPass(); 37 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel); 38 39 // SI Passes 40 FunctionPass *createGCNDPPCombinePass(); 41 FunctionPass *createSIAnnotateControlFlowPass(); 42 FunctionPass *createSIFoldOperandsPass(); 43 FunctionPass *createSIPeepholeSDWAPass(); 44 FunctionPass *createSILowerI1CopiesPass(); 45 FunctionPass *createSIFixupVectorISelPass(); 46 FunctionPass *createSIShrinkInstructionsPass(); 47 FunctionPass *createSILoadStoreOptimizerPass(); 48 FunctionPass *createSIWholeQuadModePass(); 49 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 50 FunctionPass *createSIOptimizeExecMaskingPreRAPass(); 51 FunctionPass *createSIFixSGPRCopiesPass(); 52 FunctionPass *createSIMemoryLegalizerPass(); 53 FunctionPass *createSIDebuggerInsertNopsPass(); 54 FunctionPass *createSIInsertWaitcntsPass(); 55 FunctionPass *createSIFixWWMLivenessPass(); 56 FunctionPass *createSIFormMemoryClausesPass(); 57 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &); 58 FunctionPass *createAMDGPUUseNativeCallsPass(); 59 FunctionPass *createAMDGPUCodeGenPreparePass(); 60 FunctionPass *createAMDGPUMachineCFGStructurizerPass(); 61 FunctionPass *createAMDGPURewriteOutArgumentsPass(); 62 FunctionPass *createSIModeRegisterPass(); 63 64 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&); 65 66 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&); 67 extern char &AMDGPUMachineCFGStructurizerID; 68 69 void initializeAMDGPUAlwaysInlinePass(PassRegistry&); 70 71 Pass *createAMDGPUAnnotateKernelFeaturesPass(); 72 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 73 extern char &AMDGPUAnnotateKernelFeaturesID; 74 75 FunctionPass *createAMDGPUAtomicOptimizerPass(); 76 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &); 77 extern char &AMDGPUAtomicOptimizerID; 78 79 ModulePass *createAMDGPULowerIntrinsicsPass(); 80 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &); 81 extern char &AMDGPULowerIntrinsicsID; 82 83 ModulePass *createAMDGPUFixFunctionBitcastsPass(); 84 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &); 85 extern char &AMDGPUFixFunctionBitcastsID; 86 87 FunctionPass *createAMDGPULowerKernelArgumentsPass(); 88 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &); 89 extern char &AMDGPULowerKernelArgumentsID; 90 91 ModulePass *createAMDGPULowerKernelAttributesPass(); 92 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &); 93 extern char &AMDGPULowerKernelAttributesID; 94 95 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &); 96 extern char &AMDGPURewriteOutArgumentsID; 97 98 void initializeGCNDPPCombinePass(PassRegistry &); 99 extern char &GCNDPPCombineID; 100 101 void initializeR600ClauseMergePassPass(PassRegistry &); 102 extern char &R600ClauseMergePassID; 103 104 void initializeR600ControlFlowFinalizerPass(PassRegistry &); 105 extern char &R600ControlFlowFinalizerID; 106 107 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &); 108 extern char &R600ExpandSpecialInstrsPassID; 109 110 void initializeR600VectorRegMergerPass(PassRegistry &); 111 extern char &R600VectorRegMergerID; 112 113 void initializeR600PacketizerPass(PassRegistry &); 114 extern char &R600PacketizerID; 115 116 void initializeSIFoldOperandsPass(PassRegistry &); 117 extern char &SIFoldOperandsID; 118 119 void initializeSIPeepholeSDWAPass(PassRegistry &); 120 extern char &SIPeepholeSDWAID; 121 122 void initializeSIShrinkInstructionsPass(PassRegistry&); 123 extern char &SIShrinkInstructionsID; 124 125 void initializeSIFixSGPRCopiesPass(PassRegistry &); 126 extern char &SIFixSGPRCopiesID; 127 128 void initializeSIFixVGPRCopiesPass(PassRegistry &); 129 extern char &SIFixVGPRCopiesID; 130 131 void initializeSIFixupVectorISelPass(PassRegistry &); 132 extern char &SIFixupVectorISelID; 133 134 void initializeSILowerI1CopiesPass(PassRegistry &); 135 extern char &SILowerI1CopiesID; 136 137 void initializeSILoadStoreOptimizerPass(PassRegistry &); 138 extern char &SILoadStoreOptimizerID; 139 140 void initializeSIWholeQuadModePass(PassRegistry &); 141 extern char &SIWholeQuadModeID; 142 143 void initializeSILowerControlFlowPass(PassRegistry &); 144 extern char &SILowerControlFlowID; 145 146 void initializeSIInsertSkipsPass(PassRegistry &); 147 extern char &SIInsertSkipsPassID; 148 149 void initializeSIOptimizeExecMaskingPass(PassRegistry &); 150 extern char &SIOptimizeExecMaskingID; 151 152 void initializeSIFixWWMLivenessPass(PassRegistry &); 153 extern char &SIFixWWMLivenessID; 154 155 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &); 156 extern char &AMDGPUSimplifyLibCallsID; 157 158 void initializeAMDGPUUseNativeCallsPass(PassRegistry &); 159 extern char &AMDGPUUseNativeCallsID; 160 161 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &); 162 extern char &AMDGPUPerfHintAnalysisID; 163 164 // Passes common to R600 and SI 165 FunctionPass *createAMDGPUPromoteAlloca(); 166 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 167 extern char &AMDGPUPromoteAllocaID; 168 169 Pass *createAMDGPUStructurizeCFGPass(); 170 FunctionPass *createAMDGPUISelDag( 171 TargetMachine *TM = nullptr, 172 CodeGenOpt::Level OptLevel = CodeGenOpt::Default); 173 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true); 174 ModulePass *createR600OpenCLImageTypeLoweringPass(); 175 FunctionPass *createAMDGPUAnnotateUniformValues(); 176 177 ModulePass* createAMDGPUUnifyMetadataPass(); 178 void initializeAMDGPUUnifyMetadataPass(PassRegistry&); 179 extern char &AMDGPUUnifyMetadataID; 180 181 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&); 182 extern char &SIOptimizeExecMaskingPreRAID; 183 184 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 185 extern char &AMDGPUAnnotateUniformValuesPassID; 186 187 void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 188 extern char &AMDGPUCodeGenPrepareID; 189 190 void initializeSIAnnotateControlFlowPass(PassRegistry&); 191 extern char &SIAnnotateControlFlowPassID; 192 193 void initializeSIMemoryLegalizerPass(PassRegistry&); 194 extern char &SIMemoryLegalizerID; 195 196 void initializeSIDebuggerInsertNopsPass(PassRegistry&); 197 extern char &SIDebuggerInsertNopsID; 198 199 void initializeSIModeRegisterPass(PassRegistry&); 200 extern char &SIModeRegisterID; 201 202 void initializeSIInsertWaitcntsPass(PassRegistry&); 203 extern char &SIInsertWaitcntsID; 204 205 void initializeSIFormMemoryClausesPass(PassRegistry&); 206 extern char &SIFormMemoryClausesID; 207 208 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&); 209 extern char &AMDGPUUnifyDivergentExitNodesID; 210 211 ImmutablePass *createAMDGPUAAWrapperPass(); 212 void initializeAMDGPUAAWrapperPassPass(PassRegistry&); 213 ImmutablePass *createAMDGPUExternalAAWrapperPass(); 214 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&); 215 216 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &); 217 218 Pass *createAMDGPUFunctionInliningPass(); 219 void initializeAMDGPUInlinerPass(PassRegistry&); 220 221 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass(); 222 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &); 223 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID; 224 225 Target &getTheAMDGPUTarget(); 226 Target &getTheGCNTarget(); 227 228 namespace AMDGPU { 229 enum TargetIndex { 230 TI_CONSTDATA_START, 231 TI_SCRATCH_RSRC_DWORD0, 232 TI_SCRATCH_RSRC_DWORD1, 233 TI_SCRATCH_RSRC_DWORD2, 234 TI_SCRATCH_RSRC_DWORD3 235 }; 236 } 237 238 } // End namespace llvm 239 240 /// OpenCL uses address spaces to differentiate between 241 /// various memory regions on the hardware. On the CPU 242 /// all of the address spaces point to the same memory, 243 /// however on the GPU, each address space points to 244 /// a separate piece of memory that is unique from other 245 /// memory locations. 246 namespace AMDGPUAS { 247 enum : unsigned { 248 // The maximum value for flat, generic, local, private, constant and region. 249 MAX_AMDGPU_ADDRESS = 6, 250 251 FLAT_ADDRESS = 0, ///< Address space for flat memory. 252 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 253 REGION_ADDRESS = 2, ///< Address space for region memory. 254 255 CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2) 256 LOCAL_ADDRESS = 3, ///< Address space for local memory. 257 PRIVATE_ADDRESS = 5, ///< Address space for private memory. 258 259 CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory 260 261 /// Address space for direct addressible parameter memory (CONST0) 262 PARAM_D_ADDRESS = 6, 263 /// Address space for indirect addressible parameter memory (VTX1) 264 PARAM_I_ADDRESS = 7, 265 266 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on 267 // this order to be able to dynamically index a constant buffer, for 268 // example: 269 // 270 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 271 272 CONSTANT_BUFFER_0 = 8, 273 CONSTANT_BUFFER_1 = 9, 274 CONSTANT_BUFFER_2 = 10, 275 CONSTANT_BUFFER_3 = 11, 276 CONSTANT_BUFFER_4 = 12, 277 CONSTANT_BUFFER_5 = 13, 278 CONSTANT_BUFFER_6 = 14, 279 CONSTANT_BUFFER_7 = 15, 280 CONSTANT_BUFFER_8 = 16, 281 CONSTANT_BUFFER_9 = 17, 282 CONSTANT_BUFFER_10 = 18, 283 CONSTANT_BUFFER_11 = 19, 284 CONSTANT_BUFFER_12 = 20, 285 CONSTANT_BUFFER_13 = 21, 286 CONSTANT_BUFFER_14 = 22, 287 CONSTANT_BUFFER_15 = 23, 288 289 // Some places use this if the address space can't be determined. 290 UNKNOWN_ADDRESS_SPACE = ~0u, 291 }; 292 } 293 294 #endif 295