1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12 
13 #include "llvm/IR/PassManager.h"
14 #include "llvm/Support/CodeGen.h"
15 
16 namespace llvm {
17 
18 class FunctionPass;
19 class GCNTargetMachine;
20 class ImmutablePass;
21 class MachineFunctionPass;
22 class ModulePass;
23 class Pass;
24 class Target;
25 class TargetMachine;
26 class TargetOptions;
27 class PassRegistry;
28 class Module;
29 
30 // GlobalISel passes
31 void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);
32 FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);
33 void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &);
34 FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
35 FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone);
36 void initializeAMDGPURegBankCombinerPass(PassRegistry &);
37 
38 // R600 Passes
39 FunctionPass *createR600VectorRegMerger();
40 FunctionPass *createR600ExpandSpecialInstrsPass();
41 FunctionPass *createR600EmitClauseMarkers();
42 FunctionPass *createR600ClauseMergePass();
43 FunctionPass *createR600Packetizer();
44 FunctionPass *createR600ControlFlowFinalizer();
45 FunctionPass *createAMDGPUCFGStructurizerPass();
46 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
47 
48 // SI Passes
49 FunctionPass *createGCNDPPCombinePass();
50 FunctionPass *createSIAnnotateControlFlowPass();
51 FunctionPass *createSIFoldOperandsPass();
52 FunctionPass *createSIPeepholeSDWAPass();
53 FunctionPass *createSILowerI1CopiesPass();
54 FunctionPass *createSIShrinkInstructionsPass();
55 FunctionPass *createSILoadStoreOptimizerPass();
56 FunctionPass *createSIWholeQuadModePass();
57 FunctionPass *createSIFixControlFlowLiveIntervalsPass();
58 FunctionPass *createSIOptimizeExecMaskingPreRAPass();
59 FunctionPass *createSIOptimizeVGPRLiveRangePass();
60 FunctionPass *createSIFixSGPRCopiesPass();
61 FunctionPass *createSIMemoryLegalizerPass();
62 FunctionPass *createSIInsertWaitcntsPass();
63 FunctionPass *createSIPreAllocateWWMRegsPass();
64 FunctionPass *createSIFormMemoryClausesPass();
65 
66 FunctionPass *createSIPostRABundlerPass();
67 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetMachine *);
68 FunctionPass *createAMDGPUUseNativeCallsPass();
69 FunctionPass *createAMDGPUCodeGenPreparePass();
70 FunctionPass *createAMDGPULateCodeGenPreparePass();
71 FunctionPass *createAMDGPUMachineCFGStructurizerPass();
72 FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *);
73 ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *);
74 FunctionPass *createAMDGPURewriteOutArgumentsPass();
75 ModulePass *createAMDGPUReplaceLDSUseWithPointerPass();
76 ModulePass *createAMDGPULowerModuleLDSPass();
77 FunctionPass *createSIModeRegisterPass();
78 FunctionPass *createGCNPreRAOptimizationsPass();
79 
80 struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> {
81   AMDGPUSimplifyLibCallsPass(TargetMachine &TM) : TM(TM) {}
82   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
83 
84 private:
85   TargetMachine &TM;
86 };
87 
88 struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
89   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
90 };
91 
92 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
93 
94 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
95 extern char &AMDGPUMachineCFGStructurizerID;
96 
97 void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
98 
99 Pass *createAMDGPUAnnotateKernelFeaturesPass();
100 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
101 extern char &AMDGPUAnnotateKernelFeaturesID;
102 
103 FunctionPass *createAMDGPUAtomicOptimizerPass();
104 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
105 extern char &AMDGPUAtomicOptimizerID;
106 
107 ModulePass *createAMDGPULowerIntrinsicsPass();
108 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
109 extern char &AMDGPULowerIntrinsicsID;
110 
111 ModulePass *createAMDGPUFixFunctionBitcastsPass();
112 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &);
113 extern char &AMDGPUFixFunctionBitcastsID;
114 
115 FunctionPass *createAMDGPULowerKernelArgumentsPass();
116 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
117 extern char &AMDGPULowerKernelArgumentsID;
118 
119 ModulePass *createAMDGPULowerKernelAttributesPass();
120 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
121 extern char &AMDGPULowerKernelAttributesID;
122 
123 struct AMDGPULowerKernelAttributesPass
124     : PassInfoMixin<AMDGPULowerKernelAttributesPass> {
125   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
126 };
127 
128 void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &);
129 extern char &AMDGPUPropagateAttributesEarlyID;
130 
131 struct AMDGPUPropagateAttributesEarlyPass
132     : PassInfoMixin<AMDGPUPropagateAttributesEarlyPass> {
133   AMDGPUPropagateAttributesEarlyPass(TargetMachine &TM) : TM(TM) {}
134   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
135 
136 private:
137   TargetMachine &TM;
138 };
139 
140 void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &);
141 extern char &AMDGPUPropagateAttributesLateID;
142 
143 struct AMDGPUPropagateAttributesLatePass
144     : PassInfoMixin<AMDGPUPropagateAttributesLatePass> {
145   AMDGPUPropagateAttributesLatePass(TargetMachine &TM) : TM(TM) {}
146   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
147 
148 private:
149   TargetMachine &TM;
150 };
151 
152 void initializeAMDGPUReplaceLDSUseWithPointerPass(PassRegistry &);
153 extern char &AMDGPUReplaceLDSUseWithPointerID;
154 
155 struct AMDGPUReplaceLDSUseWithPointerPass
156     : PassInfoMixin<AMDGPUReplaceLDSUseWithPointerPass> {
157   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
158 };
159 
160 void initializeAMDGPULowerModuleLDSPass(PassRegistry &);
161 extern char &AMDGPULowerModuleLDSID;
162 
163 struct AMDGPULowerModuleLDSPass : PassInfoMixin<AMDGPULowerModuleLDSPass> {
164   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
165 };
166 
167 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
168 extern char &AMDGPURewriteOutArgumentsID;
169 
170 void initializeGCNDPPCombinePass(PassRegistry &);
171 extern char &GCNDPPCombineID;
172 
173 void initializeR600ClauseMergePassPass(PassRegistry &);
174 extern char &R600ClauseMergePassID;
175 
176 void initializeR600ControlFlowFinalizerPass(PassRegistry &);
177 extern char &R600ControlFlowFinalizerID;
178 
179 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &);
180 extern char &R600ExpandSpecialInstrsPassID;
181 
182 void initializeR600VectorRegMergerPass(PassRegistry &);
183 extern char &R600VectorRegMergerID;
184 
185 void initializeR600PacketizerPass(PassRegistry &);
186 extern char &R600PacketizerID;
187 
188 void initializeSIFoldOperandsPass(PassRegistry &);
189 extern char &SIFoldOperandsID;
190 
191 void initializeSIPeepholeSDWAPass(PassRegistry &);
192 extern char &SIPeepholeSDWAID;
193 
194 void initializeSIShrinkInstructionsPass(PassRegistry&);
195 extern char &SIShrinkInstructionsID;
196 
197 void initializeSIFixSGPRCopiesPass(PassRegistry &);
198 extern char &SIFixSGPRCopiesID;
199 
200 void initializeSIFixVGPRCopiesPass(PassRegistry &);
201 extern char &SIFixVGPRCopiesID;
202 
203 void initializeSILowerI1CopiesPass(PassRegistry &);
204 extern char &SILowerI1CopiesID;
205 
206 void initializeSILowerSGPRSpillsPass(PassRegistry &);
207 extern char &SILowerSGPRSpillsID;
208 
209 void initializeSILoadStoreOptimizerPass(PassRegistry &);
210 extern char &SILoadStoreOptimizerID;
211 
212 void initializeSIWholeQuadModePass(PassRegistry &);
213 extern char &SIWholeQuadModeID;
214 
215 void initializeSILowerControlFlowPass(PassRegistry &);
216 extern char &SILowerControlFlowID;
217 
218 void initializeSIPreEmitPeepholePass(PassRegistry &);
219 extern char &SIPreEmitPeepholeID;
220 
221 void initializeSILateBranchLoweringPass(PassRegistry &);
222 extern char &SILateBranchLoweringPassID;
223 
224 void initializeSIOptimizeExecMaskingPass(PassRegistry &);
225 extern char &SIOptimizeExecMaskingID;
226 
227 void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
228 extern char &SIPreAllocateWWMRegsID;
229 
230 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &);
231 extern char &AMDGPUSimplifyLibCallsID;
232 
233 void initializeAMDGPUUseNativeCallsPass(PassRegistry &);
234 extern char &AMDGPUUseNativeCallsID;
235 
236 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &);
237 extern char &AMDGPUPerfHintAnalysisID;
238 
239 // Passes common to R600 and SI
240 FunctionPass *createAMDGPUPromoteAlloca();
241 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
242 extern char &AMDGPUPromoteAllocaID;
243 
244 FunctionPass *createAMDGPUPromoteAllocaToVector();
245 void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry&);
246 extern char &AMDGPUPromoteAllocaToVectorID;
247 
248 struct AMDGPUPromoteAllocaPass : PassInfoMixin<AMDGPUPromoteAllocaPass> {
249   AMDGPUPromoteAllocaPass(TargetMachine &TM) : TM(TM) {}
250   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
251 
252 private:
253   TargetMachine &TM;
254 };
255 
256 struct AMDGPUPromoteAllocaToVectorPass
257     : PassInfoMixin<AMDGPUPromoteAllocaToVectorPass> {
258   AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM) : TM(TM) {}
259   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
260 
261 private:
262   TargetMachine &TM;
263 };
264 
265 Pass *createAMDGPUStructurizeCFGPass();
266 FunctionPass *createAMDGPUISelDag(
267   TargetMachine *TM = nullptr,
268   CodeGenOpt::Level OptLevel = CodeGenOpt::Default);
269 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
270 
271 struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> {
272   AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {}
273   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
274 
275 private:
276   bool GlobalOpt;
277 };
278 
279 ModulePass *createR600OpenCLImageTypeLoweringPass();
280 FunctionPass *createAMDGPUAnnotateUniformValues();
281 
282 ModulePass *createAMDGPUPrintfRuntimeBinding();
283 void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
284 extern char &AMDGPUPrintfRuntimeBindingID;
285 
286 struct AMDGPUPrintfRuntimeBindingPass
287     : PassInfoMixin<AMDGPUPrintfRuntimeBindingPass> {
288   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
289 };
290 
291 ModulePass* createAMDGPUUnifyMetadataPass();
292 void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
293 extern char &AMDGPUUnifyMetadataID;
294 
295 struct AMDGPUUnifyMetadataPass : PassInfoMixin<AMDGPUUnifyMetadataPass> {
296   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
297 };
298 
299 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
300 extern char &SIOptimizeExecMaskingPreRAID;
301 
302 void initializeSIOptimizeVGPRLiveRangePass(PassRegistry &);
303 extern char &SIOptimizeVGPRLiveRangeID;
304 
305 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
306 extern char &AMDGPUAnnotateUniformValuesPassID;
307 
308 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
309 extern char &AMDGPUCodeGenPrepareID;
310 
311 void initializeAMDGPULateCodeGenPreparePass(PassRegistry &);
312 extern char &AMDGPULateCodeGenPrepareID;
313 
314 void initializeSIAnnotateControlFlowPass(PassRegistry&);
315 extern char &SIAnnotateControlFlowPassID;
316 
317 void initializeSIMemoryLegalizerPass(PassRegistry&);
318 extern char &SIMemoryLegalizerID;
319 
320 void initializeSIModeRegisterPass(PassRegistry&);
321 extern char &SIModeRegisterID;
322 
323 void initializeSIInsertHardClausesPass(PassRegistry &);
324 extern char &SIInsertHardClausesID;
325 
326 void initializeSIInsertWaitcntsPass(PassRegistry&);
327 extern char &SIInsertWaitcntsID;
328 
329 void initializeSIFormMemoryClausesPass(PassRegistry&);
330 extern char &SIFormMemoryClausesID;
331 
332 void initializeSIPostRABundlerPass(PassRegistry&);
333 extern char &SIPostRABundlerID;
334 
335 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
336 extern char &AMDGPUUnifyDivergentExitNodesID;
337 
338 ImmutablePass *createAMDGPUAAWrapperPass();
339 void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
340 ImmutablePass *createAMDGPUExternalAAWrapperPass();
341 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
342 
343 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
344 
345 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass();
346 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &);
347 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID;
348 
349 void initializeGCNNSAReassignPass(PassRegistry &);
350 extern char &GCNNSAReassignID;
351 
352 void initializeGCNPreRAOptimizationsPass(PassRegistry &);
353 extern char &GCNPreRAOptimizationsID;
354 
355 namespace AMDGPU {
356 enum TargetIndex {
357   TI_CONSTDATA_START,
358   TI_SCRATCH_RSRC_DWORD0,
359   TI_SCRATCH_RSRC_DWORD1,
360   TI_SCRATCH_RSRC_DWORD2,
361   TI_SCRATCH_RSRC_DWORD3
362 };
363 }
364 
365 /// OpenCL uses address spaces to differentiate between
366 /// various memory regions on the hardware. On the CPU
367 /// all of the address spaces point to the same memory,
368 /// however on the GPU, each address space points to
369 /// a separate piece of memory that is unique from other
370 /// memory locations.
371 namespace AMDGPUAS {
372   enum : unsigned {
373     // The maximum value for flat, generic, local, private, constant and region.
374     MAX_AMDGPU_ADDRESS = 7,
375 
376     FLAT_ADDRESS = 0,     ///< Address space for flat memory.
377     GLOBAL_ADDRESS = 1,   ///< Address space for global memory (RAT0, VTX0).
378     REGION_ADDRESS = 2,   ///< Address space for region memory. (GDS)
379 
380     CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
381     LOCAL_ADDRESS = 3,    ///< Address space for local memory.
382     PRIVATE_ADDRESS = 5,  ///< Address space for private memory.
383 
384     CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
385 
386     BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
387 
388     /// Address space for direct addressible parameter memory (CONST0).
389     PARAM_D_ADDRESS = 6,
390     /// Address space for indirect addressible parameter memory (VTX1).
391     PARAM_I_ADDRESS = 7,
392 
393     // Do not re-order the CONSTANT_BUFFER_* enums.  Several places depend on
394     // this order to be able to dynamically index a constant buffer, for
395     // example:
396     //
397     // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
398 
399     CONSTANT_BUFFER_0 = 8,
400     CONSTANT_BUFFER_1 = 9,
401     CONSTANT_BUFFER_2 = 10,
402     CONSTANT_BUFFER_3 = 11,
403     CONSTANT_BUFFER_4 = 12,
404     CONSTANT_BUFFER_5 = 13,
405     CONSTANT_BUFFER_6 = 14,
406     CONSTANT_BUFFER_7 = 15,
407     CONSTANT_BUFFER_8 = 16,
408     CONSTANT_BUFFER_9 = 17,
409     CONSTANT_BUFFER_10 = 18,
410     CONSTANT_BUFFER_11 = 19,
411     CONSTANT_BUFFER_12 = 20,
412     CONSTANT_BUFFER_13 = 21,
413     CONSTANT_BUFFER_14 = 22,
414     CONSTANT_BUFFER_15 = 23,
415 
416     // Some places use this if the address space can't be determined.
417     UNKNOWN_ADDRESS_SPACE = ~0u,
418   };
419 }
420 
421 namespace AMDGPU {
422 
423 // FIXME: Missing constant_32bit
424 inline bool isFlatGlobalAddrSpace(unsigned AS) {
425   return AS == AMDGPUAS::GLOBAL_ADDRESS ||
426          AS == AMDGPUAS::FLAT_ADDRESS ||
427          AS == AMDGPUAS::CONSTANT_ADDRESS ||
428          AS > AMDGPUAS::MAX_AMDGPU_ADDRESS;
429 }
430 }
431 
432 } // End namespace llvm
433 
434 #endif
435