1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #ifndef LLVM_LIB_TARGET_R600_AMDGPU_H 12 #define LLVM_LIB_TARGET_R600_AMDGPU_H 13 14 #include "llvm/Support/TargetRegistry.h" 15 #include "llvm/Target/TargetMachine.h" 16 17 namespace llvm { 18 19 class AMDGPUInstrPrinter; 20 class AMDGPUSubtarget; 21 class AMDGPUTargetMachine; 22 class FunctionPass; 23 struct MachineSchedContext; 24 class MCAsmInfo; 25 class raw_ostream; 26 class ScheduleDAGInstrs; 27 class Target; 28 class TargetMachine; 29 30 // R600 Passes 31 FunctionPass *createR600VectorRegMerger(TargetMachine &tm); 32 FunctionPass *createR600TextureIntrinsicsReplacer(); 33 FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm); 34 FunctionPass *createR600EmitClauseMarkers(); 35 FunctionPass *createR600ClauseMergePass(TargetMachine &tm); 36 FunctionPass *createR600Packetizer(TargetMachine &tm); 37 FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm); 38 FunctionPass *createAMDGPUCFGStructurizerPass(); 39 40 // SI Passes 41 FunctionPass *createSITypeRewriter(); 42 FunctionPass *createSIAnnotateControlFlowPass(); 43 FunctionPass *createSIFoldOperandsPass(); 44 FunctionPass *createSILowerI1CopiesPass(); 45 FunctionPass *createSIShrinkInstructionsPass(); 46 FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm); 47 FunctionPass *createSILowerControlFlowPass(); 48 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 49 FunctionPass *createSIFixSGPRCopiesPass(); 50 FunctionPass *createSIFixSGPRLiveRangesPass(); 51 FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS); 52 FunctionPass *createSIInsertWaitsPass(); 53 54 ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C); 55 56 ModulePass *createAMDGPUAnnotateKernelFeaturesPass(); 57 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 58 extern char &AMDGPUAnnotateKernelFeaturesID; 59 60 void initializeSIFoldOperandsPass(PassRegistry &); 61 extern char &SIFoldOperandsID; 62 63 void initializeSIFixSGPRCopiesPass(PassRegistry &); 64 extern char &SIFixSGPRCopiesID; 65 66 void initializeSILowerI1CopiesPass(PassRegistry &); 67 extern char &SILowerI1CopiesID; 68 69 void initializeSILoadStoreOptimizerPass(PassRegistry &); 70 extern char &SILoadStoreOptimizerID; 71 72 void initializeSILowerControlFlowPass(PassRegistry &); 73 extern char &SILowerControlFlowPassID; 74 75 76 // Passes common to R600 and SI 77 FunctionPass *createAMDGPUPromoteAlloca(const TargetMachine *TM = nullptr); 78 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 79 extern char &AMDGPUPromoteAllocaID; 80 81 FunctionPass *createAMDGPUAddDivergenceMetadata(const AMDGPUSubtarget &ST); 82 Pass *createAMDGPUStructurizeCFGPass(); 83 FunctionPass *createAMDGPUISelDag(TargetMachine &tm); 84 ModulePass *createAMDGPUAlwaysInlinePass(); 85 ModulePass *createAMDGPUOpenCLImageTypeLoweringPass(); 86 FunctionPass *createAMDGPUAnnotateUniformValues(); 87 88 void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&); 89 extern char &SIFixControlFlowLiveIntervalsID; 90 91 void initializeSIFixSGPRLiveRangesPass(PassRegistry&); 92 extern char &SIFixSGPRLiveRangesID; 93 94 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 95 extern char &AMDGPUAnnotateUniformValuesPassID; 96 97 void initializeSIAnnotateControlFlowPass(PassRegistry&); 98 extern char &SIAnnotateControlFlowPassID; 99 100 void initializeSIInsertWaitsPass(PassRegistry&); 101 extern char &SIInsertWaitsID; 102 103 extern Target TheAMDGPUTarget; 104 extern Target TheGCNTarget; 105 106 namespace AMDGPU { 107 enum TargetIndex { 108 TI_CONSTDATA_START, 109 TI_SCRATCH_RSRC_DWORD0, 110 TI_SCRATCH_RSRC_DWORD1, 111 TI_SCRATCH_RSRC_DWORD2, 112 TI_SCRATCH_RSRC_DWORD3 113 }; 114 } 115 116 } // End namespace llvm 117 118 namespace ShaderType { 119 enum Type { 120 PIXEL = 0, 121 VERTEX = 1, 122 GEOMETRY = 2, 123 COMPUTE = 3 124 }; 125 } 126 127 /// OpenCL uses address spaces to differentiate between 128 /// various memory regions on the hardware. On the CPU 129 /// all of the address spaces point to the same memory, 130 /// however on the GPU, each address space points to 131 /// a separate piece of memory that is unique from other 132 /// memory locations. 133 namespace AMDGPUAS { 134 enum AddressSpaces : unsigned { 135 PRIVATE_ADDRESS = 0, ///< Address space for private memory. 136 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 137 CONSTANT_ADDRESS = 2, ///< Address space for constant memory 138 LOCAL_ADDRESS = 3, ///< Address space for local memory. 139 FLAT_ADDRESS = 4, ///< Address space for flat memory. 140 REGION_ADDRESS = 5, ///< Address space for region memory. 141 PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0) 142 PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1) 143 144 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this 145 // order to be able to dynamically index a constant buffer, for example: 146 // 147 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 148 149 CONSTANT_BUFFER_0 = 8, 150 CONSTANT_BUFFER_1 = 9, 151 CONSTANT_BUFFER_2 = 10, 152 CONSTANT_BUFFER_3 = 11, 153 CONSTANT_BUFFER_4 = 12, 154 CONSTANT_BUFFER_5 = 13, 155 CONSTANT_BUFFER_6 = 14, 156 CONSTANT_BUFFER_7 = 15, 157 CONSTANT_BUFFER_8 = 16, 158 CONSTANT_BUFFER_9 = 17, 159 CONSTANT_BUFFER_10 = 18, 160 CONSTANT_BUFFER_11 = 19, 161 CONSTANT_BUFFER_12 = 20, 162 CONSTANT_BUFFER_13 = 21, 163 CONSTANT_BUFFER_14 = 22, 164 CONSTANT_BUFFER_15 = 23, 165 ADDRESS_NONE = 24, ///< Address space for unknown memory. 166 LAST_ADDRESS = ADDRESS_NONE, 167 168 // Some places use this if the address space can't be determined. 169 UNKNOWN_ADDRESS_SPACE = ~0u 170 }; 171 172 } // namespace AMDGPUAS 173 174 #endif 175