1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 13 14 #include "llvm/Target/TargetMachine.h" 15 16 namespace llvm { 17 18 class AMDGPUTargetMachine; 19 class FunctionPass; 20 class GCNTargetMachine; 21 class ModulePass; 22 class Pass; 23 class Target; 24 class TargetMachine; 25 class TargetOptions; 26 class PassRegistry; 27 class Module; 28 29 // R600 Passes 30 FunctionPass *createR600VectorRegMerger(); 31 FunctionPass *createR600ExpandSpecialInstrsPass(); 32 FunctionPass *createR600EmitClauseMarkers(); 33 FunctionPass *createR600ClauseMergePass(); 34 FunctionPass *createR600Packetizer(); 35 FunctionPass *createR600ControlFlowFinalizer(); 36 FunctionPass *createAMDGPUCFGStructurizerPass(); 37 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel); 38 39 // SI Passes 40 FunctionPass *createGCNDPPCombinePass(); 41 FunctionPass *createSIAnnotateControlFlowPass(); 42 FunctionPass *createSIFoldOperandsPass(); 43 FunctionPass *createSIPeepholeSDWAPass(); 44 FunctionPass *createSILowerI1CopiesPass(); 45 FunctionPass *createSIFixupVectorISelPass(); 46 FunctionPass *createSIShrinkInstructionsPass(); 47 FunctionPass *createSILoadStoreOptimizerPass(); 48 FunctionPass *createSIWholeQuadModePass(); 49 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 50 FunctionPass *createSIOptimizeExecMaskingPreRAPass(); 51 FunctionPass *createSIFixSGPRCopiesPass(); 52 FunctionPass *createSIMemoryLegalizerPass(); 53 FunctionPass *createSIDebuggerInsertNopsPass(); 54 FunctionPass *createSIInsertWaitcntsPass(); 55 FunctionPass *createSIFixWWMLivenessPass(); 56 FunctionPass *createSIFormMemoryClausesPass(); 57 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &); 58 FunctionPass *createAMDGPUUseNativeCallsPass(); 59 FunctionPass *createAMDGPUCodeGenPreparePass(); 60 FunctionPass *createAMDGPUMachineCFGStructurizerPass(); 61 FunctionPass *createAMDGPURewriteOutArgumentsPass(); 62 63 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&); 64 65 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&); 66 extern char &AMDGPUMachineCFGStructurizerID; 67 68 void initializeAMDGPUAlwaysInlinePass(PassRegistry&); 69 70 Pass *createAMDGPUAnnotateKernelFeaturesPass(); 71 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 72 extern char &AMDGPUAnnotateKernelFeaturesID; 73 74 FunctionPass *createAMDGPUAtomicOptimizerPass(); 75 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &); 76 extern char &AMDGPUAtomicOptimizerID; 77 78 ModulePass *createAMDGPULowerIntrinsicsPass(); 79 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &); 80 extern char &AMDGPULowerIntrinsicsID; 81 82 ModulePass *createAMDGPUFixFunctionBitcastsPass(); 83 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &); 84 extern char &AMDGPUFixFunctionBitcastsID; 85 86 FunctionPass *createAMDGPULowerKernelArgumentsPass(); 87 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &); 88 extern char &AMDGPULowerKernelArgumentsID; 89 90 ModulePass *createAMDGPULowerKernelAttributesPass(); 91 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &); 92 extern char &AMDGPULowerKernelAttributesID; 93 94 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &); 95 extern char &AMDGPURewriteOutArgumentsID; 96 97 void initializeGCNDPPCombinePass(PassRegistry &); 98 extern char &GCNDPPCombineID; 99 100 void initializeR600ClauseMergePassPass(PassRegistry &); 101 extern char &R600ClauseMergePassID; 102 103 void initializeR600ControlFlowFinalizerPass(PassRegistry &); 104 extern char &R600ControlFlowFinalizerID; 105 106 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &); 107 extern char &R600ExpandSpecialInstrsPassID; 108 109 void initializeR600VectorRegMergerPass(PassRegistry &); 110 extern char &R600VectorRegMergerID; 111 112 void initializeR600PacketizerPass(PassRegistry &); 113 extern char &R600PacketizerID; 114 115 void initializeSIFoldOperandsPass(PassRegistry &); 116 extern char &SIFoldOperandsID; 117 118 void initializeSIPeepholeSDWAPass(PassRegistry &); 119 extern char &SIPeepholeSDWAID; 120 121 void initializeSIShrinkInstructionsPass(PassRegistry&); 122 extern char &SIShrinkInstructionsID; 123 124 void initializeSIFixSGPRCopiesPass(PassRegistry &); 125 extern char &SIFixSGPRCopiesID; 126 127 void initializeSIFixVGPRCopiesPass(PassRegistry &); 128 extern char &SIFixVGPRCopiesID; 129 130 void initializeSIFixupVectorISelPass(PassRegistry &); 131 extern char &SIFixupVectorISelID; 132 133 void initializeSILowerI1CopiesPass(PassRegistry &); 134 extern char &SILowerI1CopiesID; 135 136 void initializeSILoadStoreOptimizerPass(PassRegistry &); 137 extern char &SILoadStoreOptimizerID; 138 139 void initializeSIWholeQuadModePass(PassRegistry &); 140 extern char &SIWholeQuadModeID; 141 142 void initializeSILowerControlFlowPass(PassRegistry &); 143 extern char &SILowerControlFlowID; 144 145 void initializeSIInsertSkipsPass(PassRegistry &); 146 extern char &SIInsertSkipsPassID; 147 148 void initializeSIOptimizeExecMaskingPass(PassRegistry &); 149 extern char &SIOptimizeExecMaskingID; 150 151 void initializeSIFixWWMLivenessPass(PassRegistry &); 152 extern char &SIFixWWMLivenessID; 153 154 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &); 155 extern char &AMDGPUSimplifyLibCallsID; 156 157 void initializeAMDGPUUseNativeCallsPass(PassRegistry &); 158 extern char &AMDGPUUseNativeCallsID; 159 160 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &); 161 extern char &AMDGPUPerfHintAnalysisID; 162 163 // Passes common to R600 and SI 164 FunctionPass *createAMDGPUPromoteAlloca(); 165 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 166 extern char &AMDGPUPromoteAllocaID; 167 168 Pass *createAMDGPUStructurizeCFGPass(); 169 FunctionPass *createAMDGPUISelDag( 170 TargetMachine *TM = nullptr, 171 CodeGenOpt::Level OptLevel = CodeGenOpt::Default); 172 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true); 173 ModulePass *createR600OpenCLImageTypeLoweringPass(); 174 FunctionPass *createAMDGPUAnnotateUniformValues(); 175 176 ModulePass* createAMDGPUUnifyMetadataPass(); 177 void initializeAMDGPUUnifyMetadataPass(PassRegistry&); 178 extern char &AMDGPUUnifyMetadataID; 179 180 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&); 181 extern char &SIOptimizeExecMaskingPreRAID; 182 183 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 184 extern char &AMDGPUAnnotateUniformValuesPassID; 185 186 void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 187 extern char &AMDGPUCodeGenPrepareID; 188 189 void initializeSIAnnotateControlFlowPass(PassRegistry&); 190 extern char &SIAnnotateControlFlowPassID; 191 192 void initializeSIMemoryLegalizerPass(PassRegistry&); 193 extern char &SIMemoryLegalizerID; 194 195 void initializeSIDebuggerInsertNopsPass(PassRegistry&); 196 extern char &SIDebuggerInsertNopsID; 197 198 void initializeSIInsertWaitcntsPass(PassRegistry&); 199 extern char &SIInsertWaitcntsID; 200 201 void initializeSIFormMemoryClausesPass(PassRegistry&); 202 extern char &SIFormMemoryClausesID; 203 204 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&); 205 extern char &AMDGPUUnifyDivergentExitNodesID; 206 207 ImmutablePass *createAMDGPUAAWrapperPass(); 208 void initializeAMDGPUAAWrapperPassPass(PassRegistry&); 209 ImmutablePass *createAMDGPUExternalAAWrapperPass(); 210 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&); 211 212 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &); 213 214 Pass *createAMDGPUFunctionInliningPass(); 215 void initializeAMDGPUInlinerPass(PassRegistry&); 216 217 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass(); 218 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &); 219 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID; 220 221 Target &getTheAMDGPUTarget(); 222 Target &getTheGCNTarget(); 223 224 namespace AMDGPU { 225 enum TargetIndex { 226 TI_CONSTDATA_START, 227 TI_SCRATCH_RSRC_DWORD0, 228 TI_SCRATCH_RSRC_DWORD1, 229 TI_SCRATCH_RSRC_DWORD2, 230 TI_SCRATCH_RSRC_DWORD3 231 }; 232 } 233 234 } // End namespace llvm 235 236 /// OpenCL uses address spaces to differentiate between 237 /// various memory regions on the hardware. On the CPU 238 /// all of the address spaces point to the same memory, 239 /// however on the GPU, each address space points to 240 /// a separate piece of memory that is unique from other 241 /// memory locations. 242 namespace AMDGPUAS { 243 enum : unsigned { 244 // The maximum value for flat, generic, local, private, constant and region. 245 MAX_AMDGPU_ADDRESS = 6, 246 247 FLAT_ADDRESS = 0, ///< Address space for flat memory. 248 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 249 REGION_ADDRESS = 2, ///< Address space for region memory. 250 251 CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2) 252 LOCAL_ADDRESS = 3, ///< Address space for local memory. 253 PRIVATE_ADDRESS = 5, ///< Address space for private memory. 254 255 CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory 256 257 /// Address space for direct addressible parameter memory (CONST0) 258 PARAM_D_ADDRESS = 6, 259 /// Address space for indirect addressible parameter memory (VTX1) 260 PARAM_I_ADDRESS = 7, 261 262 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on 263 // this order to be able to dynamically index a constant buffer, for 264 // example: 265 // 266 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 267 268 CONSTANT_BUFFER_0 = 8, 269 CONSTANT_BUFFER_1 = 9, 270 CONSTANT_BUFFER_2 = 10, 271 CONSTANT_BUFFER_3 = 11, 272 CONSTANT_BUFFER_4 = 12, 273 CONSTANT_BUFFER_5 = 13, 274 CONSTANT_BUFFER_6 = 14, 275 CONSTANT_BUFFER_7 = 15, 276 CONSTANT_BUFFER_8 = 16, 277 CONSTANT_BUFFER_9 = 17, 278 CONSTANT_BUFFER_10 = 18, 279 CONSTANT_BUFFER_11 = 19, 280 CONSTANT_BUFFER_12 = 20, 281 CONSTANT_BUFFER_13 = 21, 282 CONSTANT_BUFFER_14 = 22, 283 CONSTANT_BUFFER_15 = 23, 284 285 // Some places use this if the address space can't be determined. 286 UNKNOWN_ADDRESS_SPACE = ~0u, 287 }; 288 } 289 290 #endif 291