1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12 
13 #include "llvm/IR/PassManager.h"
14 #include "llvm/Support/CodeGen.h"
15 
16 namespace llvm {
17 
18 class FunctionPass;
19 class GCNTargetMachine;
20 class ImmutablePass;
21 class MachineFunctionPass;
22 class ModulePass;
23 class Pass;
24 class Target;
25 class TargetMachine;
26 class TargetOptions;
27 class PassRegistry;
28 class Module;
29 
30 // GlobalISel passes
31 void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);
32 FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);
33 void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &);
34 FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
35 FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone);
36 void initializeAMDGPURegBankCombinerPass(PassRegistry &);
37 
38 // R600 Passes
39 FunctionPass *createR600VectorRegMerger();
40 FunctionPass *createR600ExpandSpecialInstrsPass();
41 FunctionPass *createR600EmitClauseMarkers();
42 FunctionPass *createR600ClauseMergePass();
43 FunctionPass *createR600Packetizer();
44 FunctionPass *createR600ControlFlowFinalizer();
45 FunctionPass *createAMDGPUCFGStructurizerPass();
46 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
47 
48 // SI Passes
49 FunctionPass *createGCNDPPCombinePass();
50 FunctionPass *createSIAnnotateControlFlowPass();
51 FunctionPass *createSIFoldOperandsPass();
52 FunctionPass *createSIPeepholeSDWAPass();
53 FunctionPass *createSILowerI1CopiesPass();
54 FunctionPass *createSIShrinkInstructionsPass();
55 FunctionPass *createSILoadStoreOptimizerPass();
56 FunctionPass *createSIWholeQuadModePass();
57 FunctionPass *createSIFixControlFlowLiveIntervalsPass();
58 FunctionPass *createSIOptimizeExecMaskingPreRAPass();
59 FunctionPass *createSIFixSGPRCopiesPass();
60 FunctionPass *createSIMemoryLegalizerPass();
61 FunctionPass *createSIInsertWaitcntsPass();
62 FunctionPass *createSIPreAllocateWWMRegsPass();
63 FunctionPass *createSIFormMemoryClausesPass();
64 
65 FunctionPass *createSIPostRABundlerPass();
66 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetMachine *);
67 FunctionPass *createAMDGPUUseNativeCallsPass();
68 FunctionPass *createAMDGPUCodeGenPreparePass();
69 FunctionPass *createAMDGPULateCodeGenPreparePass();
70 FunctionPass *createAMDGPUMachineCFGStructurizerPass();
71 FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *);
72 ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *);
73 FunctionPass *createAMDGPURewriteOutArgumentsPass();
74 ModulePass *createAMDGPULowerModuleLDSPass();
75 FunctionPass *createSIModeRegisterPass();
76 
77 namespace AMDGPU {
78 enum RegBankReassignMode {
79   RM_VGPR = 1,
80   RM_SGPR = 2,
81   RM_BOTH = RM_VGPR | RM_SGPR
82 };
83 }
84 MachineFunctionPass *
85 createGCNRegBankReassignPass(AMDGPU::RegBankReassignMode Mode);
86 
87 struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> {
88   AMDGPUSimplifyLibCallsPass(TargetMachine &TM) : TM(TM) {}
89   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
90 
91 private:
92   TargetMachine &TM;
93 };
94 
95 struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
96   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
97 };
98 
99 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
100 
101 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
102 extern char &AMDGPUMachineCFGStructurizerID;
103 
104 void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
105 
106 Pass *createAMDGPUAnnotateKernelFeaturesPass();
107 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
108 extern char &AMDGPUAnnotateKernelFeaturesID;
109 
110 FunctionPass *createAMDGPUAtomicOptimizerPass();
111 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
112 extern char &AMDGPUAtomicOptimizerID;
113 
114 ModulePass *createAMDGPULowerIntrinsicsPass();
115 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
116 extern char &AMDGPULowerIntrinsicsID;
117 
118 ModulePass *createAMDGPUFixFunctionBitcastsPass();
119 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &);
120 extern char &AMDGPUFixFunctionBitcastsID;
121 
122 FunctionPass *createAMDGPULowerKernelArgumentsPass();
123 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
124 extern char &AMDGPULowerKernelArgumentsID;
125 
126 ModulePass *createAMDGPULowerKernelAttributesPass();
127 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
128 extern char &AMDGPULowerKernelAttributesID;
129 
130 struct AMDGPULowerKernelAttributesPass
131     : PassInfoMixin<AMDGPULowerKernelAttributesPass> {
132   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
133 };
134 
135 void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &);
136 extern char &AMDGPUPropagateAttributesEarlyID;
137 
138 struct AMDGPUPropagateAttributesEarlyPass
139     : PassInfoMixin<AMDGPUPropagateAttributesEarlyPass> {
140   AMDGPUPropagateAttributesEarlyPass(TargetMachine &TM) : TM(TM) {}
141   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
142 
143 private:
144   TargetMachine &TM;
145 };
146 
147 void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &);
148 extern char &AMDGPUPropagateAttributesLateID;
149 
150 struct AMDGPUPropagateAttributesLatePass
151     : PassInfoMixin<AMDGPUPropagateAttributesLatePass> {
152   AMDGPUPropagateAttributesLatePass(TargetMachine &TM) : TM(TM) {}
153   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
154 
155 private:
156   TargetMachine &TM;
157 };
158 
159 void initializeAMDGPULowerModuleLDSPass(PassRegistry &);
160 extern char &AMDGPULowerModuleLDSID;
161 
162 struct AMDGPULowerModuleLDSPass : PassInfoMixin<AMDGPULowerModuleLDSPass> {
163   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
164 };
165 
166 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
167 extern char &AMDGPURewriteOutArgumentsID;
168 
169 void initializeGCNDPPCombinePass(PassRegistry &);
170 extern char &GCNDPPCombineID;
171 
172 void initializeR600ClauseMergePassPass(PassRegistry &);
173 extern char &R600ClauseMergePassID;
174 
175 void initializeR600ControlFlowFinalizerPass(PassRegistry &);
176 extern char &R600ControlFlowFinalizerID;
177 
178 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &);
179 extern char &R600ExpandSpecialInstrsPassID;
180 
181 void initializeR600VectorRegMergerPass(PassRegistry &);
182 extern char &R600VectorRegMergerID;
183 
184 void initializeR600PacketizerPass(PassRegistry &);
185 extern char &R600PacketizerID;
186 
187 void initializeSIFoldOperandsPass(PassRegistry &);
188 extern char &SIFoldOperandsID;
189 
190 void initializeSIPeepholeSDWAPass(PassRegistry &);
191 extern char &SIPeepholeSDWAID;
192 
193 void initializeSIShrinkInstructionsPass(PassRegistry&);
194 extern char &SIShrinkInstructionsID;
195 
196 void initializeSIFixSGPRCopiesPass(PassRegistry &);
197 extern char &SIFixSGPRCopiesID;
198 
199 void initializeSIFixVGPRCopiesPass(PassRegistry &);
200 extern char &SIFixVGPRCopiesID;
201 
202 void initializeSILowerI1CopiesPass(PassRegistry &);
203 extern char &SILowerI1CopiesID;
204 
205 void initializeSILowerSGPRSpillsPass(PassRegistry &);
206 extern char &SILowerSGPRSpillsID;
207 
208 void initializeSILoadStoreOptimizerPass(PassRegistry &);
209 extern char &SILoadStoreOptimizerID;
210 
211 void initializeSIWholeQuadModePass(PassRegistry &);
212 extern char &SIWholeQuadModeID;
213 
214 void initializeSILowerControlFlowPass(PassRegistry &);
215 extern char &SILowerControlFlowID;
216 
217 void initializeSIPreEmitPeepholePass(PassRegistry &);
218 extern char &SIPreEmitPeepholeID;
219 
220 void initializeSILateBranchLoweringPass(PassRegistry &);
221 extern char &SILateBranchLoweringPassID;
222 
223 void initializeSIOptimizeExecMaskingPass(PassRegistry &);
224 extern char &SIOptimizeExecMaskingID;
225 
226 void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
227 extern char &SIPreAllocateWWMRegsID;
228 
229 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &);
230 extern char &AMDGPUSimplifyLibCallsID;
231 
232 void initializeAMDGPUUseNativeCallsPass(PassRegistry &);
233 extern char &AMDGPUUseNativeCallsID;
234 
235 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &);
236 extern char &AMDGPUPerfHintAnalysisID;
237 
238 // Passes common to R600 and SI
239 FunctionPass *createAMDGPUPromoteAlloca();
240 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
241 extern char &AMDGPUPromoteAllocaID;
242 
243 FunctionPass *createAMDGPUPromoteAllocaToVector();
244 void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry&);
245 extern char &AMDGPUPromoteAllocaToVectorID;
246 
247 struct AMDGPUPromoteAllocaPass : PassInfoMixin<AMDGPUPromoteAllocaPass> {
248   AMDGPUPromoteAllocaPass(TargetMachine &TM) : TM(TM) {}
249   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
250 
251 private:
252   TargetMachine &TM;
253 };
254 
255 struct AMDGPUPromoteAllocaToVectorPass
256     : PassInfoMixin<AMDGPUPromoteAllocaToVectorPass> {
257   AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM) : TM(TM) {}
258   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
259 
260 private:
261   TargetMachine &TM;
262 };
263 
264 Pass *createAMDGPUStructurizeCFGPass();
265 FunctionPass *createAMDGPUISelDag(
266   TargetMachine *TM = nullptr,
267   CodeGenOpt::Level OptLevel = CodeGenOpt::Default);
268 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
269 
270 struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> {
271   AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {}
272   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
273 
274 private:
275   bool GlobalOpt;
276 };
277 
278 ModulePass *createR600OpenCLImageTypeLoweringPass();
279 FunctionPass *createAMDGPUAnnotateUniformValues();
280 
281 ModulePass *createAMDGPUPrintfRuntimeBinding();
282 void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
283 extern char &AMDGPUPrintfRuntimeBindingID;
284 
285 struct AMDGPUPrintfRuntimeBindingPass
286     : PassInfoMixin<AMDGPUPrintfRuntimeBindingPass> {
287   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
288 };
289 
290 ModulePass* createAMDGPUUnifyMetadataPass();
291 void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
292 extern char &AMDGPUUnifyMetadataID;
293 
294 struct AMDGPUUnifyMetadataPass : PassInfoMixin<AMDGPUUnifyMetadataPass> {
295   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
296 };
297 
298 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
299 extern char &SIOptimizeExecMaskingPreRAID;
300 
301 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
302 extern char &AMDGPUAnnotateUniformValuesPassID;
303 
304 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
305 extern char &AMDGPUCodeGenPrepareID;
306 
307 void initializeAMDGPULateCodeGenPreparePass(PassRegistry &);
308 extern char &AMDGPULateCodeGenPrepareID;
309 
310 void initializeSIAnnotateControlFlowPass(PassRegistry&);
311 extern char &SIAnnotateControlFlowPassID;
312 
313 void initializeSIMemoryLegalizerPass(PassRegistry&);
314 extern char &SIMemoryLegalizerID;
315 
316 void initializeSIModeRegisterPass(PassRegistry&);
317 extern char &SIModeRegisterID;
318 
319 void initializeSIInsertHardClausesPass(PassRegistry &);
320 extern char &SIInsertHardClausesID;
321 
322 void initializeSIInsertWaitcntsPass(PassRegistry&);
323 extern char &SIInsertWaitcntsID;
324 
325 void initializeSIFormMemoryClausesPass(PassRegistry&);
326 extern char &SIFormMemoryClausesID;
327 
328 void initializeSIPostRABundlerPass(PassRegistry&);
329 extern char &SIPostRABundlerID;
330 
331 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
332 extern char &AMDGPUUnifyDivergentExitNodesID;
333 
334 ImmutablePass *createAMDGPUAAWrapperPass();
335 void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
336 ImmutablePass *createAMDGPUExternalAAWrapperPass();
337 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
338 
339 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
340 
341 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass();
342 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &);
343 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID;
344 
345 void initializeGCNRegBankReassignPass(PassRegistry &);
346 extern char &GCNRegBankReassignID;
347 
348 void initializeGCNNSAReassignPass(PassRegistry &);
349 extern char &GCNNSAReassignID;
350 
351 namespace AMDGPU {
352 enum TargetIndex {
353   TI_CONSTDATA_START,
354   TI_SCRATCH_RSRC_DWORD0,
355   TI_SCRATCH_RSRC_DWORD1,
356   TI_SCRATCH_RSRC_DWORD2,
357   TI_SCRATCH_RSRC_DWORD3
358 };
359 }
360 
361 /// OpenCL uses address spaces to differentiate between
362 /// various memory regions on the hardware. On the CPU
363 /// all of the address spaces point to the same memory,
364 /// however on the GPU, each address space points to
365 /// a separate piece of memory that is unique from other
366 /// memory locations.
367 namespace AMDGPUAS {
368   enum : unsigned {
369     // The maximum value for flat, generic, local, private, constant and region.
370     MAX_AMDGPU_ADDRESS = 7,
371 
372     FLAT_ADDRESS = 0,     ///< Address space for flat memory.
373     GLOBAL_ADDRESS = 1,   ///< Address space for global memory (RAT0, VTX0).
374     REGION_ADDRESS = 2,   ///< Address space for region memory. (GDS)
375 
376     CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
377     LOCAL_ADDRESS = 3,    ///< Address space for local memory.
378     PRIVATE_ADDRESS = 5,  ///< Address space for private memory.
379 
380     CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
381 
382     BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
383 
384     /// Address space for direct addressible parameter memory (CONST0).
385     PARAM_D_ADDRESS = 6,
386     /// Address space for indirect addressible parameter memory (VTX1).
387     PARAM_I_ADDRESS = 7,
388 
389     // Do not re-order the CONSTANT_BUFFER_* enums.  Several places depend on
390     // this order to be able to dynamically index a constant buffer, for
391     // example:
392     //
393     // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
394 
395     CONSTANT_BUFFER_0 = 8,
396     CONSTANT_BUFFER_1 = 9,
397     CONSTANT_BUFFER_2 = 10,
398     CONSTANT_BUFFER_3 = 11,
399     CONSTANT_BUFFER_4 = 12,
400     CONSTANT_BUFFER_5 = 13,
401     CONSTANT_BUFFER_6 = 14,
402     CONSTANT_BUFFER_7 = 15,
403     CONSTANT_BUFFER_8 = 16,
404     CONSTANT_BUFFER_9 = 17,
405     CONSTANT_BUFFER_10 = 18,
406     CONSTANT_BUFFER_11 = 19,
407     CONSTANT_BUFFER_12 = 20,
408     CONSTANT_BUFFER_13 = 21,
409     CONSTANT_BUFFER_14 = 22,
410     CONSTANT_BUFFER_15 = 23,
411 
412     // Some places use this if the address space can't be determined.
413     UNKNOWN_ADDRESS_SPACE = ~0u,
414   };
415 }
416 
417 namespace AMDGPU {
418 
419 // FIXME: Missing constant_32bit
420 inline bool isFlatGlobalAddrSpace(unsigned AS) {
421   return AS == AMDGPUAS::GLOBAL_ADDRESS ||
422          AS == AMDGPUAS::FLAT_ADDRESS ||
423          AS == AMDGPUAS::CONSTANT_ADDRESS ||
424          AS > AMDGPUAS::MAX_AMDGPU_ADDRESS;
425 }
426 }
427 
428 } // End namespace llvm
429 
430 #endif
431